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1 ;; GCC machine description for Alpha synchronization instructions.
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2 ;; Copyright (C) 2005-2017 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_code_iterator FETCHOP [plus minus ior xor and])
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21 (define_code_attr fetchop_name
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111
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22 [(plus "add") (minus "sub") (ior "or") (xor "xor") (and "and")])
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0
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23 (define_code_attr fetchop_pred
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24 [(plus "add_operand") (minus "reg_or_8bit_operand")
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25 (ior "or_operand") (xor "or_operand") (and "and_operand")])
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26 (define_code_attr fetchop_constr
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27 [(plus "rKL") (minus "rI") (ior "rIN") (xor "rIN") (and "riNM")])
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28
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29
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30 (define_expand "memory_barrier"
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31 [(set (match_dup 0)
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32 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
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33 ""
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34 {
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35 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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36 MEM_VOLATILE_P (operands[0]) = 1;
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37 })
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38
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39 (define_insn "*memory_barrier"
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40 [(set (match_operand:BLK 0)
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41 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
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42 ""
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43 "mb"
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44 [(set_attr "type" "mb")])
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45
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46 (define_insn "load_locked_<mode>"
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47 [(set (match_operand:I48MODE 0 "register_operand" "=r")
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48 (unspec_volatile:I48MODE
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49 [(match_operand:I48MODE 1 "memory_operand" "m")]
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50 UNSPECV_LL))]
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51 ""
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52 "ld<modesuffix>_l %0,%1"
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53 [(set_attr "type" "ld_l")])
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54
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55 (define_insn "store_conditional_<mode>"
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56 [(set (match_operand:DI 0 "register_operand" "=r")
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57 (unspec_volatile:DI [(const_int 0)] UNSPECV_SC))
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58 (set (match_operand:I48MODE 1 "memory_operand" "=m")
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59 (match_operand:I48MODE 2 "reg_or_0_operand" "0"))]
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60 ""
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61 "st<modesuffix>_c %0,%1"
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62 [(set_attr "type" "st_c")])
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63
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64 ;; The Alpha Architecture Handbook says that it is UNPREDICTABLE whether
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111
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65 ;; the lock is cleared by a normal load or store. This means we cannot
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66 ;; expand a ll/sc sequence before reload, lest a register spill is
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67 ;; inserted inside the sequence. It is also UNPREDICTABLE whether the
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68 ;; lock is cleared by a TAKEN branch. This means that we can not expand
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69 ;; a ll/sc sequence containing a branch (i.e. compare-and-swap) until after
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70 ;; the final basic-block reordering pass.
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71
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111
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72 (define_expand "atomic_compare_and_swap<mode>"
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73 [(parallel
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74 [(set (match_operand:DI 0 "register_operand") ;; bool out
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75 (unspec_volatile:DI [(const_int 0)] UNSPECV_CMPXCHG))
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76 (set (match_operand:I48MODE 1 "register_operand") ;; val out
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77 (unspec_volatile:I48MODE [(const_int 0)] UNSPECV_CMPXCHG))
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78 (set (match_operand:I48MODE 2 "memory_operand") ;; memory
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79 (unspec_volatile:I48MODE
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80 [(match_dup 2)
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81 (match_operand:I48MODE 3 "reg_or_8bit_operand") ;; expected
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82 (match_operand:I48MODE 4 "add_operand") ;; desired
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83 (match_operand:SI 5 "const_int_operand") ;; is_weak
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84 (match_operand:SI 6 "const_int_operand") ;; succ model
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85 (match_operand:SI 7 "const_int_operand")] ;; fail model
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86 UNSPECV_CMPXCHG))])]
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87 ""
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88 {
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89 if (<MODE>mode == SImode)
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90 {
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91 operands[3] = convert_modes (DImode, SImode, operands[3], 0);
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92 operands[4] = convert_modes (DImode, SImode, operands[4], 0);
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93 }
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94 })
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95
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96 (define_insn_and_split "*atomic_compare_and_swap<mode>"
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97 [(set (match_operand:DI 0 "register_operand" "=&r") ;; bool out
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98 (unspec_volatile:DI [(const_int 0)] UNSPECV_CMPXCHG))
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99 (set (match_operand:I48MODE 1 "register_operand" "=&r") ;; val out
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100 (unspec_volatile:I48MODE [(const_int 0)] UNSPECV_CMPXCHG))
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101 (set (match_operand:I48MODE 2 "memory_operand" "+m") ;; memory
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102 (unspec_volatile:I48MODE
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103 [(match_dup 2)
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104 (match_operand:DI 3 "reg_or_8bit_operand" "rI") ;; expected
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105 (match_operand:DI 4 "add_operand" "rKL") ;; desired
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106 (match_operand:SI 5 "const_int_operand") ;; is_weak
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107 (match_operand:SI 6 "const_int_operand") ;; succ model
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108 (match_operand:SI 7 "const_int_operand")] ;; fail model
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109 UNSPECV_CMPXCHG))]
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110 ""
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111 "#"
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36
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112 "epilogue_completed"
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113 [(const_int 0)]
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114 {
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115 alpha_split_compare_and_swap (operands);
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116 DONE;
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117 }
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118 [(set_attr "type" "multi")])
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119
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120 (define_expand "atomic_compare_and_swap<mode>"
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121 [(match_operand:DI 0 "register_operand") ;; bool out
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122 (match_operand:I12MODE 1 "register_operand") ;; val out
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123 (match_operand:I12MODE 2 "mem_noofs_operand") ;; memory
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124 (match_operand:I12MODE 3 "register_operand") ;; expected
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125 (match_operand:I12MODE 4 "add_operand") ;; desired
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126 (match_operand:SI 5 "const_int_operand") ;; is_weak
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127 (match_operand:SI 6 "const_int_operand") ;; succ model
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128 (match_operand:SI 7 "const_int_operand")] ;; fail model
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129 ""
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130 {
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131 alpha_expand_compare_and_swap_12 (operands);
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132 DONE;
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133 })
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134
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135 (define_insn_and_split "atomic_compare_and_swap<mode>_1"
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136 [(set (match_operand:DI 0 "register_operand" "=&r") ;; bool out
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137 (unspec_volatile:DI [(const_int 0)] UNSPECV_CMPXCHG))
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138 (set (match_operand:DI 1 "register_operand" "=&r") ;; val out
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139 (zero_extend:DI
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140 (unspec_volatile:I12MODE [(const_int 0)] UNSPECV_CMPXCHG)))
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141 (set (match_operand:I12MODE 2 "mem_noofs_operand" "+w") ;; memory
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142 (unspec_volatile:I12MODE
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143 [(match_dup 2)
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144 (match_operand:DI 3 "reg_or_8bit_operand" "rI") ;; expected
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145 (match_operand:DI 4 "reg_or_0_operand" "rJ") ;; desired
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146 (match_operand:DI 5 "register_operand" "r") ;; align
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147 (match_operand:SI 6 "const_int_operand") ;; is_weak
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148 (match_operand:SI 7 "const_int_operand") ;; succ model
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149 (match_operand:SI 8 "const_int_operand")] ;; fail model
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150 UNSPECV_CMPXCHG))
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151 (clobber (match_scratch:DI 9 "=&r"))]
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0
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152 ""
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153 "#"
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36
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154 "epilogue_completed"
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155 [(const_int 0)]
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156 {
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157 alpha_split_compare_and_swap_12 (operands);
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158 DONE;
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159 }
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160 [(set_attr "type" "multi")])
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161
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111
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162 (define_insn_and_split "atomic_exchange<mode>"
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163 [(set (match_operand:I48MODE 0 "register_operand" "=&r") ;; output
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164 (match_operand:I48MODE 1 "memory_operand" "+m")) ;; memory
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165 (set (match_dup 1)
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166 (unspec:I48MODE
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167 [(match_operand:I48MODE 2 "add_operand" "rKL") ;; input
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168 (match_operand:SI 3 "const_int_operand")] ;; model
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169 UNSPEC_XCHG))
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170 (clobber (match_scratch:I48MODE 4 "=&r"))]
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171 ""
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172 "#"
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36
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173 "epilogue_completed"
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174 [(const_int 0)]
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175 {
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176 alpha_split_atomic_exchange (operands);
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177 DONE;
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178 }
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179 [(set_attr "type" "multi")])
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180
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111
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181 (define_expand "atomic_exchange<mode>"
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182 [(match_operand:I12MODE 0 "register_operand") ;; output
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183 (match_operand:I12MODE 1 "mem_noofs_operand") ;; memory
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184 (match_operand:I12MODE 2 "reg_or_0_operand") ;; input
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185 (match_operand:SI 3 "const_int_operand")] ;; model
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186 ""
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187 {
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188 alpha_expand_atomic_exchange_12 (operands);
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189 DONE;
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190 })
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191
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192 (define_insn_and_split "atomic_exchange<mode>_1"
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193 [(set (match_operand:DI 0 "register_operand" "=&r") ;; output
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194 (zero_extend:DI
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195 (match_operand:I12MODE 1 "mem_noofs_operand" "+w"))) ;; memory
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196 (set (match_dup 1)
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111
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197 (unspec:I12MODE
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198 [(match_operand:DI 2 "reg_or_8bit_operand" "rI") ;; input
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199 (match_operand:DI 3 "register_operand" "r") ;; align
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200 (match_operand:SI 4 "const_int_operand")] ;; model
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201 UNSPEC_XCHG))
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202 (clobber (match_scratch:DI 5 "=&r"))]
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203 ""
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204 "#"
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205 "epilogue_completed"
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206 [(const_int 0)]
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207 {
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208 alpha_split_atomic_exchange_12 (operands);
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209 DONE;
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210 }
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211 [(set_attr "type" "multi")])
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212
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213 (define_insn_and_split "atomic_<fetchop_name><mode>"
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214 [(set (match_operand:I48MODE 0 "memory_operand" "+m")
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215 (unspec:I48MODE
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216 [(FETCHOP:I48MODE (match_dup 0)
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217 (match_operand:I48MODE 1 "<fetchop_pred>" "<fetchop_constr>"))
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218 (match_operand:SI 2 "const_int_operand")]
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219 UNSPEC_ATOMIC))
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220 (clobber (match_scratch:I48MODE 3 "=&r"))]
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221 ""
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222 "#"
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36
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223 "epilogue_completed"
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224 [(const_int 0)]
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225 {
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226 alpha_split_atomic_op (<CODE>, operands[0], operands[1],
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227 NULL, NULL, operands[3],
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228 (enum memmodel) INTVAL (operands[2]));
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229 DONE;
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230 }
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231 [(set_attr "type" "multi")])
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232
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111
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233 (define_insn_and_split "atomic_nand<mode>"
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234 [(set (match_operand:I48MODE 0 "memory_operand" "+m")
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235 (unspec:I48MODE
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236 [(not:I48MODE
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237 (and:I48MODE (match_dup 0)
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238 (match_operand:I48MODE 1 "register_operand" "r")))
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239 (match_operand:SI 2 "const_int_operand")]
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240 UNSPEC_ATOMIC))
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241 (clobber (match_scratch:I48MODE 3 "=&r"))]
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0
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242 ""
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243 "#"
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36
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244 "epilogue_completed"
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245 [(const_int 0)]
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246 {
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247 alpha_split_atomic_op (NOT, operands[0], operands[1],
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248 NULL, NULL, operands[3],
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249 (enum memmodel) INTVAL (operands[2]));
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250 DONE;
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251 }
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252 [(set_attr "type" "multi")])
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253
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111
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254 (define_insn_and_split "atomic_fetch_<fetchop_name><mode>"
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255 [(set (match_operand:I48MODE 0 "register_operand" "=&r")
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256 (match_operand:I48MODE 1 "memory_operand" "+m"))
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257 (set (match_dup 1)
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258 (unspec:I48MODE
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111
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259 [(FETCHOP:I48MODE (match_dup 1)
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260 (match_operand:I48MODE 2 "<fetchop_pred>" "<fetchop_constr>"))
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261 (match_operand:SI 3 "const_int_operand")]
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262 UNSPEC_ATOMIC))
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263 (clobber (match_scratch:I48MODE 4 "=&r"))]
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264 ""
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265 "#"
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266 "epilogue_completed"
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267 [(const_int 0)]
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268 {
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269 alpha_split_atomic_op (<CODE>, operands[1], operands[2],
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270 operands[0], NULL, operands[4],
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271 (enum memmodel) INTVAL (operands[3]));
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272 DONE;
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273 }
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274 [(set_attr "type" "multi")])
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275
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111
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276 (define_insn_and_split "atomic_fetch_nand<mode>"
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277 [(set (match_operand:I48MODE 0 "register_operand" "=&r")
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278 (match_operand:I48MODE 1 "memory_operand" "+m"))
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279 (set (match_dup 1)
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280 (unspec:I48MODE
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281 [(not:I48MODE
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282 (and:I48MODE (match_dup 1)
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283 (match_operand:I48MODE 2 "register_operand" "r")))
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284 (match_operand:SI 3 "const_int_operand")]
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285 UNSPEC_ATOMIC))
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286 (clobber (match_scratch:I48MODE 4 "=&r"))]
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287 ""
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288 "#"
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36
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289 "epilogue_completed"
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0
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290 [(const_int 0)]
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291 {
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111
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292 alpha_split_atomic_op (NOT, operands[1], operands[2],
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293 operands[0], NULL, operands[4],
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294 (enum memmodel) INTVAL (operands[3]));
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295 DONE;
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296 }
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297 [(set_attr "type" "multi")])
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298
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111
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299 (define_insn_and_split "atomic_<fetchop_name>_fetch<mode>"
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0
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300 [(set (match_operand:I48MODE 0 "register_operand" "=&r")
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111
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301 (FETCHOP:I48MODE
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302 (match_operand:I48MODE 1 "memory_operand" "+m")
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303 (match_operand:I48MODE 2 "<fetchop_pred>" "<fetchop_constr>")))
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0
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304 (set (match_dup 1)
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305 (unspec:I48MODE
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111
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306 [(FETCHOP:I48MODE (match_dup 1) (match_dup 2))
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307 (match_operand:SI 3 "const_int_operand")]
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308 UNSPEC_ATOMIC))
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309 (clobber (match_scratch:I48MODE 4 "=&r"))]
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0
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310 ""
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311 "#"
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36
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312 "epilogue_completed"
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0
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313 [(const_int 0)]
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314 {
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111
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315 alpha_split_atomic_op (<CODE>, operands[1], operands[2],
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316 NULL, operands[0], operands[4],
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317 (enum memmodel) INTVAL (operands[3]));
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0
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318 DONE;
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319 }
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320 [(set_attr "type" "multi")])
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111
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321
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322 (define_insn_and_split "atomic_nand_fetch<mode>"
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323 [(set (match_operand:I48MODE 0 "register_operand" "=&r")
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324 (not:I48MODE
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325 (and:I48MODE (match_operand:I48MODE 1 "memory_operand" "+m")
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326 (match_operand:I48MODE 2 "register_operand" "r"))))
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327 (set (match_dup 1)
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328 (unspec:I48MODE
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329 [(not:I48MODE (and:I48MODE (match_dup 1) (match_dup 2)))
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330 (match_operand:SI 3 "const_int_operand")]
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331 UNSPEC_ATOMIC))
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332 (clobber (match_scratch:I48MODE 4 "=&r"))]
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333 ""
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334 "#"
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335 "epilogue_completed"
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336 [(const_int 0)]
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337 {
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338 alpha_split_atomic_op (NOT, operands[1], operands[2],
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339 NULL, operands[0], operands[4],
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340 (enum memmodel) INTVAL (operands[3]));
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341 DONE;
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342 }
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343 [(set_attr "type" "multi")])
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