Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/iq2000/iq2000.h @ 111:04ced10e8804
gcc 7
| author | kono |
|---|---|
| date | Fri, 27 Oct 2017 22:46:09 +0900 |
| parents | f6334be47118 |
| children | 84e7813d76e9 |
| rev | line source |
|---|---|
| 0 | 1 /* Definitions of target machine for GNU compiler. |
| 2 Vitesse IQ2000 processors | |
| 111 | 3 Copyright (C) 2003-2017 Free Software Foundation, Inc. |
| 0 | 4 |
| 5 This file is part of GCC. | |
| 6 | |
| 7 GCC is free software; you can redistribute it and/or modify it | |
| 8 under the terms of the GNU General Public License as published | |
| 9 by the Free Software Foundation; either version 3, or (at your | |
| 10 option) any later version. | |
| 11 | |
| 12 GCC is distributed in the hope that it will be useful, but WITHOUT | |
| 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 15 License for more details. | |
| 16 | |
| 17 You should have received a copy of the GNU General Public License | |
| 18 along with GCC; see the file COPYING3. If not see | |
| 19 <http://www.gnu.org/licenses/>. */ | |
| 20 | |
| 21 /* Driver configuration. */ | |
| 22 | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
23 /* A generic LIB_SPEC with -leval and --*group tacked on. */ |
| 0 | 24 #undef LIB_SPEC |
| 25 #define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}" | |
| 26 | |
| 27 #undef STARTFILE_SPEC | |
| 28 #undef ENDFILE_SPEC | |
| 29 | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
30 #undef LINK_SPEC |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
31 #define LINK_SPEC "%{h*} %{v:-V} \ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
32 %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
33 |
| 0 | 34 |
| 35 /* Run-time target specifications. */ | |
| 36 | |
| 37 #define TARGET_CPU_CPP_BUILTINS() \ | |
| 38 do \ | |
| 39 { \ | |
| 40 builtin_define ("__iq2000__"); \ | |
| 41 builtin_assert ("cpu=iq2000"); \ | |
| 42 builtin_assert ("machine=iq2000"); \ | |
| 43 } \ | |
| 44 while (0) | |
| 45 | |
| 46 /* Macros used in the machine description to test the flags. */ | |
| 47 | |
| 48 #define TARGET_STATS 0 | |
| 49 | |
| 50 #define TARGET_DEBUG_MODE 0 | |
| 51 #define TARGET_DEBUG_A_MODE 0 | |
| 52 #define TARGET_DEBUG_B_MODE 0 | |
| 53 #define TARGET_DEBUG_C_MODE 0 | |
| 54 #define TARGET_DEBUG_D_MODE 0 | |
| 55 | |
| 56 #ifndef IQ2000_ISA_DEFAULT | |
| 57 #define IQ2000_ISA_DEFAULT 1 | |
| 58 #endif | |
| 59 | |
| 60 /* Storage Layout. */ | |
| 61 | |
| 62 #define BITS_BIG_ENDIAN 0 | |
| 63 #define BYTES_BIG_ENDIAN 1 | |
| 64 #define WORDS_BIG_ENDIAN 1 | |
| 65 #define BITS_PER_WORD 32 | |
| 66 #define MAX_BITS_PER_WORD 64 | |
| 67 #define UNITS_PER_WORD 4 | |
| 68 #define MIN_UNITS_PER_WORD 4 | |
| 69 #define POINTER_SIZE 32 | |
| 70 | |
| 71 /* Define this macro if it is advisable to hold scalars in registers | |
| 72 in a wider mode than that declared by the program. In such cases, | |
| 73 the value is constrained to be within the bounds of the declared | |
| 74 type, but kept valid in the wider mode. The signedness of the | |
| 75 extension may differ from that of the type. | |
| 76 | |
| 77 We promote any value smaller than SImode up to SImode. */ | |
| 78 | |
| 79 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
| 80 if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
| 81 && GET_MODE_SIZE (MODE) < 4) \ | |
| 82 (MODE) = SImode; | |
| 83 | |
| 84 #define PARM_BOUNDARY 32 | |
| 85 | |
| 86 #define STACK_BOUNDARY 64 | |
| 87 | |
| 88 #define FUNCTION_BOUNDARY 32 | |
| 89 | |
| 90 #define BIGGEST_ALIGNMENT 64 | |
| 91 | |
| 92 #undef DATA_ALIGNMENT | |
| 93 #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
| 94 ((((ALIGN) < BITS_PER_WORD) \ | |
| 95 && (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
| 96 || TREE_CODE (TYPE) == UNION_TYPE \ | |
| 97 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
| 98 | |
| 99 #define EMPTY_FIELD_BOUNDARY 32 | |
| 100 | |
| 101 #define STRUCTURE_SIZE_BOUNDARY 8 | |
| 102 | |
| 103 #define STRICT_ALIGNMENT 1 | |
| 104 | |
| 105 #define PCC_BITFIELD_TYPE_MATTERS 1 | |
| 106 | |
| 107 | |
| 108 /* Layout of Source Language Data Types. */ | |
| 109 | |
| 110 #define INT_TYPE_SIZE 32 | |
| 111 #define SHORT_TYPE_SIZE 16 | |
| 112 #define LONG_TYPE_SIZE 32 | |
| 113 #define LONG_LONG_TYPE_SIZE 64 | |
| 114 #define CHAR_TYPE_SIZE BITS_PER_UNIT | |
| 115 #define FLOAT_TYPE_SIZE 32 | |
| 116 #define DOUBLE_TYPE_SIZE 64 | |
| 117 #define LONG_DOUBLE_TYPE_SIZE 64 | |
| 118 #define DEFAULT_SIGNED_CHAR 1 | |
| 119 | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
120 #undef SIZE_TYPE |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
121 #define SIZE_TYPE "unsigned int" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
122 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
123 #undef PTRDIFF_TYPE |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
124 #define PTRDIFF_TYPE "int" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
125 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
126 #undef WCHAR_TYPE |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
127 #define WCHAR_TYPE "long int" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
128 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
129 #undef WCHAR_TYPE_SIZE |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
130 #define WCHAR_TYPE_SIZE BITS_PER_WORD |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
131 |
| 0 | 132 |
| 133 /* Register Basics. */ | |
| 134 | |
| 135 /* On the IQ2000, we have 32 integer registers. */ | |
| 136 #define FIRST_PSEUDO_REGISTER 33 | |
| 137 | |
| 138 #define FIXED_REGISTERS \ | |
| 139 { \ | |
| 140 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 141 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1 \ | |
| 142 } | |
| 143 | |
| 144 #define CALL_USED_REGISTERS \ | |
| 145 { \ | |
| 146 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 147 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1 \ | |
| 148 } | |
| 149 | |
| 150 | |
| 151 /* Order of allocation of registers. */ | |
| 152 | |
| 153 #define REG_ALLOC_ORDER \ | |
| 154 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ | |
| 155 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 \ | |
| 156 } | |
| 157 | |
| 158 | |
| 159 | |
| 160 #define AVOID_CCMODE_COPIES | |
| 161 | |
| 162 | |
| 163 /* Register Classes. */ | |
| 164 | |
| 165 enum reg_class | |
| 166 { | |
| 167 NO_REGS, /* No registers in set. */ | |
| 168 GR_REGS, /* Integer registers. */ | |
| 169 ALL_REGS, /* All registers. */ | |
| 170 LIM_REG_CLASSES /* Max value + 1. */ | |
| 171 }; | |
| 172 | |
| 173 #define GENERAL_REGS GR_REGS | |
| 174 | |
| 175 #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
| 176 | |
| 177 #define REG_CLASS_NAMES \ | |
| 178 { \ | |
| 179 "NO_REGS", \ | |
| 180 "GR_REGS", \ | |
| 181 "ALL_REGS" \ | |
| 182 } | |
| 183 | |
| 184 #define REG_CLASS_CONTENTS \ | |
| 185 { \ | |
| 186 { 0x00000000, 0x00000000 }, /* No registers, */ \ | |
| 187 { 0xffffffff, 0x00000000 }, /* Integer registers. */ \ | |
| 188 { 0xffffffff, 0x00000001 } /* All registers. */ \ | |
| 189 } | |
| 190 | |
| 191 #define REGNO_REG_CLASS(REGNO) \ | |
| 192 ((REGNO) <= GP_REG_LAST + 1 ? GR_REGS : NO_REGS) | |
| 193 | |
| 194 #define BASE_REG_CLASS (GR_REGS) | |
| 195 | |
| 196 #define INDEX_REG_CLASS NO_REGS | |
| 197 | |
| 198 #define REGNO_OK_FOR_INDEX_P(regno) 0 | |
| 199 | |
| 200 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ | |
| 201 ((CLASS) != ALL_REGS \ | |
| 202 ? (CLASS) \ | |
| 203 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ | |
| 204 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \ | |
| 205 ? (GR_REGS) \ | |
| 206 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \ | |
| 207 || GET_MODE (X) == VOIDmode) \ | |
| 208 ? (GR_REGS) \ | |
| 209 : (CLASS)))) | |
| 210 | |
| 211 | |
| 212 /* Basic Stack Layout. */ | |
| 213 | |
| 111 | 214 #define STACK_GROWS_DOWNWARD 1 |
| 0 | 215 |
| 216 #define FRAME_GROWS_DOWNWARD 0 | |
| 217 | |
| 218 /* Use the default value zero. */ | |
| 219 /* #define STACK_POINTER_OFFSET 0 */ | |
| 220 | |
| 221 #define FIRST_PARM_OFFSET(FNDECL) 0 | |
| 222 | |
| 223 /* The return address for the current frame is in r31 if this is a leaf | |
| 224 function. Otherwise, it is on the stack. It is at a variable offset | |
| 225 from sp/fp/ap, so we define a fake hard register rap which is a | |
| 226 pointer to the return address on the stack. This always gets eliminated | |
| 227 during reload to be either the frame pointer or the stack pointer plus | |
| 228 an offset. */ | |
| 229 | |
| 230 #define RETURN_ADDR_RTX(count, frame) \ | |
| 231 (((count) == 0) \ | |
| 232 ? (leaf_function_p () \ | |
| 233 ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31) \ | |
| 234 : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, \ | |
| 235 RETURN_ADDRESS_POINTER_REGNUM))) \ | |
| 236 : (rtx) 0) | |
| 237 | |
| 238 /* Before the prologue, RA lives in r31. */ | |
| 111 | 239 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 31) |
| 0 | 240 |
| 241 | |
| 242 /* Register That Address the Stack Frame. */ | |
| 243 | |
| 244 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29) | |
| 245 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1) | |
| 246 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 27) | |
| 247 #define ARG_POINTER_REGNUM GP_REG_FIRST | |
| 248 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM | |
| 249 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2) | |
| 250 | |
| 251 | |
| 252 /* Eliminating the Frame Pointer and the Arg Pointer. */ | |
| 253 | |
| 254 #define ELIMINABLE_REGS \ | |
| 255 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 256 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
| 257 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 258 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
| 259 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \ | |
| 260 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 261 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
| 262 | |
| 263 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
| 264 (OFFSET) = iq2000_initial_elimination_offset ((FROM), (TO)) | |
| 265 | |
| 266 /* Passing Function Arguments on the Stack. */ | |
| 267 | |
| 268 /* #define PUSH_ROUNDING(BYTES) 0 */ | |
| 269 | |
| 270 #define ACCUMULATE_OUTGOING_ARGS 1 | |
| 271 | |
| 272 #define REG_PARM_STACK_SPACE(FNDECL) 0 | |
| 273 | |
| 274 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 | |
| 275 | |
| 276 | |
| 277 /* Function Arguments in Registers. */ | |
| 278 | |
| 279 #define MAX_ARGS_IN_REGISTERS 8 | |
| 280 | |
| 281 typedef struct iq2000_args | |
| 282 { | |
| 283 int gp_reg_found; /* Whether a gp register was found yet. */ | |
| 284 unsigned int arg_number; /* Argument number. */ | |
| 285 unsigned int arg_words; /* # total words the arguments take. */ | |
| 286 unsigned int fp_arg_words; /* # words for FP args (IQ2000_EABI only). */ | |
| 287 int last_arg_fp; /* Nonzero if last arg was FP (EABI only). */ | |
| 288 int fp_code; /* Mode of FP arguments. */ | |
| 289 unsigned int num_adjusts; /* Number of adjustments made. */ | |
| 290 /* Adjustments made to args pass in regs. */ | |
| 111 | 291 rtx adjust[MAX_ARGS_IN_REGISTERS * 2]; |
| 0 | 292 } CUMULATIVE_ARGS; |
| 293 | |
| 294 /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
| 295 for a call to a function whose data type is FNTYPE. | |
| 296 For a library call, FNTYPE is 0. */ | |
| 297 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ | |
| 298 init_cumulative_args (& CUM, FNTYPE, LIBNAME) \ | |
| 299 | |
| 300 #define FUNCTION_ARG_REGNO_P(N) \ | |
| 301 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST)) | |
| 302 | |
| 303 | |
| 304 /* On the IQ2000, R2 and R3 are the only register thus used. */ | |
| 305 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
306 #define FUNCTION_VALUE_REGNO_P(N) iq2000_function_value_regno_p (N) |
| 0 | 307 |
| 308 | |
| 309 /* How Large Values are Returned. */ | |
| 310 | |
| 311 #define DEFAULT_PCC_STRUCT_RETURN 0 | |
| 312 | |
| 313 /* Function Entry and Exit. */ | |
| 314 | |
| 315 #define EXIT_IGNORE_STACK 1 | |
| 316 | |
| 317 | |
| 318 /* Generating Code for Profiling. */ | |
| 319 | |
| 320 #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
| 321 { \ | |
| 322 fprintf (FILE, "\t.set\tnoreorder\n"); \ | |
| 323 fprintf (FILE, "\t.set\tnoat\n"); \ | |
| 324 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \ | |
| 325 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \ | |
| 326 fprintf (FILE, "\tjal\t_mcount\n"); \ | |
| 327 fprintf (FILE, \ | |
| 328 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \ | |
| 329 "subu", \ | |
| 330 reg_names[STACK_POINTER_REGNUM], \ | |
| 331 reg_names[STACK_POINTER_REGNUM], \ | |
| 332 Pmode == DImode ? 16 : 8); \ | |
| 333 fprintf (FILE, "\t.set\treorder\n"); \ | |
| 334 fprintf (FILE, "\t.set\tat\n"); \ | |
| 335 } | |
| 336 | |
| 337 | |
| 338 /* Trampolines for Nested Functions. */ | |
| 339 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
340 #define TRAMPOLINE_CODE_SIZE (8*4) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
341 #define TRAMPOLINE_SIZE (TRAMPOLINE_CODE_SIZE + 2*GET_MODE_SIZE (Pmode)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
342 #define TRAMPOLINE_ALIGNMENT GET_MODE_ALIGNMENT (Pmode) |
| 0 | 343 |
| 344 | |
| 345 /* Addressing Modes. */ | |
| 346 | |
| 347 #define CONSTANT_ADDRESS_P(X) \ | |
| 348 ( (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
| 349 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ | |
| 350 || (GET_CODE (X) == CONST))) | |
| 351 | |
| 352 #define MAX_REGS_PER_ADDRESS 1 | |
| 353 | |
| 354 #define REG_OK_FOR_INDEX_P(X) 0 | |
| 355 | |
| 356 | |
| 357 /* Describing Relative Costs of Operations. */ | |
| 358 | |
| 359 #define REGISTER_MOVE_COST(MODE, FROM, TO) 2 | |
| 360 | |
| 361 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \ | |
| 362 (TO_P ? 2 : 16) | |
| 363 | |
| 364 #define BRANCH_COST(speed_p, predictable_p) 2 | |
| 365 | |
| 366 #define SLOW_BYTE_ACCESS 1 | |
| 367 | |
| 368 #define NO_FUNCTION_CSE 1 | |
| 369 | |
| 370 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \ | |
| 371 if (REG_NOTE_KIND (LINK) != 0) \ | |
| 372 (COST) = 0; /* Anti or output dependence. */ | |
| 373 | |
| 374 | |
| 375 /* Dividing the output into sections. */ | |
| 376 | |
| 377 #define TEXT_SECTION_ASM_OP "\t.text" /* Instructions. */ | |
| 378 | |
| 379 #define DATA_SECTION_ASM_OP "\t.data" /* Large data. */ | |
| 380 | |
| 381 | |
| 382 /* The Overall Framework of an Assembler File. */ | |
| 383 | |
| 384 #define ASM_COMMENT_START " #" | |
| 385 | |
| 386 #define ASM_APP_ON "#APP\n" | |
| 387 | |
| 388 #define ASM_APP_OFF "#NO_APP\n" | |
| 389 | |
| 390 | |
| 391 /* Output and Generation of Labels. */ | |
| 392 | |
| 393 #undef ASM_GENERATE_INTERNAL_LABEL | |
| 394 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
| 395 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long) (NUM)) | |
| 396 | |
| 397 #define GLOBAL_ASM_OP "\t.globl\t" | |
| 398 | |
| 399 | |
| 400 /* Output of Assembler Instructions. */ | |
| 401 | |
| 402 #define REGISTER_NAMES \ | |
| 403 { \ | |
| 404 "%0", "%1", "%2", "%3", "%4", "%5", "%6", "%7", \ | |
| 405 "%8", "%9", "%10", "%11", "%12", "%13", "%14", "%15", \ | |
| 406 "%16", "%17", "%18", "%19", "%20", "%21", "%22", "%23", \ | |
| 407 "%24", "%25", "%26", "%27", "%28", "%29", "%30", "%31", "%rap" \ | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
408 } |
| 0 | 409 |
| 410 #define ADDITIONAL_REGISTER_NAMES \ | |
| 411 { \ | |
| 412 { "%0", 0 + GP_REG_FIRST }, \ | |
| 413 { "%1", 1 + GP_REG_FIRST }, \ | |
| 414 { "%2", 2 + GP_REG_FIRST }, \ | |
| 415 { "%3", 3 + GP_REG_FIRST }, \ | |
| 416 { "%4", 4 + GP_REG_FIRST }, \ | |
| 417 { "%5", 5 + GP_REG_FIRST }, \ | |
| 418 { "%6", 6 + GP_REG_FIRST }, \ | |
| 419 { "%7", 7 + GP_REG_FIRST }, \ | |
| 420 { "%8", 8 + GP_REG_FIRST }, \ | |
| 421 { "%9", 9 + GP_REG_FIRST }, \ | |
| 422 { "%10", 10 + GP_REG_FIRST }, \ | |
| 423 { "%11", 11 + GP_REG_FIRST }, \ | |
| 424 { "%12", 12 + GP_REG_FIRST }, \ | |
| 425 { "%13", 13 + GP_REG_FIRST }, \ | |
| 426 { "%14", 14 + GP_REG_FIRST }, \ | |
| 427 { "%15", 15 + GP_REG_FIRST }, \ | |
| 428 { "%16", 16 + GP_REG_FIRST }, \ | |
| 429 { "%17", 17 + GP_REG_FIRST }, \ | |
| 430 { "%18", 18 + GP_REG_FIRST }, \ | |
| 431 { "%19", 19 + GP_REG_FIRST }, \ | |
| 432 { "%20", 20 + GP_REG_FIRST }, \ | |
| 433 { "%21", 21 + GP_REG_FIRST }, \ | |
| 434 { "%22", 22 + GP_REG_FIRST }, \ | |
| 435 { "%23", 23 + GP_REG_FIRST }, \ | |
| 436 { "%24", 24 + GP_REG_FIRST }, \ | |
| 437 { "%25", 25 + GP_REG_FIRST }, \ | |
| 438 { "%26", 26 + GP_REG_FIRST }, \ | |
| 439 { "%27", 27 + GP_REG_FIRST }, \ | |
| 440 { "%28", 28 + GP_REG_FIRST }, \ | |
| 441 { "%29", 29 + GP_REG_FIRST }, \ | |
| 442 { "%30", 27 + GP_REG_FIRST }, \ | |
| 443 { "%31", 31 + GP_REG_FIRST }, \ | |
| 444 { "%rap", 32 + GP_REG_FIRST }, \ | |
| 445 } | |
| 446 | |
| 447 /* Check if the current insn needs a nop in front of it | |
| 448 because of load delays, and also update the delay slot statistics. */ | |
| 449 | |
| 450 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ | |
| 451 final_prescan_insn (INSN, OPVEC, NOPERANDS) | |
| 452 | |
| 453 #define DBR_OUTPUT_SEQEND(STREAM) \ | |
| 454 do \ | |
| 455 { \ | |
| 456 fputs ("\n", STREAM); \ | |
| 457 } \ | |
| 458 while (0) | |
| 459 | |
| 460 #define LOCAL_LABEL_PREFIX "$" | |
| 461 | |
| 462 #define USER_LABEL_PREFIX "" | |
| 463 | |
| 464 | |
| 465 /* Output of dispatch tables. */ | |
| 466 | |
| 467 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ | |
| 468 do \ | |
| 469 { \ | |
| 470 fprintf (STREAM, "\t%s\t%sL%d\n", \ | |
| 471 Pmode == DImode ? ".dword" : ".word", \ | |
| 472 LOCAL_LABEL_PREFIX, VALUE); \ | |
| 473 } \ | |
| 474 while (0) | |
| 475 | |
| 476 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ | |
| 477 fprintf (STREAM, "\t%s\t%sL%d\n", \ | |
| 478 Pmode == DImode ? ".dword" : ".word", \ | |
| 479 LOCAL_LABEL_PREFIX, \ | |
| 480 VALUE) | |
| 481 | |
| 482 | |
| 483 /* Assembler Commands for Alignment. */ | |
| 484 | |
| 485 #undef ASM_OUTPUT_SKIP | |
| 486 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \ | |
| 487 fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n", \ | |
| 488 (unsigned HOST_WIDE_INT)(SIZE)) | |
| 489 | |
| 490 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \ | |
| 491 if ((LOG) != 0) \ | |
| 492 fprintf (STREAM, "\t.balign %d\n", 1<<(LOG)) | |
| 493 | |
| 494 | |
| 495 /* Macros Affecting all Debug Formats. */ | |
| 496 | |
| 497 #define DEBUGGER_AUTO_OFFSET(X) \ | |
| 498 iq2000_debugger_offset (X, (HOST_WIDE_INT) 0) | |
| 499 | |
| 500 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \ | |
| 501 iq2000_debugger_offset (X, (HOST_WIDE_INT) OFFSET) | |
| 502 | |
| 503 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG | |
| 504 | |
| 505 #define DWARF2_DEBUGGING_INFO 1 | |
| 506 | |
| 507 | |
| 508 /* Miscellaneous Parameters. */ | |
| 509 | |
| 510 #define CASE_VECTOR_MODE SImode | |
| 511 | |
| 111 | 512 #define WORD_REGISTER_OPERATIONS 1 |
| 0 | 513 |
| 514 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
| 515 | |
| 516 #define MOVE_MAX 4 | |
| 517 | |
| 518 #define MAX_MOVE_MAX 8 | |
| 519 | |
| 520 #define SHIFT_COUNT_TRUNCATED 1 | |
| 521 | |
| 522 #define STORE_FLAG_VALUE 1 | |
| 523 | |
| 524 #define Pmode SImode | |
| 525 | |
| 526 #define FUNCTION_MODE SImode | |
| 527 | |
| 528 /* IQ2000 external variables defined in iq2000.c. */ | |
| 529 | |
| 530 /* Comparison type. */ | |
| 531 enum cmp_type | |
| 532 { | |
| 533 CMP_SI, /* Compare four byte integers. */ | |
| 534 CMP_DI, /* Compare eight byte integers. */ | |
| 535 CMP_SF, /* Compare single precision floats. */ | |
| 536 CMP_DF, /* Compare double precision floats. */ | |
| 537 CMP_MAX /* Max comparison type. */ | |
| 538 }; | |
| 539 | |
| 540 /* Types of delay slot. */ | |
| 541 enum delay_type | |
| 542 { | |
| 543 DELAY_NONE, /* No delay slot. */ | |
| 544 DELAY_LOAD, /* Load from memory delay. */ | |
| 545 DELAY_FCMP /* Delay after doing c.<xx>.{d,s}. */ | |
| 546 }; | |
| 547 | |
| 548 /* Recast the cpu class to be the cpu attribute. */ | |
| 549 #define iq2000_cpu_attr ((enum attr_cpu) iq2000_tune) | |
| 550 | |
| 551 #define BITMASK_UPPER16 ((unsigned long) 0xffff << 16) /* 0xffff0000 */ | |
| 552 #define BITMASK_LOWER16 ((unsigned long) 0xffff) /* 0x0000ffff */ | |
| 553 | |
| 554 | |
| 555 #define GENERATE_BRANCHLIKELY (ISA_HAS_BRANCHLIKELY) | |
| 556 | |
| 557 /* Macros to decide whether certain features are available or not, | |
| 558 depending on the instruction set architecture level. */ | |
| 559 | |
| 560 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY | |
| 561 | |
| 562 /* ISA has branch likely instructions. */ | |
| 563 #define ISA_HAS_BRANCHLIKELY (iq2000_isa == 1) | |
| 564 | |
| 565 | |
| 566 #undef ASM_SPEC | |
| 567 | |
| 568 | |
| 569 /* The mapping from gcc register number to DWARF 2 CFA column number. */ | |
| 570 #define DWARF_FRAME_REGNUM(REG) (REG) | |
| 571 | |
| 572 /* The DWARF 2 CFA column which tracks the return address. */ | |
| 573 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31) | |
| 574 | |
| 575 /* Describe how we implement __builtin_eh_return. */ | |
| 576 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM) | |
| 577 | |
| 578 /* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the | |
| 579 location used to store the amount to adjust the stack. This is | |
| 580 usually a register that is available from end of the function's body | |
| 581 to the end of the epilogue. Thus, this cannot be a register used as a | |
| 582 temporary by the epilogue. | |
| 583 | |
| 584 This must be an integer register. */ | |
| 585 #define EH_RETURN_STACKADJ_REGNO 3 | |
| 586 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO) | |
| 587 | |
| 588 /* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the | |
| 589 location used to store the address the processor should jump to | |
| 590 catch exception. This is usually a registers that is available from | |
| 591 end of the function's body to the end of the epilogue. Thus, this | |
| 592 cannot be a register used as a temporary by the epilogue. | |
| 593 | |
| 594 This must be an address register. */ | |
| 595 #define EH_RETURN_HANDLER_REGNO 26 | |
| 596 #define EH_RETURN_HANDLER_RTX \ | |
| 597 gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO) | |
| 598 | |
| 599 /* Offsets recorded in opcodes are a multiple of this alignment factor. */ | |
| 600 #define DWARF_CIE_DATA_ALIGNMENT 4 | |
| 601 | |
| 602 /* For IQ2000, width of a floating point register. */ | |
| 603 #define UNITS_PER_FPREG 4 | |
| 604 | |
| 605 /* Force right-alignment for small varargs in 32 bit little_endian mode */ | |
| 606 | |
| 607 #define PAD_VARARGS_DOWN !BYTES_BIG_ENDIAN | |
| 608 | |
| 609 /* Internal macros to classify a register number as to whether it's a | |
| 610 general purpose register, a floating point register, a | |
| 611 multiply/divide register, or a status register. */ | |
| 612 | |
| 613 #define GP_REG_FIRST 0 | |
| 614 #define GP_REG_LAST 31 | |
| 615 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) | |
| 616 | |
| 617 #define RAP_REG_NUM 32 | |
| 618 #define AT_REGNUM (GP_REG_FIRST + 1) | |
| 619 | |
| 620 #define GP_REG_P(REGNO) \ | |
| 621 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) | |
| 622 | |
| 623 /* IQ2000 registers used in prologue/epilogue code when the stack frame | |
| 624 is larger than 32K bytes. These registers must come from the | |
| 625 scratch register set, and not used for passing and returning | |
| 626 arguments and any other information used in the calling sequence. */ | |
| 627 | |
| 628 #define IQ2000_TEMP1_REGNUM (GP_REG_FIRST + 12) | |
| 629 #define IQ2000_TEMP2_REGNUM (GP_REG_FIRST + 13) | |
| 630 | |
| 631 /* This macro is used later on in the file. */ | |
| 632 #define GR_REG_CLASS_P(CLASS) \ | |
| 633 ((CLASS) == GR_REGS) | |
| 634 | |
| 635 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000) | |
| 636 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000) | |
| 637 | |
| 638 /* Certain machines have the property that some registers cannot be | |
| 639 copied to some other registers without using memory. Define this | |
| 640 macro on those machines to be a C expression that is nonzero if | |
| 641 objects of mode MODE in registers of CLASS1 can only be copied to | |
| 642 registers of class CLASS2 by storing a register of CLASS1 into | |
| 643 memory and loading that memory location into a register of CLASS2. | |
| 644 | |
| 645 Do not define this macro if its value would always be zero. */ | |
| 646 | |
| 647 /* Return the maximum number of consecutive registers | |
| 648 needed to represent mode MODE in a register of class CLASS. */ | |
| 649 | |
| 650 #define CLASS_UNITS(mode, size) \ | |
| 651 ((GET_MODE_SIZE (mode) + (size) - 1) / (size)) | |
| 652 | |
| 653 /* If defined, gives a class of registers that cannot be used as the | |
| 654 operand of a SUBREG that changes the mode of the object illegally. */ | |
| 655 | |
| 656 #define CLASS_CANNOT_CHANGE_MODE 0 | |
| 657 | |
| 658 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */ | |
| 659 | |
| 660 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \ | |
| 661 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)) | |
| 662 | |
| 663 /* Make sure 4 words are always allocated on the stack. */ | |
| 664 | |
| 665 #ifndef STACK_ARGS_ADJUST | |
| 666 #define STACK_ARGS_ADJUST(SIZE) \ | |
| 667 { \ | |
| 668 if (SIZE.constant < 4 * UNITS_PER_WORD) \ | |
| 669 SIZE.constant = 4 * UNITS_PER_WORD; \ | |
| 670 } | |
| 671 #endif | |
| 672 | |
| 673 | |
| 674 /* Symbolic macros for the registers used to return integer and floating | |
| 675 point values. */ | |
| 676 | |
| 677 #define GP_RETURN (GP_REG_FIRST + 2) | |
| 678 | |
| 679 /* Symbolic macros for the first/last argument registers. */ | |
| 680 | |
| 681 #define GP_ARG_FIRST (GP_REG_FIRST + 4) | |
| 682 #define GP_ARG_LAST (GP_REG_FIRST + 11) | |
| 683 | |
| 684 #define MAX_ARGS_IN_REGISTERS 8 | |
| 685 | |
| 686 | |
| 687 /* Tell prologue and epilogue if register REGNO should be saved / restored. */ | |
| 688 | |
| 689 #define MUST_SAVE_REGISTER(regno) \ | |
| 690 ((df_regs_ever_live_p (regno) && !call_used_regs[regno]) \ | |
| 691 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \ | |
| 692 || (regno == (GP_REG_FIRST + 31) && df_regs_ever_live_p (GP_REG_FIRST + 31))) | |
| 693 | |
| 694 /* ALIGN FRAMES on double word boundaries */ | |
| 695 #ifndef IQ2000_STACK_ALIGN | |
| 696 #define IQ2000_STACK_ALIGN(LOC) (((LOC) + 7) & ~7) | |
| 697 #endif | |
| 698 | |
| 699 | |
| 700 /* These assume that REGNO is a hard or pseudo reg number. | |
| 701 They give nonzero only if REGNO is a hard reg of the suitable class | |
| 702 or a pseudo reg currently allocated to a suitable hard reg. | |
| 703 These definitions are NOT overridden anywhere. */ | |
| 704 | |
| 705 #define BASE_REG_P(regno, mode) \ | |
| 706 (GP_REG_P (regno)) | |
| 707 | |
| 708 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \ | |
| 709 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \ | |
| 710 (mode)) | |
| 711 | |
| 712 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \ | |
| 713 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode)))) | |
| 714 | |
| 715 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \ | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
716 GP_REG_OR_PSEUDO_STRICT_P ((int) (regno), (mode)) |
| 0 | 717 |
| 718 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
| 719 and check its validity for a certain class. | |
| 720 We have two alternate definitions for each of them. | |
| 721 The usual definition accepts all pseudo regs; the other rejects them all. | |
| 722 The symbol REG_OK_STRICT causes the latter definition to be used. | |
| 723 | |
| 724 Most source files want to accept pseudo regs in the hope that | |
| 725 they will get allocated to the class that the insn wants them to be in. | |
| 726 Some source files that are used after register allocation | |
| 727 need to be strict. */ | |
| 728 | |
| 729 #ifndef REG_OK_STRICT | |
| 730 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
| 731 iq2000_reg_mode_ok_for_base_p (X, MODE, 0) | |
| 732 #else | |
| 733 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
| 734 iq2000_reg_mode_ok_for_base_p (X, MODE, 1) | |
| 735 #endif | |
| 736 | |
| 737 #if 1 | |
| 738 #define GO_PRINTF(x) fprintf (stderr, (x)) | |
| 739 #define GO_PRINTF2(x,y) fprintf (stderr, (x), (y)) | |
| 740 #define GO_DEBUG_RTX(x) debug_rtx (x) | |
| 741 | |
| 742 #else | |
| 743 #define GO_PRINTF(x) | |
| 744 #define GO_PRINTF2(x,y) | |
| 745 #define GO_DEBUG_RTX(x) | |
| 746 #endif | |
| 747 | |
| 748 /* If defined, modifies the length assigned to instruction INSN as a | |
| 749 function of the context in which it is used. LENGTH is an lvalue | |
| 750 that contains the initially computed length of the insn and should | |
| 751 be updated with the correct length of the insn. */ | |
| 752 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ | |
| 753 ((LENGTH) = iq2000_adjust_insn_length ((INSN), (LENGTH))) | |
| 754 | |
| 755 | |
| 756 | |
| 757 | |
| 758 /* How to tell the debugger about changes of source files. */ | |
| 759 | |
| 760 #ifndef SET_FILE_NUMBER | |
| 761 #define SET_FILE_NUMBER() ++ num_source_filenames | |
| 762 #endif | |
| 763 | |
| 764 /* This is how to output a note the debugger telling it the line number | |
| 765 to which the following sequence of instructions corresponds. */ | |
| 766 | |
| 767 #ifndef LABEL_AFTER_LOC | |
| 768 #define LABEL_AFTER_LOC(STREAM) | |
| 769 #endif | |
| 770 | |
| 771 | |
| 772 /* Default to -G 8 */ | |
| 773 #ifndef IQ2000_DEFAULT_GVALUE | |
| 774 #define IQ2000_DEFAULT_GVALUE 8 | |
| 775 #endif | |
| 776 | |
| 777 #define SDATA_SECTION_ASM_OP "\t.sdata" /* Small data. */ | |
| 778 | |
| 779 | |
| 780 /* Which instruction set architecture to use. */ | |
| 781 extern int iq2000_isa; | |
| 782 | |
| 783 enum iq2000_builtins | |
| 784 { | |
| 785 IQ2000_BUILTIN_ADO16, | |
| 786 IQ2000_BUILTIN_CFC0, | |
| 787 IQ2000_BUILTIN_CFC1, | |
| 788 IQ2000_BUILTIN_CFC2, | |
| 789 IQ2000_BUILTIN_CFC3, | |
| 790 IQ2000_BUILTIN_CHKHDR, | |
| 791 IQ2000_BUILTIN_CTC0, | |
| 792 IQ2000_BUILTIN_CTC1, | |
| 793 IQ2000_BUILTIN_CTC2, | |
| 794 IQ2000_BUILTIN_CTC3, | |
| 795 IQ2000_BUILTIN_LU, | |
| 796 IQ2000_BUILTIN_LUC32L, | |
| 797 IQ2000_BUILTIN_LUC64, | |
| 798 IQ2000_BUILTIN_LUC64L, | |
| 799 IQ2000_BUILTIN_LUK, | |
| 800 IQ2000_BUILTIN_LULCK, | |
| 801 IQ2000_BUILTIN_LUM32, | |
| 802 IQ2000_BUILTIN_LUM32L, | |
| 803 IQ2000_BUILTIN_LUM64, | |
| 804 IQ2000_BUILTIN_LUM64L, | |
| 805 IQ2000_BUILTIN_LUR, | |
| 806 IQ2000_BUILTIN_LURL, | |
| 807 IQ2000_BUILTIN_MFC0, | |
| 808 IQ2000_BUILTIN_MFC1, | |
| 809 IQ2000_BUILTIN_MFC2, | |
| 810 IQ2000_BUILTIN_MFC3, | |
| 811 IQ2000_BUILTIN_MRGB, | |
| 812 IQ2000_BUILTIN_MTC0, | |
| 813 IQ2000_BUILTIN_MTC1, | |
| 814 IQ2000_BUILTIN_MTC2, | |
| 815 IQ2000_BUILTIN_MTC3, | |
| 816 IQ2000_BUILTIN_PKRL, | |
| 817 IQ2000_BUILTIN_RAM, | |
| 818 IQ2000_BUILTIN_RB, | |
| 819 IQ2000_BUILTIN_RX, | |
| 820 IQ2000_BUILTIN_SRRD, | |
| 821 IQ2000_BUILTIN_SRRDL, | |
| 822 IQ2000_BUILTIN_SRULC, | |
| 823 IQ2000_BUILTIN_SRULCK, | |
| 824 IQ2000_BUILTIN_SRWR, | |
| 825 IQ2000_BUILTIN_SRWRU, | |
| 826 IQ2000_BUILTIN_TRAPQF, | |
| 827 IQ2000_BUILTIN_TRAPQFL, | |
| 828 IQ2000_BUILTIN_TRAPQN, | |
| 829 IQ2000_BUILTIN_TRAPQNE, | |
| 830 IQ2000_BUILTIN_TRAPRE, | |
| 831 IQ2000_BUILTIN_TRAPREL, | |
| 832 IQ2000_BUILTIN_WB, | |
| 833 IQ2000_BUILTIN_WBR, | |
| 834 IQ2000_BUILTIN_WBU, | |
| 835 IQ2000_BUILTIN_WX, | |
| 836 IQ2000_BUILTIN_SYSCALL | |
| 837 }; |