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1 /* Change pseudos by memory.
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145
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2 Copyright (C) 2010-2020 Free Software Foundation, Inc.
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3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify it under
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8 the terms of the GNU General Public License as published by the Free
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9 Software Foundation; either version 3, or (at your option) any later
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10 version.
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11
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12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
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14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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15 for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21
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22 /* This file contains code for a pass to change spilled pseudos into
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23 memory.
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24
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25 The pass creates necessary stack slots and assigns spilled pseudos
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26 to the stack slots in following way:
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27
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28 for all spilled pseudos P most frequently used first do
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29 for all stack slots S do
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30 if P doesn't conflict with pseudos assigned to S then
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31 assign S to P and goto to the next pseudo process
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32 end
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33 end
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34 create new stack slot S and assign P to S
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35 end
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36
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37 The actual algorithm is bit more complicated because of different
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38 pseudo sizes.
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39
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40 After that the code changes spilled pseudos (except ones created
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41 from scratches) by corresponding stack slot memory in RTL.
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42
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43 If at least one stack slot was created, we need to run more passes
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44 because we have new addresses which should be checked and because
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45 the old address displacements might change and address constraints
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46 (or insn memory constraints) might not be satisfied any more.
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47
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48 For some targets, the pass can spill some pseudos into hard
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49 registers of different class (usually into vector registers)
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50 instead of spilling them into memory if it is possible and
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51 profitable. Spilling GENERAL_REGS pseudo into SSE registers for
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52 Intel Corei7 is an example of such optimization. And this is
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53 actually recommended by Intel optimization guide.
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54
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55 The file also contains code for final change of pseudos on hard
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56 regs correspondingly assigned to them. */
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57
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58 #include "config.h"
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59 #include "system.h"
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60 #include "coretypes.h"
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61 #include "backend.h"
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62 #include "target.h"
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63 #include "rtl.h"
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64 #include "df.h"
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65 #include "insn-config.h"
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66 #include "regs.h"
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67 #include "memmodel.h"
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68 #include "ira.h"
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69 #include "recog.h"
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70 #include "output.h"
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71 #include "cfgrtl.h"
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72 #include "lra.h"
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73 #include "lra-int.h"
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74
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75
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76 /* Max regno at the start of the pass. */
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77 static int regs_num;
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78
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79 /* Map spilled regno -> hard regno used instead of memory for
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80 spilling. */
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81 static rtx *spill_hard_reg;
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82
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83 /* The structure describes stack slot of a spilled pseudo. */
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84 struct pseudo_slot
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85 {
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86 /* Number (0, 1, ...) of the stack slot to which given pseudo
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87 belongs. */
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88 int slot_num;
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89 /* First or next slot with the same slot number. */
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90 struct pseudo_slot *next, *first;
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91 /* Memory representing the spilled pseudo. */
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92 rtx mem;
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93 };
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94
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95 /* The stack slots for each spilled pseudo. Indexed by regnos. */
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96 static struct pseudo_slot *pseudo_slots;
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97
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98 /* The structure describes a register or a stack slot which can be
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99 used for several spilled pseudos. */
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100 class slot
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101 {
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102 public:
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103 /* First pseudo with given stack slot. */
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104 int regno;
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105 /* Hard reg into which the slot pseudos are spilled. The value is
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106 negative for pseudos spilled into memory. */
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107 int hard_regno;
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108 /* Maximum alignment required by all users of the slot. */
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109 unsigned int align;
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110 /* Maximum size required by all users of the slot. */
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131
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111 poly_int64 size;
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112 /* Memory representing the all stack slot. It can be different from
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113 memory representing a pseudo belonging to give stack slot because
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114 pseudo can be placed in a part of the corresponding stack slot.
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115 The value is NULL for pseudos spilled into a hard reg. */
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116 rtx mem;
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117 /* Combined live ranges of all pseudos belonging to given slot. It
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118 is used to figure out that a new spilled pseudo can use given
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119 stack slot. */
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120 lra_live_range_t live_ranges;
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121 };
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122
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123 /* Array containing info about the stack slots. The array element is
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124 indexed by the stack slot number in the range [0..slots_num). */
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125 static class slot *slots;
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126 /* The number of the stack slots currently existing. */
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127 static int slots_num;
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128
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129 /* Set up memory of the spilled pseudo I. The function can allocate
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130 the corresponding stack slot if it is not done yet. */
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131 static void
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132 assign_mem_slot (int i)
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133 {
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134 rtx x = NULL_RTX;
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135 machine_mode mode = GET_MODE (regno_reg_rtx[i]);
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131
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136 poly_int64 inherent_size = PSEUDO_REGNO_BYTES (i);
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137 machine_mode wider_mode
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138 = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode);
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131
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139 poly_int64 total_size = GET_MODE_SIZE (wider_mode);
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140 poly_int64 adjust = 0;
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111
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141
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142 lra_assert (regno_reg_rtx[i] != NULL_RTX && REG_P (regno_reg_rtx[i])
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143 && lra_reg_info[i].nrefs != 0 && reg_renumber[i] < 0);
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144
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145 unsigned int slot_num = pseudo_slots[i].slot_num;
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146 x = slots[slot_num].mem;
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147 if (!x)
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148 {
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149 x = assign_stack_local (BLKmode, slots[slot_num].size,
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150 slots[slot_num].align);
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151 slots[slot_num].mem = x;
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152 }
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153
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154 /* On a big endian machine, the "address" of the slot is the address
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155 of the low part that fits its inherent mode. */
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156 adjust += subreg_size_lowpart_offset (inherent_size, total_size);
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157 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
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158
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159 /* Set all of the memory attributes as appropriate for a spill. */
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160 set_mem_attrs_for_spill (x);
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161 pseudo_slots[i].mem = x;
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162 }
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163
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164 /* Sort pseudos according their usage frequencies. */
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165 static int
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166 regno_freq_compare (const void *v1p, const void *v2p)
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167 {
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168 const int regno1 = *(const int *) v1p;
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169 const int regno2 = *(const int *) v2p;
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170 int diff;
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171
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172 if ((diff = lra_reg_info[regno2].freq - lra_reg_info[regno1].freq) != 0)
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173 return diff;
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174 return regno1 - regno2;
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175 }
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176
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177 /* Sort pseudos according to their slots, putting the slots in the order
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131
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178 that they should be allocated.
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179
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180 First prefer to group slots with variable sizes together and slots
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181 with constant sizes together, since that usually makes them easier
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182 to address from a common anchor point. E.g. loads of polynomial-sized
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183 registers tend to take polynomial offsets while loads of constant-sized
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184 registers tend to take constant (non-polynomial) offsets.
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185
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186 Next, slots with lower numbers have the highest priority and should
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187 get the smallest displacement from the stack or frame pointer
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188 (whichever is being used).
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111
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189
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190 The first allocated slot is always closest to the frame pointer,
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191 so prefer lower slot numbers when frame_pointer_needed. If the stack
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192 and frame grow in the same direction, then the first allocated slot is
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193 always closest to the initial stack pointer and furthest away from the
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194 final stack pointer, so allocate higher numbers first when using the
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195 stack pointer in that case. The reverse is true if the stack and
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196 frame grow in opposite directions. */
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197 static int
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198 pseudo_reg_slot_compare (const void *v1p, const void *v2p)
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199 {
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200 const int regno1 = *(const int *) v1p;
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201 const int regno2 = *(const int *) v2p;
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202 int diff, slot_num1, slot_num2;
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203
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204 slot_num1 = pseudo_slots[regno1].slot_num;
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205 slot_num2 = pseudo_slots[regno2].slot_num;
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131
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206 diff = (int (slots[slot_num1].size.is_constant ())
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207 - int (slots[slot_num2].size.is_constant ()));
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208 if (diff != 0)
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209 return diff;
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111
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210 if ((diff = slot_num1 - slot_num2) != 0)
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211 return (frame_pointer_needed
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212 || (!FRAME_GROWS_DOWNWARD) == STACK_GROWS_DOWNWARD ? diff : -diff);
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131
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213 poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode);
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214 poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode);
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215 if ((diff = compare_sizes_for_sort (total_size2, total_size1)) != 0)
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111
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216 return diff;
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217 return regno1 - regno2;
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218 }
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219
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220 /* Assign spill hard registers to N pseudos in PSEUDO_REGNOS which is
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221 sorted in order of highest frequency first. Put the pseudos which
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222 did not get a spill hard register at the beginning of array
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223 PSEUDO_REGNOS. Return the number of such pseudos. */
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224 static int
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225 assign_spill_hard_regs (int *pseudo_regnos, int n)
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226 {
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227 int i, k, p, regno, res, spill_class_size, hard_regno, nr;
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228 enum reg_class rclass, spill_class;
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229 machine_mode mode;
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230 lra_live_range_t r;
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231 rtx_insn *insn;
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232 rtx set;
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233 basic_block bb;
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234 HARD_REG_SET conflict_hard_regs;
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235 bitmap setjump_crosses = regstat_get_setjmp_crosses ();
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236 /* Hard registers which cannot be used for any purpose at given
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237 program point because they are unallocatable or already allocated
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238 for other pseudos. */
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239 HARD_REG_SET *reserved_hard_regs;
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240
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241 if (! lra_reg_spill_p)
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242 return n;
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243 /* Set up reserved hard regs for every program point. */
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244 reserved_hard_regs = XNEWVEC (HARD_REG_SET, lra_live_max_point);
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245 for (p = 0; p < lra_live_max_point; p++)
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246 reserved_hard_regs[p] = lra_no_alloc_regs;
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111
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247 for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++)
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248 if (lra_reg_info[i].nrefs != 0
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249 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
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250 for (r = lra_reg_info[i].live_ranges; r != NULL; r = r->next)
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251 for (p = r->start; p <= r->finish; p++)
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252 add_to_hard_reg_set (&reserved_hard_regs[p],
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253 lra_reg_info[i].biggest_mode, hard_regno);
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254 auto_bitmap ok_insn_bitmap (®_obstack);
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255 FOR_EACH_BB_FN (bb, cfun)
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256 FOR_BB_INSNS (bb, insn)
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257 if (DEBUG_INSN_P (insn)
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258 || ((set = single_set (insn)) != NULL_RTX
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259 && REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))))
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260 bitmap_set_bit (ok_insn_bitmap, INSN_UID (insn));
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261 for (res = i = 0; i < n; i++)
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262 {
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263 regno = pseudo_regnos[i];
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264 rclass = lra_get_allocno_class (regno);
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265 if (bitmap_bit_p (setjump_crosses, regno)
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266 || (spill_class
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267 = ((enum reg_class)
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268 targetm.spill_class ((reg_class_t) rclass,
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269 PSEUDO_REGNO_MODE (regno)))) == NO_REGS
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270 || bitmap_intersect_compl_p (&lra_reg_info[regno].insn_bitmap,
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271 ok_insn_bitmap))
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272 {
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273 pseudo_regnos[res++] = regno;
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274 continue;
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275 }
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276 lra_assert (spill_class != NO_REGS);
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145
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277 conflict_hard_regs = lra_reg_info[regno].conflict_hard_regs;
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111
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278 for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next)
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279 for (p = r->start; p <= r->finish; p++)
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280 conflict_hard_regs |= reserved_hard_regs[p];
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111
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281 spill_class_size = ira_class_hard_regs_num[spill_class];
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282 mode = lra_reg_info[regno].biggest_mode;
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283 for (k = 0; k < spill_class_size; k++)
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284 {
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285 hard_regno = ira_class_hard_regs[spill_class][k];
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286 if (TEST_HARD_REG_BIT (eliminable_regset, hard_regno)
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287 || !targetm.hard_regno_mode_ok (hard_regno, mode))
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288 continue;
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111
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289 if (! overlaps_hard_reg_set_p (conflict_hard_regs, mode, hard_regno))
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290 break;
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291 }
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292 if (k >= spill_class_size)
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293 {
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294 /* There is no available regs -- assign memory later. */
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295 pseudo_regnos[res++] = regno;
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296 continue;
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297 }
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298 if (lra_dump_file != NULL)
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299 fprintf (lra_dump_file, " Spill r%d into hr%d\n", regno, hard_regno);
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131
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300 add_to_hard_reg_set (&hard_regs_spilled_into,
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301 lra_reg_info[regno].biggest_mode, hard_regno);
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111
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302 /* Update reserved_hard_regs. */
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303 for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next)
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304 for (p = r->start; p <= r->finish; p++)
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305 add_to_hard_reg_set (&reserved_hard_regs[p],
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306 lra_reg_info[regno].biggest_mode, hard_regno);
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307 spill_hard_reg[regno]
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308 = gen_raw_REG (PSEUDO_REGNO_MODE (regno), hard_regno);
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309 for (nr = 0;
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310 nr < hard_regno_nregs (hard_regno,
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311 lra_reg_info[regno].biggest_mode);
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312 nr++)
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313 /* Just loop. */
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314 df_set_regs_ever_live (hard_regno + nr, true);
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315 }
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316 free (reserved_hard_regs);
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317 return res;
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318 }
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319
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320 /* Add pseudo REGNO to slot SLOT_NUM. */
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321 static void
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322 add_pseudo_to_slot (int regno, int slot_num)
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323 {
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324 struct pseudo_slot *first;
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325
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326 /* Each pseudo has an inherent size which comes from its own mode,
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327 and a total size which provides room for paradoxical subregs.
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328 We need to make sure the size and alignment of the slot are
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329 sufficient for both. */
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330 machine_mode mode = wider_subreg_mode (PSEUDO_REGNO_MODE (regno),
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331 lra_reg_info[regno].biggest_mode);
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332 unsigned int align = spill_slot_alignment (mode);
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333 slots[slot_num].align = MAX (slots[slot_num].align, align);
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131
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334 slots[slot_num].size = upper_bound (slots[slot_num].size,
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335 GET_MODE_SIZE (mode));
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111
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336
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337 if (slots[slot_num].regno < 0)
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338 {
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339 /* It is the first pseudo in the slot. */
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340 slots[slot_num].regno = regno;
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341 pseudo_slots[regno].first = &pseudo_slots[regno];
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342 pseudo_slots[regno].next = NULL;
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343 }
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344 else
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345 {
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346 first = pseudo_slots[regno].first = &pseudo_slots[slots[slot_num].regno];
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347 pseudo_slots[regno].next = first->next;
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348 first->next = &pseudo_slots[regno];
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349 }
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350 pseudo_slots[regno].mem = NULL_RTX;
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351 pseudo_slots[regno].slot_num = slot_num;
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352 slots[slot_num].live_ranges
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353 = lra_merge_live_ranges (slots[slot_num].live_ranges,
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354 lra_copy_live_range_list
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355 (lra_reg_info[regno].live_ranges));
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356 }
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357
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358 /* Assign stack slot numbers to pseudos in array PSEUDO_REGNOS of
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359 length N. Sort pseudos in PSEUDO_REGNOS for subsequent assigning
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360 memory stack slots. */
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361 static void
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|
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362 assign_stack_slot_num_and_sort_pseudos (int *pseudo_regnos, int n)
|
|
|
363 {
|
|
|
364 int i, j, regno;
|
|
|
365
|
|
|
366 slots_num = 0;
|
|
|
367 /* Assign stack slot numbers to spilled pseudos, use smaller numbers
|
|
|
368 for most frequently used pseudos. */
|
|
|
369 for (i = 0; i < n; i++)
|
|
|
370 {
|
|
|
371 regno = pseudo_regnos[i];
|
|
|
372 if (! flag_ira_share_spill_slots)
|
|
|
373 j = slots_num;
|
|
|
374 else
|
|
|
375 {
|
|
131
|
376 machine_mode mode
|
|
|
377 = wider_subreg_mode (PSEUDO_REGNO_MODE (regno),
|
|
|
378 lra_reg_info[regno].biggest_mode);
|
|
111
|
379 for (j = 0; j < slots_num; j++)
|
|
|
380 if (slots[j].hard_regno < 0
|
|
131
|
381 /* Although it's possible to share slots between modes
|
|
|
382 with constant and non-constant widths, we usually
|
|
|
383 get better spill code by keeping the constant and
|
|
|
384 non-constant areas separate. */
|
|
|
385 && (GET_MODE_SIZE (mode).is_constant ()
|
|
|
386 == slots[j].size.is_constant ())
|
|
111
|
387 && ! (lra_intersected_live_ranges_p
|
|
|
388 (slots[j].live_ranges,
|
|
|
389 lra_reg_info[regno].live_ranges)))
|
|
|
390 break;
|
|
|
391 }
|
|
|
392 if (j >= slots_num)
|
|
|
393 {
|
|
|
394 /* New slot. */
|
|
|
395 slots[j].live_ranges = NULL;
|
|
|
396 slots[j].size = 0;
|
|
|
397 slots[j].align = BITS_PER_UNIT;
|
|
|
398 slots[j].regno = slots[j].hard_regno = -1;
|
|
|
399 slots[j].mem = NULL_RTX;
|
|
|
400 slots_num++;
|
|
|
401 }
|
|
|
402 add_pseudo_to_slot (regno, j);
|
|
|
403 }
|
|
|
404 /* Sort regnos according to their slot numbers. */
|
|
|
405 qsort (pseudo_regnos, n, sizeof (int), pseudo_reg_slot_compare);
|
|
|
406 }
|
|
|
407
|
|
|
408 /* Recursively process LOC in INSN and change spilled pseudos to the
|
|
|
409 corresponding memory or spilled hard reg. Ignore spilled pseudos
|
|
|
410 created from the scratches. Return true if the pseudo nrefs equal
|
|
|
411 to 0 (don't change the pseudo in this case). Otherwise return false. */
|
|
|
412 static bool
|
|
|
413 remove_pseudos (rtx *loc, rtx_insn *insn)
|
|
|
414 {
|
|
|
415 int i;
|
|
|
416 rtx hard_reg;
|
|
|
417 const char *fmt;
|
|
|
418 enum rtx_code code;
|
|
|
419 bool res = false;
|
|
|
420
|
|
|
421 if (*loc == NULL_RTX)
|
|
|
422 return res;
|
|
|
423 code = GET_CODE (*loc);
|
|
|
424 if (code == REG && (i = REGNO (*loc)) >= FIRST_PSEUDO_REGISTER
|
|
|
425 && lra_get_regno_hard_regno (i) < 0
|
|
|
426 /* We do not want to assign memory for former scratches because
|
|
|
427 it might result in an address reload for some targets. In
|
|
|
428 any case we transform such pseudos not getting hard registers
|
|
|
429 into scratches back. */
|
|
|
430 && ! lra_former_scratch_p (i))
|
|
|
431 {
|
|
|
432 if (lra_reg_info[i].nrefs == 0
|
|
|
433 && pseudo_slots[i].mem == NULL && spill_hard_reg[i] == NULL)
|
|
|
434 return true;
|
|
|
435 if ((hard_reg = spill_hard_reg[i]) != NULL_RTX)
|
|
|
436 *loc = copy_rtx (hard_reg);
|
|
|
437 else
|
|
|
438 {
|
|
|
439 rtx x = lra_eliminate_regs_1 (insn, pseudo_slots[i].mem,
|
|
|
440 GET_MODE (pseudo_slots[i].mem),
|
|
|
441 false, false, 0, true);
|
|
|
442 *loc = x != pseudo_slots[i].mem ? x : copy_rtx (x);
|
|
|
443 }
|
|
|
444 return res;
|
|
|
445 }
|
|
|
446
|
|
|
447 fmt = GET_RTX_FORMAT (code);
|
|
|
448 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
|
|
|
449 {
|
|
|
450 if (fmt[i] == 'e')
|
|
|
451 res = remove_pseudos (&XEXP (*loc, i), insn) || res;
|
|
|
452 else if (fmt[i] == 'E')
|
|
|
453 {
|
|
|
454 int j;
|
|
|
455
|
|
|
456 for (j = XVECLEN (*loc, i) - 1; j >= 0; j--)
|
|
|
457 res = remove_pseudos (&XVECEXP (*loc, i, j), insn) || res;
|
|
|
458 }
|
|
|
459 }
|
|
|
460 return res;
|
|
|
461 }
|
|
|
462
|
|
|
463 /* Convert spilled pseudos into their stack slots or spill hard regs,
|
|
|
464 put insns to process on the constraint stack (that is all insns in
|
|
|
465 which pseudos were changed to memory or spill hard regs). */
|
|
|
466 static void
|
|
|
467 spill_pseudos (void)
|
|
|
468 {
|
|
|
469 basic_block bb;
|
|
|
470 rtx_insn *insn, *curr;
|
|
|
471 int i;
|
|
|
472
|
|
|
473 auto_bitmap spilled_pseudos (®_obstack);
|
|
|
474 auto_bitmap changed_insns (®_obstack);
|
|
|
475 for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++)
|
|
|
476 {
|
|
|
477 if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0
|
|
|
478 && ! lra_former_scratch_p (i))
|
|
|
479 {
|
|
|
480 bitmap_set_bit (spilled_pseudos, i);
|
|
|
481 bitmap_ior_into (changed_insns, &lra_reg_info[i].insn_bitmap);
|
|
|
482 }
|
|
|
483 }
|
|
|
484 FOR_EACH_BB_FN (bb, cfun)
|
|
|
485 {
|
|
|
486 FOR_BB_INSNS_SAFE (bb, insn, curr)
|
|
|
487 {
|
|
|
488 bool removed_pseudo_p = false;
|
|
|
489
|
|
|
490 if (bitmap_bit_p (changed_insns, INSN_UID (insn)))
|
|
|
491 {
|
|
|
492 rtx *link_loc, link;
|
|
|
493
|
|
|
494 removed_pseudo_p = remove_pseudos (&PATTERN (insn), insn);
|
|
|
495 if (CALL_P (insn)
|
|
|
496 && remove_pseudos (&CALL_INSN_FUNCTION_USAGE (insn), insn))
|
|
|
497 removed_pseudo_p = true;
|
|
|
498 for (link_loc = ®_NOTES (insn);
|
|
|
499 (link = *link_loc) != NULL_RTX;
|
|
|
500 link_loc = &XEXP (link, 1))
|
|
|
501 {
|
|
|
502 switch (REG_NOTE_KIND (link))
|
|
|
503 {
|
|
|
504 case REG_FRAME_RELATED_EXPR:
|
|
|
505 case REG_CFA_DEF_CFA:
|
|
|
506 case REG_CFA_ADJUST_CFA:
|
|
|
507 case REG_CFA_OFFSET:
|
|
|
508 case REG_CFA_REGISTER:
|
|
|
509 case REG_CFA_EXPRESSION:
|
|
|
510 case REG_CFA_RESTORE:
|
|
|
511 case REG_CFA_SET_VDRAP:
|
|
|
512 if (remove_pseudos (&XEXP (link, 0), insn))
|
|
|
513 removed_pseudo_p = true;
|
|
|
514 break;
|
|
|
515 default:
|
|
|
516 break;
|
|
|
517 }
|
|
|
518 }
|
|
|
519 if (lra_dump_file != NULL)
|
|
|
520 fprintf (lra_dump_file,
|
|
|
521 "Changing spilled pseudos to memory in insn #%u\n",
|
|
|
522 INSN_UID (insn));
|
|
|
523 lra_push_insn (insn);
|
|
|
524 if (lra_reg_spill_p || targetm.different_addr_displacement_p ())
|
|
131
|
525 lra_set_used_insn_alternative (insn, LRA_UNKNOWN_ALT);
|
|
111
|
526 }
|
|
|
527 else if (CALL_P (insn)
|
|
|
528 /* Presence of any pseudo in CALL_INSN_FUNCTION_USAGE
|
|
|
529 does not affect value of insn_bitmap of the
|
|
|
530 corresponding lra_reg_info. That is because we
|
|
|
531 don't need to reload pseudos in
|
|
|
532 CALL_INSN_FUNCTION_USAGEs. So if we process only
|
|
|
533 insns in the insn_bitmap of given pseudo here, we
|
|
|
534 can miss the pseudo in some
|
|
|
535 CALL_INSN_FUNCTION_USAGEs. */
|
|
|
536 && remove_pseudos (&CALL_INSN_FUNCTION_USAGE (insn), insn))
|
|
|
537 removed_pseudo_p = true;
|
|
|
538 if (removed_pseudo_p)
|
|
|
539 {
|
|
|
540 lra_assert (DEBUG_INSN_P (insn));
|
|
|
541 lra_invalidate_insn_data (insn);
|
|
|
542 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
|
|
|
543 if (lra_dump_file != NULL)
|
|
|
544 fprintf (lra_dump_file,
|
|
|
545 "Debug insn #%u is reset because it referenced "
|
|
|
546 "removed pseudo\n", INSN_UID (insn));
|
|
|
547 }
|
|
|
548 bitmap_and_compl_into (df_get_live_in (bb), spilled_pseudos);
|
|
|
549 bitmap_and_compl_into (df_get_live_out (bb), spilled_pseudos);
|
|
|
550 }
|
|
|
551 }
|
|
|
552 }
|
|
|
553
|
|
145
|
554 /* Return true if we need scratch reg assignments. */
|
|
|
555 bool
|
|
|
556 lra_need_for_scratch_reg_p (void)
|
|
|
557 {
|
|
|
558 int i; max_regno = max_reg_num ();
|
|
|
559
|
|
|
560 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
|
|
|
561 if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0
|
|
|
562 && lra_former_scratch_p (i))
|
|
|
563 return true;
|
|
|
564 return false;
|
|
|
565 }
|
|
|
566
|
|
111
|
567 /* Return true if we need to change some pseudos into memory. */
|
|
|
568 bool
|
|
|
569 lra_need_for_spills_p (void)
|
|
|
570 {
|
|
|
571 int i; max_regno = max_reg_num ();
|
|
|
572
|
|
|
573 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
|
|
|
574 if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0
|
|
|
575 && ! lra_former_scratch_p (i))
|
|
|
576 return true;
|
|
|
577 return false;
|
|
|
578 }
|
|
|
579
|
|
|
580 /* Change spilled pseudos into memory or spill hard regs. Put changed
|
|
|
581 insns on the constraint stack (these insns will be considered on
|
|
|
582 the next constraint pass). The changed insns are all insns in
|
|
|
583 which pseudos were changed. */
|
|
|
584 void
|
|
|
585 lra_spill (void)
|
|
|
586 {
|
|
|
587 int i, n, curr_regno;
|
|
|
588 int *pseudo_regnos;
|
|
|
589
|
|
|
590 regs_num = max_reg_num ();
|
|
|
591 spill_hard_reg = XNEWVEC (rtx, regs_num);
|
|
|
592 pseudo_regnos = XNEWVEC (int, regs_num);
|
|
|
593 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < regs_num; i++)
|
|
|
594 if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0
|
|
|
595 /* We do not want to assign memory for former scratches. */
|
|
|
596 && ! lra_former_scratch_p (i))
|
|
|
597 pseudo_regnos[n++] = i;
|
|
|
598 lra_assert (n > 0);
|
|
|
599 pseudo_slots = XNEWVEC (struct pseudo_slot, regs_num);
|
|
|
600 for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++)
|
|
|
601 {
|
|
|
602 spill_hard_reg[i] = NULL_RTX;
|
|
|
603 pseudo_slots[i].mem = NULL_RTX;
|
|
|
604 }
|
|
145
|
605 slots = XNEWVEC (class slot, regs_num);
|
|
111
|
606 /* Sort regnos according their usage frequencies. */
|
|
|
607 qsort (pseudo_regnos, n, sizeof (int), regno_freq_compare);
|
|
|
608 n = assign_spill_hard_regs (pseudo_regnos, n);
|
|
|
609 assign_stack_slot_num_and_sort_pseudos (pseudo_regnos, n);
|
|
|
610 for (i = 0; i < n; i++)
|
|
|
611 if (pseudo_slots[pseudo_regnos[i]].mem == NULL_RTX)
|
|
|
612 assign_mem_slot (pseudo_regnos[i]);
|
|
|
613 if (n > 0 && crtl->stack_alignment_needed)
|
|
|
614 /* If we have a stack frame, we must align it now. The stack size
|
|
|
615 may be a part of the offset computation for register
|
|
|
616 elimination. */
|
|
|
617 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
|
|
|
618 if (lra_dump_file != NULL)
|
|
|
619 {
|
|
|
620 for (i = 0; i < slots_num; i++)
|
|
|
621 {
|
|
131
|
622 fprintf (lra_dump_file, " Slot %d regnos (width = ", i);
|
|
|
623 print_dec (GET_MODE_SIZE (GET_MODE (slots[i].mem)),
|
|
|
624 lra_dump_file, SIGNED);
|
|
|
625 fprintf (lra_dump_file, "):");
|
|
111
|
626 for (curr_regno = slots[i].regno;;
|
|
|
627 curr_regno = pseudo_slots[curr_regno].next - pseudo_slots)
|
|
|
628 {
|
|
|
629 fprintf (lra_dump_file, " %d", curr_regno);
|
|
|
630 if (pseudo_slots[curr_regno].next == NULL)
|
|
|
631 break;
|
|
|
632 }
|
|
|
633 fprintf (lra_dump_file, "\n");
|
|
|
634 }
|
|
|
635 }
|
|
|
636 spill_pseudos ();
|
|
|
637 free (slots);
|
|
|
638 free (pseudo_slots);
|
|
|
639 free (pseudo_regnos);
|
|
|
640 free (spill_hard_reg);
|
|
|
641 }
|
|
|
642
|
|
|
643 /* Apply alter_subreg for subregs of regs in *LOC. Use FINAL_P for
|
|
|
644 alter_subreg calls. Return true if any subreg of reg is
|
|
|
645 processed. */
|
|
|
646 static bool
|
|
|
647 alter_subregs (rtx *loc, bool final_p)
|
|
|
648 {
|
|
|
649 int i;
|
|
|
650 rtx x = *loc;
|
|
|
651 bool res;
|
|
|
652 const char *fmt;
|
|
|
653 enum rtx_code code;
|
|
|
654
|
|
|
655 if (x == NULL_RTX)
|
|
|
656 return false;
|
|
|
657 code = GET_CODE (x);
|
|
|
658 if (code == SUBREG && REG_P (SUBREG_REG (x)))
|
|
|
659 {
|
|
|
660 lra_assert (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER);
|
|
|
661 alter_subreg (loc, final_p);
|
|
|
662 return true;
|
|
|
663 }
|
|
|
664 fmt = GET_RTX_FORMAT (code);
|
|
|
665 res = false;
|
|
|
666 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
|
|
|
667 {
|
|
|
668 if (fmt[i] == 'e')
|
|
|
669 {
|
|
|
670 if (alter_subregs (&XEXP (x, i), final_p))
|
|
|
671 res = true;
|
|
|
672 }
|
|
|
673 else if (fmt[i] == 'E')
|
|
|
674 {
|
|
|
675 int j;
|
|
|
676
|
|
|
677 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
|
|
|
678 if (alter_subregs (&XVECEXP (x, i, j), final_p))
|
|
|
679 res = true;
|
|
|
680 }
|
|
|
681 }
|
|
|
682 return res;
|
|
|
683 }
|
|
|
684
|
|
|
685 /* Return true if REGNO is used for return in the current
|
|
|
686 function. */
|
|
|
687 static bool
|
|
|
688 return_regno_p (unsigned int regno)
|
|
|
689 {
|
|
|
690 rtx outgoing = crtl->return_rtx;
|
|
|
691
|
|
|
692 if (! outgoing)
|
|
|
693 return false;
|
|
|
694
|
|
|
695 if (REG_P (outgoing))
|
|
|
696 return REGNO (outgoing) == regno;
|
|
|
697 else if (GET_CODE (outgoing) == PARALLEL)
|
|
|
698 {
|
|
|
699 int i;
|
|
|
700
|
|
|
701 for (i = 0; i < XVECLEN (outgoing, 0); i++)
|
|
|
702 {
|
|
|
703 rtx x = XEXP (XVECEXP (outgoing, 0, i), 0);
|
|
|
704
|
|
|
705 if (REG_P (x) && REGNO (x) == regno)
|
|
|
706 return true;
|
|
|
707 }
|
|
|
708 }
|
|
|
709 return false;
|
|
|
710 }
|
|
|
711
|
|
|
712 /* Return true if REGNO is in one of subsequent USE after INSN in the
|
|
|
713 same BB. */
|
|
|
714 static bool
|
|
|
715 regno_in_use_p (rtx_insn *insn, unsigned int regno)
|
|
|
716 {
|
|
|
717 static lra_insn_recog_data_t id;
|
|
|
718 static struct lra_static_insn_data *static_id;
|
|
|
719 struct lra_insn_reg *reg;
|
|
|
720 int i, arg_regno;
|
|
|
721 basic_block bb = BLOCK_FOR_INSN (insn);
|
|
|
722
|
|
|
723 while ((insn = next_nondebug_insn (insn)) != NULL_RTX)
|
|
|
724 {
|
|
|
725 if (BARRIER_P (insn) || bb != BLOCK_FOR_INSN (insn))
|
|
|
726 return false;
|
|
|
727 if (! INSN_P (insn))
|
|
|
728 continue;
|
|
|
729 if (GET_CODE (PATTERN (insn)) == USE
|
|
|
730 && REG_P (XEXP (PATTERN (insn), 0))
|
|
|
731 && regno == REGNO (XEXP (PATTERN (insn), 0)))
|
|
|
732 return true;
|
|
|
733 /* Check that the regno is not modified. */
|
|
|
734 id = lra_get_insn_recog_data (insn);
|
|
|
735 for (reg = id->regs; reg != NULL; reg = reg->next)
|
|
|
736 if (reg->type != OP_IN && reg->regno == (int) regno)
|
|
|
737 return false;
|
|
|
738 static_id = id->insn_static_data;
|
|
|
739 for (reg = static_id->hard_regs; reg != NULL; reg = reg->next)
|
|
|
740 if (reg->type != OP_IN && reg->regno == (int) regno)
|
|
|
741 return false;
|
|
|
742 if (id->arg_hard_regs != NULL)
|
|
|
743 for (i = 0; (arg_regno = id->arg_hard_regs[i]) >= 0; i++)
|
|
|
744 if ((int) regno == (arg_regno >= FIRST_PSEUDO_REGISTER
|
|
|
745 ? arg_regno : arg_regno - FIRST_PSEUDO_REGISTER))
|
|
|
746 return false;
|
|
|
747 }
|
|
|
748 return false;
|
|
|
749 }
|
|
|
750
|
|
|
751 /* Final change of pseudos got hard registers into the corresponding
|
|
|
752 hard registers and removing temporary clobbers. */
|
|
|
753 void
|
|
|
754 lra_final_code_change (void)
|
|
|
755 {
|
|
|
756 int i, hard_regno;
|
|
|
757 basic_block bb;
|
|
|
758 rtx_insn *insn, *curr;
|
|
145
|
759 rtx set;
|
|
111
|
760 int max_regno = max_reg_num ();
|
|
|
761
|
|
|
762 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
|
|
|
763 if (lra_reg_info[i].nrefs != 0
|
|
|
764 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
|
|
|
765 SET_REGNO (regno_reg_rtx[i], hard_regno);
|
|
|
766 FOR_EACH_BB_FN (bb, cfun)
|
|
|
767 FOR_BB_INSNS_SAFE (bb, insn, curr)
|
|
|
768 if (INSN_P (insn))
|
|
|
769 {
|
|
|
770 rtx pat = PATTERN (insn);
|
|
|
771
|
|
|
772 if (GET_CODE (pat) == CLOBBER && LRA_TEMP_CLOBBER_P (pat))
|
|
|
773 {
|
|
|
774 /* Remove clobbers temporarily created in LRA. We don't
|
|
|
775 need them anymore and don't want to waste compiler
|
|
|
776 time processing them in a few subsequent passes. */
|
|
|
777 lra_invalidate_insn_data (insn);
|
|
|
778 delete_insn (insn);
|
|
|
779 continue;
|
|
|
780 }
|
|
|
781
|
|
|
782 /* IRA can generate move insns involving pseudos. It is
|
|
|
783 better remove them earlier to speed up compiler a bit.
|
|
|
784 It is also better to do it here as they might not pass
|
|
|
785 final RTL check in LRA, (e.g. insn moving a control
|
|
|
786 register into itself). So remove an useless move insn
|
|
|
787 unless next insn is USE marking the return reg (we should
|
|
|
788 save this as some subsequent optimizations assume that
|
|
|
789 such original insns are saved). */
|
|
|
790 if (NONJUMP_INSN_P (insn) && GET_CODE (pat) == SET
|
|
|
791 && REG_P (SET_SRC (pat)) && REG_P (SET_DEST (pat))
|
|
|
792 && REGNO (SET_SRC (pat)) == REGNO (SET_DEST (pat))
|
|
|
793 && (! return_regno_p (REGNO (SET_SRC (pat)))
|
|
|
794 || ! regno_in_use_p (insn, REGNO (SET_SRC (pat)))))
|
|
|
795 {
|
|
|
796 lra_invalidate_insn_data (insn);
|
|
|
797 delete_insn (insn);
|
|
|
798 continue;
|
|
|
799 }
|
|
|
800
|
|
|
801 lra_insn_recog_data_t id = lra_get_insn_recog_data (insn);
|
|
|
802 struct lra_insn_reg *reg;
|
|
|
803
|
|
|
804 for (reg = id->regs; reg != NULL; reg = reg->next)
|
|
|
805 if (reg->regno >= FIRST_PSEUDO_REGISTER
|
|
|
806 && lra_reg_info [reg->regno].nrefs == 0)
|
|
|
807 break;
|
|
|
808
|
|
|
809 if (reg != NULL)
|
|
|
810 {
|
|
|
811 /* Pseudos still can be in debug insns in some very rare
|
|
|
812 and complicated cases, e.g. the pseudo was removed by
|
|
|
813 inheritance and the debug insn is not EBBs where the
|
|
|
814 inheritance happened. It is difficult and time
|
|
|
815 consuming to find what hard register corresponds the
|
|
|
816 pseudo -- so just remove the debug insn. Another
|
|
|
817 solution could be assigning hard reg/memory but it
|
|
|
818 would be a misleading info. It is better not to have
|
|
|
819 info than have it wrong. */
|
|
|
820 lra_assert (DEBUG_INSN_P (insn));
|
|
|
821 lra_invalidate_insn_data (insn);
|
|
|
822 delete_insn (insn);
|
|
|
823 continue;
|
|
|
824 }
|
|
|
825
|
|
|
826 struct lra_static_insn_data *static_id = id->insn_static_data;
|
|
|
827 bool insn_change_p = false;
|
|
|
828
|
|
|
829 for (i = id->insn_static_data->n_operands - 1; i >= 0; i--)
|
|
|
830 if ((DEBUG_INSN_P (insn) || ! static_id->operand[i].is_operator)
|
|
|
831 && alter_subregs (id->operand_loc[i], ! DEBUG_INSN_P (insn)))
|
|
|
832 {
|
|
|
833 lra_update_dup (id, i);
|
|
|
834 insn_change_p = true;
|
|
|
835 }
|
|
|
836 if (insn_change_p)
|
|
|
837 lra_update_operator_dups (id);
|
|
145
|
838
|
|
|
839 if ((set = single_set (insn)) != NULL
|
|
|
840 && REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
|
|
|
841 && REGNO (SET_SRC (set)) == REGNO (SET_DEST (set)))
|
|
|
842 {
|
|
|
843 /* Remove an useless move insn. IRA can generate move
|
|
|
844 insns involving pseudos. It is better remove them
|
|
|
845 earlier to speed up compiler a bit. It is also
|
|
|
846 better to do it here as they might not pass final RTL
|
|
|
847 check in LRA, (e.g. insn moving a control register
|
|
|
848 into itself). */
|
|
|
849 lra_invalidate_insn_data (insn);
|
|
|
850 delete_insn (insn);
|
|
|
851 }
|
|
111
|
852 }
|
|
|
853 }
|
