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annotate gcc/config/rs6000/mpc.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children 04ced10e8804
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1 ;; Scheduling description for Motorola PowerPC processor cores.
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2 ;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify it
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7 ;; under the terms of the GNU General Public License as published
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8 ;; by the Free Software Foundation; either version 3, or (at your
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9 ;; option) any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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14 ;; License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_automaton "mpc,mpcfp")
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21 (define_cpu_unit "iu_mpc,mciu_mpc" "mpc")
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22 (define_cpu_unit "fpu_mpc" "mpcfp")
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23 (define_cpu_unit "lsu_mpc,bpu_mpc" "mpc")
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24
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25 ;; MPCCORE 32-bit SCIU, MCIU, LSU, FPU, BPU
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26 ;; 505/801/821/823
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28 (define_insn_reservation "mpccore-load" 2
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29 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
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30 load_l,store_c,sync")
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31 (eq_attr "cpu" "mpccore"))
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32 "lsu_mpc")
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33
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34 (define_insn_reservation "mpccore-store" 2
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35 (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
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36 (eq_attr "cpu" "mpccore"))
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37 "lsu_mpc")
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38
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39 (define_insn_reservation "mpccore-fpload" 2
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40 (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
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41 (eq_attr "cpu" "mpccore"))
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42 "lsu_mpc")
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43
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44 (define_insn_reservation "mpccore-integer" 1
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45 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
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46 var_shift_rotate,cntlz,exts,isel")
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47 (eq_attr "cpu" "mpccore"))
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48 "iu_mpc")
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49
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50 (define_insn_reservation "mpccore-two" 1
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51 (and (eq_attr "type" "two")
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52 (eq_attr "cpu" "mpccore"))
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53 "iu_mpc,iu_mpc")
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55 (define_insn_reservation "mpccore-three" 1
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56 (and (eq_attr "type" "three")
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57 (eq_attr "cpu" "mpccore"))
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58 "iu_mpc,iu_mpc,iu_mpc")
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59
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60 (define_insn_reservation "mpccore-imul" 2
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61 (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
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62 (eq_attr "cpu" "mpccore"))
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63 "mciu_mpc")
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64
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65 ; Divide latency varies greatly from 2-11, use 6 as average
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66 (define_insn_reservation "mpccore-idiv" 6
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67 (and (eq_attr "type" "idiv")
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68 (eq_attr "cpu" "mpccore"))
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69 "mciu_mpc*6")
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70
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71 (define_insn_reservation "mpccore-compare" 3
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72 (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
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73 var_delayed_compare")
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74 (eq_attr "cpu" "mpccore"))
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75 "iu_mpc,nothing,bpu_mpc")
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76
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77 (define_insn_reservation "mpccore-fpcompare" 2
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78 (and (eq_attr "type" "fpcompare")
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79 (eq_attr "cpu" "mpccore"))
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80 "fpu_mpc,bpu_mpc")
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81
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82 (define_insn_reservation "mpccore-fp" 4
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83 (and (eq_attr "type" "fp")
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84 (eq_attr "cpu" "mpccore"))
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85 "fpu_mpc*2")
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86
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87 (define_insn_reservation "mpccore-dmul" 5
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88 (and (eq_attr "type" "dmul")
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89 (eq_attr "cpu" "mpccore"))
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90 "fpu_mpc*5")
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91
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92 (define_insn_reservation "mpccore-sdiv" 10
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93 (and (eq_attr "type" "sdiv")
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94 (eq_attr "cpu" "mpccore"))
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95 "fpu_mpc*10")
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96
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97 (define_insn_reservation "mpccore-ddiv" 17
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98 (and (eq_attr "type" "ddiv")
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99 (eq_attr "cpu" "mpccore"))
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100 "fpu_mpc*17")
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101
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102 (define_insn_reservation "mpccore-mtjmpr" 4
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103 (and (eq_attr "type" "mtjmpr,mfjmpr")
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104 (eq_attr "cpu" "mpccore"))
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105 "bpu_mpc")
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106
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107 (define_insn_reservation "mpccore-jmpreg" 1
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108 (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr,mfcr,mtcr,isync")
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109 (eq_attr "cpu" "mpccore"))
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110 "bpu_mpc")
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111