Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/sh/sh.opt @ 55:77e2b8dfacca gcc-4.4.5
update it from 4.4.3 to 4.5.0
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Fri, 12 Feb 2010 23:39:51 +0900 |
| parents | a06113de4d67 |
| children | b7f97abdc517 |
| rev | line source |
|---|---|
| 0 | 1 ; Options for the SH port of the compiler. |
| 2 | |
|
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77e2b8dfacca
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
3 ; Copyright (C) 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. |
| 0 | 4 ; |
| 5 ; This file is part of GCC. | |
| 6 ; | |
| 7 ; GCC is free software; you can redistribute it and/or modify it under | |
| 8 ; the terms of the GNU General Public License as published by the Free | |
| 9 ; Software Foundation; either version 3, or (at your option) any later | |
| 10 ; version. | |
| 11 ; | |
| 12 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
| 13 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 14 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 15 ; for more details. | |
| 16 ; | |
| 17 ; You should have received a copy of the GNU General Public License | |
| 18 ; along with GCC; see the file COPYING3. If not see | |
| 19 ; <http://www.gnu.org/licenses/>. | |
| 20 | |
| 21 ;; Used for various architecture options. | |
| 22 Mask(SH_E) | |
| 23 | |
| 24 ;; Set if the default precision of th FPU is single. | |
| 25 Mask(FPU_SINGLE) | |
| 26 | |
| 27 ;; Set if we should generate code using type 2A insns. | |
| 28 Mask(HARD_SH2A) | |
| 29 | |
| 30 ;; Set if we should generate code using type 2A DF insns. | |
| 31 Mask(HARD_SH2A_DOUBLE) | |
| 32 | |
| 33 ;; Set if compiling for SH4 hardware (to be used for insn costs etc.) | |
| 34 Mask(HARD_SH4) | |
| 35 | |
| 36 ;; Set if we should generate code for a SH5 CPU (either ISA). | |
| 37 Mask(SH5) | |
| 38 | |
| 39 ;; Set if we should save all target registers. | |
| 40 Mask(SAVE_ALL_TARGET_REGS) | |
| 41 | |
| 42 m1 | |
| 43 Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1) | |
| 44 Generate SH1 code | |
| 45 | |
| 46 m2 | |
| 47 Target RejectNegative Mask(SH2) Condition(SUPPORT_SH2) | |
| 48 Generate SH2 code | |
| 49 | |
| 50 m2a | |
| 51 Target RejectNegative Condition(SUPPORT_SH2A) | |
|
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77e2b8dfacca
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
52 Generate default double-precision SH2a-FPU code |
| 0 | 53 |
| 54 m2a-nofpu | |
| 55 Target RejectNegative Condition(SUPPORT_SH2A_NOFPU) | |
| 56 Generate SH2a FPU-less code | |
| 57 | |
| 58 m2a-single | |
| 59 Target RejectNegative Condition(SUPPORT_SH2A_SINGLE) | |
|
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
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changeset
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60 Generate default single-precision SH2a-FPU code |
| 0 | 61 |
| 62 m2a-single-only | |
| 63 Target RejectNegative Condition(SUPPORT_SH2A_SINGLE_ONLY) | |
|
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
64 Generate only single-precision SH2a-FPU code |
| 0 | 65 |
| 66 m2e | |
| 67 Target RejectNegative Condition(SUPPORT_SH2E) | |
| 68 Generate SH2e code | |
| 69 | |
| 70 m3 | |
| 71 Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) | |
| 72 Generate SH3 code | |
| 73 | |
| 74 m3e | |
| 75 Target RejectNegative Condition(SUPPORT_SH3E) | |
| 76 Generate SH3e code | |
| 77 | |
| 78 m4 | |
| 79 Target RejectNegative Mask(SH4) Condition(SUPPORT_SH4) | |
| 80 Generate SH4 code | |
| 81 | |
| 82 m4-100 | |
| 83 Target RejectNegative Condition(SUPPORT_SH4) | |
| 84 Generate SH4-100 code | |
| 85 | |
| 86 m4-200 | |
| 87 Target RejectNegative Condition(SUPPORT_SH4) | |
| 88 Generate SH4-200 code | |
| 89 | |
| 90 ;; TARGET_SH4_300 indicates if we have the ST40-300 instruction set and | |
| 91 ;; pipeline - irrespective of ABI. | |
| 92 m4-300 | |
| 93 Target RejectNegative Condition(SUPPORT_SH4) Var(TARGET_SH4_300) | |
| 94 Generate SH4-300 code | |
| 95 | |
| 96 m4-nofpu | |
| 97 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) | |
| 98 Generate SH4 FPU-less code | |
| 99 | |
| 100 m4-100-nofpu | |
| 101 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) | |
| 102 Generate SH4-100 FPU-less code | |
| 103 | |
| 104 m4-200-nofpu | |
| 105 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) | |
| 106 Generate SH4-200 FPU-less code | |
| 107 | |
| 108 m4-300-nofpu | |
| 109 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists | |
| 110 Generate SH4-300 FPU-less code | |
| 111 | |
| 112 m4-340 | |
| 113 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists | |
| 114 Generate code for SH4 340 series (MMU/FPU-less) | |
| 115 ;; passes -isa=sh4-nommu-nofpu to the assembler. | |
| 116 | |
| 117 m4-400 | |
| 118 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) | |
| 119 Generate code for SH4 400 series (MMU/FPU-less) | |
| 120 ;; passes -isa=sh4-nommu-nofpu to the assembler. | |
| 121 | |
| 122 m4-500 | |
| 123 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) | |
| 124 Generate code for SH4 500 series (FPU-less). | |
| 125 ;; passes -isa=sh4-nofpu to the assembler. | |
| 126 | |
| 127 m4-single | |
| 128 Target RejectNegative Condition(SUPPORT_SH4_SINGLE) | |
| 129 Generate default single-precision SH4 code | |
| 130 | |
| 131 m4-100-single | |
| 132 Target RejectNegative Condition(SUPPORT_SH4_SINGLE) | |
| 133 Generate default single-precision SH4-100 code | |
| 134 | |
| 135 m4-200-single | |
| 136 Target RejectNegative Condition(SUPPORT_SH4_SINGLE) | |
| 137 Generate default single-precision SH4-200 code | |
| 138 | |
| 139 m4-300-single | |
| 140 Target RejectNegative Condition(SUPPORT_SH4_SINGLE) Var(TARGET_SH4_300) VarExists | |
| 141 Generate default single-precision SH4-300 code | |
| 142 | |
| 143 m4-single-only | |
| 144 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) | |
| 145 Generate only single-precision SH4 code | |
| 146 | |
| 147 m4-100-single-only | |
| 148 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) | |
| 149 Generate only single-precision SH4-100 code | |
| 150 | |
| 151 m4-200-single-only | |
| 152 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) | |
| 153 Generate only single-precision SH4-200 code | |
| 154 | |
| 155 m4-300-single-only | |
| 156 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Var(TARGET_SH4_300) VarExists | |
| 157 Generate only single-precision SH4-300 code | |
| 158 | |
| 159 m4a | |
| 160 Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A) | |
| 161 Generate SH4a code | |
| 162 | |
| 163 m4a-nofpu | |
| 164 Target RejectNegative Condition(SUPPORT_SH4A_NOFPU) | |
| 165 Generate SH4a FPU-less code | |
| 166 | |
| 167 m4a-single | |
| 168 Target RejectNegative Condition(SUPPORT_SH4A_SINGLE) | |
| 169 Generate default single-precision SH4a code | |
| 170 | |
| 171 m4a-single-only | |
| 172 Target RejectNegative Condition(SUPPORT_SH4A_SINGLE_ONLY) | |
| 173 Generate only single-precision SH4a code | |
| 174 | |
| 175 m4al | |
| 176 Target RejectNegative Condition(SUPPORT_SH4AL) | |
| 177 Generate SH4al-dsp code | |
| 178 | |
| 179 m5-32media | |
| 180 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA) | |
| 181 Generate 32-bit SHmedia code | |
| 182 | |
| 183 m5-32media-nofpu | |
| 184 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU) | |
| 185 Generate 32-bit FPU-less SHmedia code | |
| 186 | |
| 187 m5-64media | |
| 188 Target RejectNegative Condition(SUPPORT_SH5_64MEDIA) | |
| 189 Generate 64-bit SHmedia code | |
| 190 | |
| 191 m5-64media-nofpu | |
| 192 Target RejectNegative Condition(SUPPORT_SH5_64MEDIA_NOFPU) | |
| 193 Generate 64-bit FPU-less SHmedia code | |
| 194 | |
| 195 m5-compact | |
| 196 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA) | |
| 197 Generate SHcompact code | |
| 198 | |
| 199 m5-compact-nofpu | |
| 200 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU) | |
| 201 Generate FPU-less SHcompact code | |
| 202 | |
| 203 madjust-unroll | |
| 204 Target Report Mask(ADJUST_UNROLL) Condition(SUPPORT_ANY_SH5) | |
| 205 Throttle unrolling to avoid thrashing target registers unless the unroll benefit outweighs this | |
| 206 | |
| 207 mb | |
| 208 Target Report RejectNegative InverseMask(LITTLE_ENDIAN) | |
| 209 Generate code in big endian mode | |
| 210 | |
| 211 mbigtable | |
| 212 Target Report RejectNegative Mask(BIGTABLE) | |
| 213 Generate 32-bit offsets in switch tables | |
| 214 | |
| 215 mbitops | |
| 216 Target Report RejectNegative Mask(BITOPS) | |
| 217 Generate bit instructions | |
| 218 | |
| 219 mbranch-cost= | |
| 220 Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1) | |
| 221 Cost to assume for a branch insn | |
| 222 | |
| 223 mcbranchdi | |
| 224 Target Var(TARGET_CBRANCHDI4) | |
| 225 Enable cbranchdi4 pattern | |
| 226 | |
| 227 mcmpeqdi | |
| 228 Target Var(TARGET_CMPEQDI_T) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
229 Emit cmpeqdi_t pattern even when -mcbranchdi is in effect. |
| 0 | 230 |
| 231 mcut2-workaround | |
| 232 Target RejectNegative Var(TARGET_SH5_CUT2_WORKAROUND) | |
| 233 Enable SH5 cut2 workaround | |
| 234 | |
| 235 mdalign | |
| 236 Target Report RejectNegative Mask(ALIGN_DOUBLE) | |
| 237 Align doubles at 64-bit boundaries | |
| 238 | |
| 239 mdiv= | |
| 240 Target RejectNegative Joined Var(sh_div_str) Init("") | |
| 241 Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table | |
| 242 | |
| 243 mdivsi3_libfunc= | |
| 244 Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("") | |
| 245 Specify name for 32 bit signed division function | |
| 246 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
247 mfmovd |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
248 Target RejectNegative Mask(FMOVD) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
249 Enable the use of 64-bit floating point registers in fmov instructions. See -mdalign if 64-bit alignment is required. |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
250 |
| 0 | 251 mfixed-range= |
| 252 Target RejectNegative Joined Var(sh_fixed_range_str) | |
| 253 Specify range of registers to make fixed | |
| 254 | |
| 255 mfused-madd | |
| 256 Target Var(TARGET_FMAC) | |
| 257 Enable the use of the fused floating point multiply-accumulate operation | |
| 258 | |
| 259 mgettrcost= | |
| 260 Target RejectNegative Joined UInteger Var(sh_gettrcost) Init(-1) | |
| 261 Cost to assume for gettr insn | |
| 262 | |
| 263 mhitachi | |
| 264 Target Report RejectNegative Mask(HITACHI) | |
| 265 Follow Renesas (formerly Hitachi) / SuperH calling conventions | |
| 266 | |
| 267 mieee | |
| 268 Target Report Mask(IEEE) | |
| 269 Increase the IEEE compliance for floating-point code | |
| 270 | |
| 271 mindexed-addressing | |
| 272 Target Report Mask(ALLOW_INDEXED_ADDRESS) Condition(SUPPORT_ANY_SH5_32MEDIA) | |
| 273 Enable the use of the indexed addressing mode for SHmedia32/SHcompact | |
| 274 | |
| 275 minline-ic_invalidate | |
| 276 Target Report Var(TARGET_INLINE_IC_INVALIDATE) | |
| 277 inline code to invalidate instruction cache entries after setting up nested function trampolines | |
| 278 | |
| 279 minvalid-symbols | |
| 280 Target Report Mask(INVALID_SYMBOLS) Condition(SUPPORT_ANY_SH5) | |
| 281 Assume symbols might be invalid | |
| 282 | |
| 283 misize | |
| 284 Target Report RejectNegative Mask(DUMPISIZE) | |
| 285 Annotate assembler instructions with estimated addresses | |
| 286 | |
| 287 ml | |
| 288 Target Report RejectNegative Mask(LITTLE_ENDIAN) | |
| 289 Generate code in little endian mode | |
| 290 | |
| 291 mnomacsave | |
| 292 Target Report RejectNegative Mask(NOMACSAVE) | |
| 293 Mark MAC register as call-clobbered | |
| 294 | |
| 295 ;; ??? This option is not useful, but is retained in case there are people | |
| 296 ;; who are still relying on it. It may be deleted in the future. | |
| 297 mpadstruct | |
| 298 Target Report RejectNegative Mask(PADSTRUCT) | |
| 299 Make structs a multiple of 4 bytes (warning: ABI altered) | |
| 300 | |
| 301 mprefergot | |
| 302 Target Report RejectNegative Mask(PREFERGOT) | |
| 303 Emit function-calls using global offset table when generating PIC | |
| 304 | |
| 305 mpt-fixed | |
| 306 Target Report Mask(PT_FIXED) Condition(SUPPORT_ANY_SH5) | |
| 307 Assume pt* instructions won't trap | |
| 308 | |
| 309 mrelax | |
| 310 Target Report RejectNegative Mask(RELAX) | |
| 311 Shorten address references during linking | |
| 312 | |
| 313 mrenesas | |
| 314 Target Mask(HITACHI) MaskExists | |
| 315 Follow Renesas (formerly Hitachi) / SuperH calling conventions | |
| 316 | |
| 317 mspace | |
| 318 Target Report RejectNegative Mask(SMALLCODE) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
319 Deprecated. Use -Os instead |
| 0 | 320 |
| 321 multcost= | |
| 322 Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1) | |
| 323 Cost to assume for a multiply insn | |
| 324 | |
| 325 musermode | |
| 326 Target Report RejectNegative Mask(USERMODE) | |
| 327 Don't generate privileged-mode only code; implies -mno-inline-ic_invalidate if the inline code would not work in user mode. | |
| 328 | |
| 329 ;; We might want to enable this by default for TARGET_HARD_SH4, because | |
| 330 ;; zero-offset branches have zero latency. Needs some benchmarking. | |
| 331 mpretend-cmove | |
| 332 Target Var(TARGET_PRETEND_CMOVE) | |
| 333 Pretend a branch-around-a-move is a conditional move. |