Mercurial > hg > CbC > CbC_gcc
annotate gcc/ira-costs.c @ 108:7ad14f446135
add CbC-example/rectypeTest/
| author | Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Thu, 14 Jun 2012 20:30:24 +0900 |
| parents | f6334be47118 |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
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1 /* IRA hard register and memory cost calculation for allocnos or pseudos. |
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2 Copyright (C) 2006, 2007, 2008, 2009, 2010 |
| 0 | 3 Free Software Foundation, Inc. |
| 4 Contributed by Vladimir Makarov <vmakarov@redhat.com>. | |
| 5 | |
| 6 This file is part of GCC. | |
| 7 | |
| 8 GCC is free software; you can redistribute it and/or modify it under | |
| 9 the terms of the GNU General Public License as published by the Free | |
| 10 Software Foundation; either version 3, or (at your option) any later | |
| 11 version. | |
| 12 | |
| 13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
| 14 WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 16 for more details. | |
| 17 | |
| 18 You should have received a copy of the GNU General Public License | |
| 19 along with GCC; see the file COPYING3. If not see | |
| 20 <http://www.gnu.org/licenses/>. */ | |
| 21 | |
| 22 #include "config.h" | |
| 23 #include "system.h" | |
| 24 #include "coretypes.h" | |
| 25 #include "tm.h" | |
| 26 #include "hard-reg-set.h" | |
| 27 #include "rtl.h" | |
| 28 #include "expr.h" | |
| 29 #include "tm_p.h" | |
| 30 #include "flags.h" | |
| 31 #include "basic-block.h" | |
| 32 #include "regs.h" | |
| 33 #include "addresses.h" | |
| 34 #include "insn-config.h" | |
| 35 #include "recog.h" | |
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36 #include "reload.h" |
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37 #include "diagnostic-core.h" |
| 0 | 38 #include "target.h" |
| 39 #include "params.h" | |
| 40 #include "ira-int.h" | |
| 41 | |
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42 /* The flags is set up every time when we calculate pseudo register |
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43 classes through function ira_set_pseudo_classes. */ |
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44 static bool pseudo_classes_defined_p = false; |
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45 |
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46 /* TRUE if we work with allocnos. Otherwise we work with pseudos. */ |
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47 static bool allocno_p; |
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48 |
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49 /* Number of elements in arrays `in_inc_dec' and `costs'. */ |
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50 static int cost_elements_num; |
| 0 | 51 |
| 52 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
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53 /* Indexed by n, is TRUE if allocno or pseudo with number N is used in |
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54 an auto-inc or auto-dec context. */ |
| 0 | 55 static bool *in_inc_dec; |
| 56 #endif | |
| 57 | |
| 58 /* The `costs' struct records the cost of using hard registers of each | |
| 59 class considered for the calculation and of using memory for each | |
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60 allocno or pseudo. */ |
| 0 | 61 struct costs |
| 62 { | |
| 63 int mem_cost; | |
| 64 /* Costs for register classes start here. We process only some | |
| 65 register classes (cover classes on the 1st cost calculation | |
| 66 iteration and important classes on the 2nd iteration). */ | |
| 67 int cost[1]; | |
| 68 }; | |
| 69 | |
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70 #define max_struct_costs_size \ |
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71 (this_target_ira_int->x_max_struct_costs_size) |
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72 #define init_cost \ |
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73 (this_target_ira_int->x_init_cost) |
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74 #define temp_costs \ |
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75 (this_target_ira_int->x_temp_costs) |
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76 #define op_costs \ |
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77 (this_target_ira_int->x_op_costs) |
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78 #define this_op_costs \ |
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79 (this_target_ira_int->x_this_op_costs) |
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80 #define cost_classes \ |
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81 (this_target_ira_int->x_cost_classes) |
| 0 | 82 |
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83 /* Costs of each class for each allocno or pseudo. */ |
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84 static struct costs *costs; |
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85 |
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86 /* Accumulated costs of each class for each allocno. */ |
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87 static struct costs *total_allocno_costs; |
| 0 | 88 |
| 89 /* The size of the previous array. */ | |
| 90 static int cost_classes_num; | |
| 91 | |
| 92 /* Map: cost class -> order number (they start with 0) of the cost | |
| 93 class. The order number is negative for non-cost classes. */ | |
| 94 static int cost_class_nums[N_REG_CLASSES]; | |
| 95 | |
| 96 /* It is the current size of struct costs. */ | |
| 97 static int struct_costs_size; | |
| 98 | |
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99 /* Return pointer to structure containing costs of allocno or pseudo |
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100 with given NUM in array ARR. */ |
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101 #define COSTS(arr, num) \ |
| 0 | 102 ((struct costs *) ((char *) (arr) + (num) * struct_costs_size)) |
| 103 | |
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104 /* Return index in COSTS when processing reg with REGNO. */ |
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105 #define COST_INDEX(regno) (allocno_p \ |
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106 ? ALLOCNO_NUM (ira_curr_regno_allocno_map[regno]) \ |
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107 : (int) regno) |
| 0 | 108 |
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109 /* Record register class preferences of each allocno or pseudo. Null |
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110 value means no preferences. It happens on the 1st iteration of the |
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111 cost calculation. */ |
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112 static enum reg_class *pref; |
| 0 | 113 |
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114 /* Allocated buffers for pref. */ |
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115 static enum reg_class *pref_buffer; |
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116 |
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117 /* Record cover register class of each allocno with the same regno. */ |
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118 static enum reg_class *regno_cover_class; |
| 0 | 119 |
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120 /* Record cost gains for not allocating a register with an invariant |
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121 equivalence. */ |
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122 static int *regno_equiv_gains; |
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123 |
| 0 | 124 /* Execution frequency of the current insn. */ |
| 125 static int frequency; | |
| 126 | |
| 127 | |
| 128 | |
| 129 /* Compute the cost of loading X into (if TO_P is TRUE) or from (if | |
| 130 TO_P is FALSE) a register of class RCLASS in mode MODE. X must not | |
| 131 be a pseudo register. */ | |
| 132 static int | |
|
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133 copy_cost (rtx x, enum machine_mode mode, reg_class_t rclass, bool to_p, |
| 0 | 134 secondary_reload_info *prev_sri) |
| 135 { | |
| 136 secondary_reload_info sri; | |
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137 reg_class_t secondary_class = NO_REGS; |
| 0 | 138 |
| 139 /* If X is a SCRATCH, there is actually nothing to move since we are | |
| 140 assuming optimal allocation. */ | |
| 141 if (GET_CODE (x) == SCRATCH) | |
| 142 return 0; | |
| 143 | |
| 144 /* Get the class we will actually use for a reload. */ | |
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145 rclass = targetm.preferred_reload_class (x, rclass); |
| 0 | 146 |
| 147 /* If we need a secondary reload for an intermediate, the cost is | |
| 148 that to load the input into the intermediate register, then to | |
| 149 copy it. */ | |
| 150 sri.prev_sri = prev_sri; | |
| 151 sri.extra_cost = 0; | |
| 152 secondary_class = targetm.secondary_reload (to_p, x, rclass, mode, &sri); | |
| 153 | |
| 154 if (secondary_class != NO_REGS) | |
| 155 { | |
| 156 if (!move_cost[mode]) | |
| 157 init_move_cost (mode); | |
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158 return (move_cost[mode][(int) secondary_class][(int) rclass] |
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159 + sri.extra_cost |
| 0 | 160 + copy_cost (x, mode, secondary_class, to_p, &sri)); |
| 161 } | |
| 162 | |
| 163 /* For memory, use the memory move cost, for (hard) registers, use | |
| 164 the cost to move between the register classes, and use 2 for | |
| 165 everything else (constants). */ | |
| 166 if (MEM_P (x) || rclass == NO_REGS) | |
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167 return sri.extra_cost |
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168 + ira_memory_move_cost[mode][(int) rclass][to_p != 0]; |
| 0 | 169 else if (REG_P (x)) |
| 170 { | |
| 171 if (!move_cost[mode]) | |
| 172 init_move_cost (mode); | |
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173 return (sri.extra_cost |
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174 + move_cost[mode][REGNO_REG_CLASS (REGNO (x))][(int) rclass]); |
| 0 | 175 } |
| 176 else | |
| 177 /* If this is a constant, we may eventually want to call rtx_cost | |
| 178 here. */ | |
| 179 return sri.extra_cost + COSTS_N_INSNS (1); | |
| 180 } | |
| 181 | |
| 182 | |
| 183 | |
| 184 /* Record the cost of using memory or hard registers of various | |
| 185 classes for the operands in INSN. | |
| 186 | |
| 187 N_ALTS is the number of alternatives. | |
| 188 N_OPS is the number of operands. | |
| 189 OPS is an array of the operands. | |
| 190 MODES are the modes of the operands, in case any are VOIDmode. | |
| 191 CONSTRAINTS are the constraints to use for the operands. This array | |
| 192 is modified by this procedure. | |
| 193 | |
| 194 This procedure works alternative by alternative. For each | |
| 195 alternative we assume that we will be able to allocate all allocnos | |
| 196 to their ideal register class and calculate the cost of using that | |
| 197 alternative. Then we compute, for each operand that is a | |
| 198 pseudo-register, the cost of having the allocno allocated to each | |
| 199 register class and using it in that alternative. To this cost is | |
| 200 added the cost of the alternative. | |
| 201 | |
| 202 The cost of each class for this insn is its lowest cost among all | |
| 203 the alternatives. */ | |
| 204 static void | |
| 205 record_reg_classes (int n_alts, int n_ops, rtx *ops, | |
| 206 enum machine_mode *modes, const char **constraints, | |
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207 rtx insn, enum reg_class *pref) |
| 0 | 208 { |
| 209 int alt; | |
| 210 int i, j, k; | |
| 211 rtx set; | |
| 212 int insn_allows_mem[MAX_RECOG_OPERANDS]; | |
| 213 | |
| 214 for (i = 0; i < n_ops; i++) | |
| 215 insn_allows_mem[i] = 0; | |
| 216 | |
| 217 /* Process each alternative, each time minimizing an operand's cost | |
| 218 with the cost for each operand in that alternative. */ | |
| 219 for (alt = 0; alt < n_alts; alt++) | |
| 220 { | |
| 221 enum reg_class classes[MAX_RECOG_OPERANDS]; | |
| 222 int allows_mem[MAX_RECOG_OPERANDS]; | |
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223 enum reg_class rclass; |
| 0 | 224 int alt_fail = 0; |
| 225 int alt_cost = 0, op_cost_add; | |
| 226 | |
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227 if (!recog_data.alternative_enabled_p[alt]) |
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228 { |
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229 for (i = 0; i < recog_data.n_operands; i++) |
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230 constraints[i] = skip_alternative (constraints[i]); |
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231 |
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232 continue; |
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233 } |
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234 |
| 0 | 235 for (i = 0; i < n_ops; i++) |
| 236 { | |
| 237 unsigned char c; | |
| 238 const char *p = constraints[i]; | |
| 239 rtx op = ops[i]; | |
| 240 enum machine_mode mode = modes[i]; | |
| 241 int allows_addr = 0; | |
| 242 int win = 0; | |
| 243 | |
| 244 /* Initially show we know nothing about the register class. */ | |
| 245 classes[i] = NO_REGS; | |
| 246 allows_mem[i] = 0; | |
| 247 | |
| 248 /* If this operand has no constraints at all, we can | |
| 249 conclude nothing about it since anything is valid. */ | |
| 250 if (*p == 0) | |
| 251 { | |
| 252 if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
| 253 memset (this_op_costs[i], 0, struct_costs_size); | |
| 254 continue; | |
| 255 } | |
| 256 | |
| 257 /* If this alternative is only relevant when this operand | |
| 258 matches a previous operand, we do different things | |
| 259 depending on whether this operand is a allocno-reg or not. | |
| 260 We must process any modifiers for the operand before we | |
| 261 can make this test. */ | |
| 262 while (*p == '%' || *p == '=' || *p == '+' || *p == '&') | |
| 263 p++; | |
| 264 | |
| 265 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) | |
| 266 { | |
| 267 /* Copy class and whether memory is allowed from the | |
| 268 matching alternative. Then perform any needed cost | |
| 269 computations and/or adjustments. */ | |
| 270 j = p[0] - '0'; | |
| 271 classes[i] = classes[j]; | |
| 272 allows_mem[i] = allows_mem[j]; | |
| 273 if (allows_mem[i]) | |
| 274 insn_allows_mem[i] = 1; | |
| 275 | |
| 276 if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
| 277 { | |
| 278 /* If this matches the other operand, we have no | |
| 279 added cost and we win. */ | |
| 280 if (rtx_equal_p (ops[j], op)) | |
| 281 win = 1; | |
| 282 /* If we can put the other operand into a register, | |
| 283 add to the cost of this alternative the cost to | |
| 284 copy this operand to the register used for the | |
| 285 other operand. */ | |
| 286 else if (classes[j] != NO_REGS) | |
| 287 { | |
| 288 alt_cost += copy_cost (op, mode, classes[j], 1, NULL); | |
| 289 win = 1; | |
| 290 } | |
| 291 } | |
| 292 else if (! REG_P (ops[j]) | |
| 293 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
| 294 { | |
| 295 /* This op is an allocno but the one it matches is | |
| 296 not. */ | |
| 297 | |
| 298 /* If we can't put the other operand into a | |
| 299 register, this alternative can't be used. */ | |
| 300 | |
| 301 if (classes[j] == NO_REGS) | |
| 302 alt_fail = 1; | |
| 303 /* Otherwise, add to the cost of this alternative | |
| 304 the cost to copy the other operand to the hard | |
| 305 register used for this operand. */ | |
| 306 else | |
| 307 alt_cost += copy_cost (ops[j], mode, classes[j], 1, NULL); | |
| 308 } | |
| 309 else | |
| 310 { | |
| 311 /* The costs of this operand are not the same as the | |
| 312 other operand since move costs are not symmetric. | |
| 313 Moreover, if we cannot tie them, this alternative | |
| 314 needs to do a copy, which is one insn. */ | |
| 315 struct costs *pp = this_op_costs[i]; | |
| 316 | |
| 317 for (k = 0; k < cost_classes_num; k++) | |
| 318 { | |
| 319 rclass = cost_classes[k]; | |
| 320 pp->cost[k] | |
|
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321 = (((recog_data.operand_type[i] != OP_OUT |
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322 ? ira_get_may_move_cost (mode, rclass, |
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323 classes[i], true) : 0) |
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324 + (recog_data.operand_type[i] != OP_IN |
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325 ? ira_get_may_move_cost (mode, classes[i], |
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326 rclass, false) : 0)) |
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327 * frequency); |
| 0 | 328 } |
| 329 | |
| 330 /* If the alternative actually allows memory, make | |
| 331 things a bit cheaper since we won't need an extra | |
| 332 insn to load it. */ | |
| 333 pp->mem_cost | |
| 334 = ((recog_data.operand_type[i] != OP_IN | |
| 335 ? ira_memory_move_cost[mode][classes[i]][0] : 0) | |
| 336 + (recog_data.operand_type[i] != OP_OUT | |
| 337 ? ira_memory_move_cost[mode][classes[i]][1] : 0) | |
| 338 - allows_mem[i]) * frequency; | |
| 339 | |
| 340 /* If we have assigned a class to this allocno in our | |
| 341 first pass, add a cost to this alternative | |
| 342 corresponding to what we would add if this allocno | |
| 343 were not in the appropriate class. We could use | |
| 344 cover class here but it is less accurate | |
| 345 approximation. */ | |
|
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346 if (pref) |
| 0 | 347 { |
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348 enum reg_class pref_class = pref[COST_INDEX (REGNO (op))]; |
| 0 | 349 |
| 350 if (pref_class == NO_REGS) | |
| 351 alt_cost | |
| 352 += ((recog_data.operand_type[i] != OP_IN | |
| 353 ? ira_memory_move_cost[mode][classes[i]][0] | |
| 354 : 0) | |
| 355 + (recog_data.operand_type[i] != OP_OUT | |
| 356 ? ira_memory_move_cost[mode][classes[i]][1] | |
| 357 : 0)); | |
| 358 else if (ira_reg_class_intersect | |
| 359 [pref_class][classes[i]] == NO_REGS) | |
|
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360 alt_cost += ira_get_register_move_cost (mode, |
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361 pref_class, |
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362 classes[i]); |
| 0 | 363 } |
| 364 if (REGNO (ops[i]) != REGNO (ops[j]) | |
| 365 && ! find_reg_note (insn, REG_DEAD, op)) | |
| 366 alt_cost += 2; | |
| 367 | |
| 368 /* This is in place of ordinary cost computation for | |
| 369 this operand, so skip to the end of the | |
| 370 alternative (should be just one character). */ | |
| 371 while (*p && *p++ != ',') | |
| 372 ; | |
| 373 | |
| 374 constraints[i] = p; | |
| 375 continue; | |
| 376 } | |
| 377 } | |
|
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378 |
| 0 | 379 /* Scan all the constraint letters. See if the operand |
| 380 matches any of the constraints. Collect the valid | |
| 381 register classes and see if this operand accepts | |
| 382 memory. */ | |
| 383 while ((c = *p)) | |
| 384 { | |
| 385 switch (c) | |
| 386 { | |
| 387 case ',': | |
| 388 break; | |
| 389 case '*': | |
| 390 /* Ignore the next letter for this pass. */ | |
| 391 c = *++p; | |
| 392 break; | |
| 393 | |
| 394 case '?': | |
| 395 alt_cost += 2; | |
| 396 case '!': case '#': case '&': | |
| 397 case '0': case '1': case '2': case '3': case '4': | |
| 398 case '5': case '6': case '7': case '8': case '9': | |
| 399 break; | |
| 400 | |
| 401 case 'p': | |
| 402 allows_addr = 1; | |
| 403 win = address_operand (op, GET_MODE (op)); | |
| 404 /* We know this operand is an address, so we want it | |
| 405 to be allocated to a register that can be the | |
| 406 base of an address, i.e. BASE_REG_CLASS. */ | |
| 407 classes[i] | |
| 408 = ira_reg_class_union[classes[i]] | |
| 409 [base_reg_class (VOIDmode, ADDRESS, SCRATCH)]; | |
| 410 break; | |
| 411 | |
| 412 case 'm': case 'o': case 'V': | |
| 413 /* It doesn't seem worth distinguishing between | |
| 414 offsettable and non-offsettable addresses | |
| 415 here. */ | |
| 416 insn_allows_mem[i] = allows_mem[i] = 1; | |
| 417 if (MEM_P (op)) | |
| 418 win = 1; | |
| 419 break; | |
| 420 | |
| 421 case '<': | |
| 422 if (MEM_P (op) | |
| 423 && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
| 424 || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
| 425 win = 1; | |
| 426 break; | |
| 427 | |
| 428 case '>': | |
| 429 if (MEM_P (op) | |
| 430 && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
| 431 || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
| 432 win = 1; | |
| 433 break; | |
| 434 | |
| 435 case 'E': | |
| 436 case 'F': | |
| 437 if (GET_CODE (op) == CONST_DOUBLE | |
| 438 || (GET_CODE (op) == CONST_VECTOR | |
| 439 && (GET_MODE_CLASS (GET_MODE (op)) | |
| 440 == MODE_VECTOR_FLOAT))) | |
| 441 win = 1; | |
| 442 break; | |
| 443 | |
| 444 case 'G': | |
| 445 case 'H': | |
| 446 if (GET_CODE (op) == CONST_DOUBLE | |
| 447 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p)) | |
| 448 win = 1; | |
| 449 break; | |
| 450 | |
| 451 case 's': | |
|
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452 if (CONST_INT_P (op) |
| 0 | 453 || (GET_CODE (op) == CONST_DOUBLE |
| 454 && GET_MODE (op) == VOIDmode)) | |
| 455 break; | |
| 456 | |
| 457 case 'i': | |
| 458 if (CONSTANT_P (op) | |
| 459 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))) | |
| 460 win = 1; | |
| 461 break; | |
| 462 | |
| 463 case 'n': | |
|
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464 if (CONST_INT_P (op) |
| 0 | 465 || (GET_CODE (op) == CONST_DOUBLE |
| 466 && GET_MODE (op) == VOIDmode)) | |
| 467 win = 1; | |
| 468 break; | |
| 469 | |
| 470 case 'I': | |
| 471 case 'J': | |
| 472 case 'K': | |
| 473 case 'L': | |
| 474 case 'M': | |
| 475 case 'N': | |
| 476 case 'O': | |
| 477 case 'P': | |
|
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478 if (CONST_INT_P (op) |
| 0 | 479 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p)) |
| 480 win = 1; | |
| 481 break; | |
| 482 | |
| 483 case 'X': | |
| 484 win = 1; | |
| 485 break; | |
| 486 | |
| 487 case 'g': | |
| 488 if (MEM_P (op) | |
| 489 || (CONSTANT_P (op) | |
| 490 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)))) | |
| 491 win = 1; | |
| 492 insn_allows_mem[i] = allows_mem[i] = 1; | |
| 493 case 'r': | |
| 494 classes[i] = ira_reg_class_union[classes[i]][GENERAL_REGS]; | |
| 495 break; | |
| 496 | |
| 497 default: | |
| 498 if (REG_CLASS_FROM_CONSTRAINT (c, p) != NO_REGS) | |
| 499 classes[i] = ira_reg_class_union[classes[i]] | |
| 500 [REG_CLASS_FROM_CONSTRAINT (c, p)]; | |
| 501 #ifdef EXTRA_CONSTRAINT_STR | |
| 502 else if (EXTRA_CONSTRAINT_STR (op, c, p)) | |
| 503 win = 1; | |
| 504 | |
| 505 if (EXTRA_MEMORY_CONSTRAINT (c, p)) | |
| 506 { | |
| 507 /* Every MEM can be reloaded to fit. */ | |
| 508 insn_allows_mem[i] = allows_mem[i] = 1; | |
| 509 if (MEM_P (op)) | |
| 510 win = 1; | |
| 511 } | |
| 512 if (EXTRA_ADDRESS_CONSTRAINT (c, p)) | |
| 513 { | |
| 514 /* Every address can be reloaded to fit. */ | |
| 515 allows_addr = 1; | |
| 516 if (address_operand (op, GET_MODE (op))) | |
| 517 win = 1; | |
| 518 /* We know this operand is an address, so we | |
| 519 want it to be allocated to a hard register | |
| 520 that can be the base of an address, | |
| 521 i.e. BASE_REG_CLASS. */ | |
| 522 classes[i] | |
| 523 = ira_reg_class_union[classes[i]] | |
| 524 [base_reg_class (VOIDmode, ADDRESS, SCRATCH)]; | |
| 525 } | |
| 526 #endif | |
| 527 break; | |
| 528 } | |
| 529 p += CONSTRAINT_LEN (c, p); | |
| 530 if (c == ',') | |
| 531 break; | |
| 532 } | |
| 533 | |
| 534 constraints[i] = p; | |
| 535 | |
| 536 /* How we account for this operand now depends on whether it | |
| 537 is a pseudo register or not. If it is, we first check if | |
| 538 any register classes are valid. If not, we ignore this | |
| 539 alternative, since we want to assume that all allocnos get | |
| 540 allocated for register preferencing. If some register | |
| 541 class is valid, compute the costs of moving the allocno | |
| 542 into that class. */ | |
| 543 if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
| 544 { | |
| 545 if (classes[i] == NO_REGS) | |
| 546 { | |
| 547 /* We must always fail if the operand is a REG, but | |
| 548 we did not find a suitable class. | |
| 549 | |
| 550 Otherwise we may perform an uninitialized read | |
| 551 from this_op_costs after the `continue' statement | |
| 552 below. */ | |
| 553 alt_fail = 1; | |
| 554 } | |
| 555 else | |
| 556 { | |
| 557 struct costs *pp = this_op_costs[i]; | |
| 558 | |
| 559 for (k = 0; k < cost_classes_num; k++) | |
| 560 { | |
| 561 rclass = cost_classes[k]; | |
| 562 pp->cost[k] | |
|
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563 = (((recog_data.operand_type[i] != OP_OUT |
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564 ? ira_get_may_move_cost (mode, rclass, |
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565 classes[i], true) : 0) |
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566 + (recog_data.operand_type[i] != OP_IN |
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567 ? ira_get_may_move_cost (mode, classes[i], |
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568 rclass, false) : 0)) |
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569 * frequency); |
| 0 | 570 } |
| 571 | |
| 572 /* If the alternative actually allows memory, make | |
| 573 things a bit cheaper since we won't need an extra | |
| 574 insn to load it. */ | |
| 575 pp->mem_cost | |
| 576 = ((recog_data.operand_type[i] != OP_IN | |
| 577 ? ira_memory_move_cost[mode][classes[i]][0] : 0) | |
| 578 + (recog_data.operand_type[i] != OP_OUT | |
| 579 ? ira_memory_move_cost[mode][classes[i]][1] : 0) | |
| 580 - allows_mem[i]) * frequency; | |
| 581 /* If we have assigned a class to this allocno in our | |
| 582 first pass, add a cost to this alternative | |
| 583 corresponding to what we would add if this allocno | |
| 584 were not in the appropriate class. We could use | |
| 585 cover class here but it is less accurate | |
| 586 approximation. */ | |
|
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587 if (pref) |
| 0 | 588 { |
|
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589 enum reg_class pref_class = pref[COST_INDEX (REGNO (op))]; |
| 0 | 590 |
| 591 if (pref_class == NO_REGS) | |
| 592 alt_cost | |
| 593 += ((recog_data.operand_type[i] != OP_IN | |
| 594 ? ira_memory_move_cost[mode][classes[i]][0] | |
| 595 : 0) | |
| 596 + (recog_data.operand_type[i] != OP_OUT | |
| 597 ? ira_memory_move_cost[mode][classes[i]][1] | |
| 598 : 0)); | |
| 599 else if (ira_reg_class_intersect[pref_class][classes[i]] | |
| 600 == NO_REGS) | |
|
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601 alt_cost += ira_get_register_move_cost (mode, |
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602 pref_class, |
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603 classes[i]); |
| 0 | 604 } |
| 605 } | |
| 606 } | |
| 607 | |
| 608 /* Otherwise, if this alternative wins, either because we | |
| 609 have already determined that or if we have a hard | |
| 610 register of the proper class, there is no cost for this | |
| 611 alternative. */ | |
| 612 else if (win || (REG_P (op) | |
| 613 && reg_fits_class_p (op, classes[i], | |
| 614 0, GET_MODE (op)))) | |
| 615 ; | |
| 616 | |
| 617 /* If registers are valid, the cost of this alternative | |
| 618 includes copying the object to and/or from a | |
| 619 register. */ | |
| 620 else if (classes[i] != NO_REGS) | |
| 621 { | |
| 622 if (recog_data.operand_type[i] != OP_OUT) | |
| 623 alt_cost += copy_cost (op, mode, classes[i], 1, NULL); | |
| 624 | |
| 625 if (recog_data.operand_type[i] != OP_IN) | |
| 626 alt_cost += copy_cost (op, mode, classes[i], 0, NULL); | |
| 627 } | |
| 628 /* The only other way this alternative can be used is if | |
| 629 this is a constant that could be placed into memory. */ | |
| 630 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) | |
| 631 alt_cost += ira_memory_move_cost[mode][classes[i]][1]; | |
| 632 else | |
| 633 alt_fail = 1; | |
| 634 } | |
| 635 | |
| 636 if (alt_fail) | |
| 637 continue; | |
| 638 | |
| 639 op_cost_add = alt_cost * frequency; | |
| 640 /* Finally, update the costs with the information we've | |
| 641 calculated about this alternative. */ | |
| 642 for (i = 0; i < n_ops; i++) | |
| 643 if (REG_P (ops[i]) && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
| 644 { | |
| 645 struct costs *pp = op_costs[i], *qq = this_op_costs[i]; | |
| 646 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); | |
| 647 | |
| 648 pp->mem_cost = MIN (pp->mem_cost, | |
| 649 (qq->mem_cost + op_cost_add) * scale); | |
| 650 | |
| 651 for (k = 0; k < cost_classes_num; k++) | |
| 652 pp->cost[k] | |
| 653 = MIN (pp->cost[k], (qq->cost[k] + op_cost_add) * scale); | |
| 654 } | |
| 655 } | |
| 656 | |
|
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657 if (allocno_p) |
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658 for (i = 0; i < n_ops; i++) |
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659 { |
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660 ira_allocno_t a; |
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661 rtx op = ops[i]; |
| 0 | 662 |
|
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663 if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER) |
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664 continue; |
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665 a = ira_curr_regno_allocno_map [REGNO (op)]; |
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666 if (! ALLOCNO_BAD_SPILL_P (a) && insn_allows_mem[i] == 0) |
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667 ALLOCNO_BAD_SPILL_P (a) = true; |
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668 } |
| 0 | 669 |
| 670 /* If this insn is a single set copying operand 1 to operand 0 and | |
| 671 one operand is an allocno with the other a hard reg or an allocno | |
| 672 that prefers a hard register that is in its own register class | |
| 673 then we may want to adjust the cost of that register class to -1. | |
| 674 | |
| 675 Avoid the adjustment if the source does not die to avoid | |
| 676 stressing of register allocator by preferrencing two colliding | |
| 677 registers into single class. | |
| 678 | |
| 679 Also avoid the adjustment if a copy between hard registers of the | |
| 680 class is expensive (ten times the cost of a default copy is | |
| 681 considered arbitrarily expensive). This avoids losing when the | |
| 682 preferred class is very expensive as the source of a copy | |
| 683 instruction. */ | |
| 684 if ((set = single_set (insn)) != 0 | |
| 685 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
| 686 && REG_P (ops[0]) && REG_P (ops[1]) | |
| 687 && find_regno_note (insn, REG_DEAD, REGNO (ops[1]))) | |
| 688 for (i = 0; i <= 1; i++) | |
| 689 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
| 690 { | |
| 691 unsigned int regno = REGNO (ops[!i]); | |
| 692 enum machine_mode mode = GET_MODE (ops[!i]); | |
|
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693 enum reg_class rclass; |
| 0 | 694 unsigned int nr; |
| 695 | |
| 696 if (regno < FIRST_PSEUDO_REGISTER) | |
| 697 for (k = 0; k < cost_classes_num; k++) | |
| 698 { | |
| 699 rclass = cost_classes[k]; | |
| 700 if (TEST_HARD_REG_BIT (reg_class_contents[rclass], regno) | |
| 701 && (reg_class_size[rclass] | |
| 702 == (unsigned) CLASS_MAX_NREGS (rclass, mode))) | |
| 703 { | |
| 704 if (reg_class_size[rclass] == 1) | |
| 705 op_costs[i]->cost[k] = -frequency; | |
| 706 else | |
| 707 { | |
| 708 for (nr = 0; | |
| 709 nr < (unsigned) hard_regno_nregs[regno][mode]; | |
| 710 nr++) | |
| 711 if (! TEST_HARD_REG_BIT (reg_class_contents[rclass], | |
| 712 regno + nr)) | |
| 713 break; | |
|
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714 |
| 0 | 715 if (nr == (unsigned) hard_regno_nregs[regno][mode]) |
| 716 op_costs[i]->cost[k] = -frequency; | |
| 717 } | |
| 718 } | |
| 719 } | |
| 720 } | |
| 721 } | |
| 722 | |
| 723 | |
| 724 | |
| 725 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */ | |
| 726 static inline bool | |
| 727 ok_for_index_p_nonstrict (rtx reg) | |
| 728 { | |
| 729 unsigned regno = REGNO (reg); | |
| 730 | |
| 731 return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno); | |
| 732 } | |
| 733 | |
| 734 /* A version of regno_ok_for_base_p for use here, when all | |
| 735 pseudo-registers should count as OK. Arguments as for | |
| 736 regno_ok_for_base_p. */ | |
| 737 static inline bool | |
| 738 ok_for_base_p_nonstrict (rtx reg, enum machine_mode mode, | |
| 739 enum rtx_code outer_code, enum rtx_code index_code) | |
| 740 { | |
| 741 unsigned regno = REGNO (reg); | |
| 742 | |
| 743 if (regno >= FIRST_PSEUDO_REGISTER) | |
| 744 return true; | |
| 745 return ok_for_base_p_1 (regno, mode, outer_code, index_code); | |
| 746 } | |
| 747 | |
| 748 /* Record the pseudo registers we must reload into hard registers in a | |
| 749 subexpression of a memory address, X. | |
| 750 | |
| 751 If CONTEXT is 0, we are looking at the base part of an address, | |
| 752 otherwise we are looking at the index part. | |
| 753 | |
| 754 MODE is the mode of the memory reference; OUTER_CODE and INDEX_CODE | |
| 755 give the context that the rtx appears in. These three arguments | |
| 756 are passed down to base_reg_class. | |
| 757 | |
| 758 SCALE is twice the amount to multiply the cost by (it is twice so | |
| 759 we can represent half-cost adjustments). */ | |
| 760 static void | |
| 761 record_address_regs (enum machine_mode mode, rtx x, int context, | |
| 762 enum rtx_code outer_code, enum rtx_code index_code, | |
| 763 int scale) | |
| 764 { | |
| 765 enum rtx_code code = GET_CODE (x); | |
| 766 enum reg_class rclass; | |
| 767 | |
| 768 if (context == 1) | |
| 769 rclass = INDEX_REG_CLASS; | |
| 770 else | |
| 771 rclass = base_reg_class (mode, outer_code, index_code); | |
| 772 | |
| 773 switch (code) | |
| 774 { | |
| 775 case CONST_INT: | |
| 776 case CONST: | |
| 777 case CC0: | |
| 778 case PC: | |
| 779 case SYMBOL_REF: | |
| 780 case LABEL_REF: | |
| 781 return; | |
| 782 | |
| 783 case PLUS: | |
| 784 /* When we have an address that is a sum, we must determine | |
| 785 whether registers are "base" or "index" regs. If there is a | |
| 786 sum of two registers, we must choose one to be the "base". | |
| 787 Luckily, we can use the REG_POINTER to make a good choice | |
| 788 most of the time. We only need to do this on machines that | |
| 789 can have two registers in an address and where the base and | |
| 790 index register classes are different. | |
| 791 | |
| 792 ??? This code used to set REGNO_POINTER_FLAG in some cases, | |
| 793 but that seems bogus since it should only be set when we are | |
| 794 sure the register is being used as a pointer. */ | |
| 795 { | |
| 796 rtx arg0 = XEXP (x, 0); | |
| 797 rtx arg1 = XEXP (x, 1); | |
| 798 enum rtx_code code0 = GET_CODE (arg0); | |
| 799 enum rtx_code code1 = GET_CODE (arg1); | |
| 800 | |
| 801 /* Look inside subregs. */ | |
| 802 if (code0 == SUBREG) | |
| 803 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); | |
| 804 if (code1 == SUBREG) | |
| 805 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); | |
| 806 | |
| 807 /* If this machine only allows one register per address, it | |
| 808 must be in the first operand. */ | |
| 809 if (MAX_REGS_PER_ADDRESS == 1) | |
| 810 record_address_regs (mode, arg0, 0, PLUS, code1, scale); | |
| 811 | |
| 812 /* If index and base registers are the same on this machine, | |
| 813 just record registers in any non-constant operands. We | |
| 814 assume here, as well as in the tests below, that all | |
| 815 addresses are in canonical form. */ | |
| 816 else if (INDEX_REG_CLASS == base_reg_class (VOIDmode, PLUS, SCRATCH)) | |
| 817 { | |
| 818 record_address_regs (mode, arg0, context, PLUS, code1, scale); | |
| 819 if (! CONSTANT_P (arg1)) | |
| 820 record_address_regs (mode, arg1, context, PLUS, code0, scale); | |
| 821 } | |
| 822 | |
| 823 /* If the second operand is a constant integer, it doesn't | |
| 824 change what class the first operand must be. */ | |
| 825 else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
| 826 record_address_regs (mode, arg0, context, PLUS, code1, scale); | |
| 827 /* If the second operand is a symbolic constant, the first | |
| 828 operand must be an index register. */ | |
| 829 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
| 830 record_address_regs (mode, arg0, 1, PLUS, code1, scale); | |
| 831 /* If both operands are registers but one is already a hard | |
| 832 register of index or reg-base class, give the other the | |
| 833 class that the hard register is not. */ | |
| 834 else if (code0 == REG && code1 == REG | |
| 835 && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
| 836 && (ok_for_base_p_nonstrict (arg0, mode, PLUS, REG) | |
| 837 || ok_for_index_p_nonstrict (arg0))) | |
| 838 record_address_regs (mode, arg1, | |
| 839 ok_for_base_p_nonstrict (arg0, mode, PLUS, REG) | |
| 840 ? 1 : 0, | |
| 841 PLUS, REG, scale); | |
| 842 else if (code0 == REG && code1 == REG | |
| 843 && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
| 844 && (ok_for_base_p_nonstrict (arg1, mode, PLUS, REG) | |
| 845 || ok_for_index_p_nonstrict (arg1))) | |
| 846 record_address_regs (mode, arg0, | |
| 847 ok_for_base_p_nonstrict (arg1, mode, PLUS, REG) | |
| 848 ? 1 : 0, | |
| 849 PLUS, REG, scale); | |
| 850 /* If one operand is known to be a pointer, it must be the | |
| 851 base with the other operand the index. Likewise if the | |
| 852 other operand is a MULT. */ | |
| 853 else if ((code0 == REG && REG_POINTER (arg0)) || code1 == MULT) | |
| 854 { | |
| 855 record_address_regs (mode, arg0, 0, PLUS, code1, scale); | |
| 856 record_address_regs (mode, arg1, 1, PLUS, code0, scale); | |
| 857 } | |
| 858 else if ((code1 == REG && REG_POINTER (arg1)) || code0 == MULT) | |
| 859 { | |
| 860 record_address_regs (mode, arg0, 1, PLUS, code1, scale); | |
| 861 record_address_regs (mode, arg1, 0, PLUS, code0, scale); | |
| 862 } | |
| 863 /* Otherwise, count equal chances that each might be a base or | |
| 864 index register. This case should be rare. */ | |
| 865 else | |
| 866 { | |
| 867 record_address_regs (mode, arg0, 0, PLUS, code1, scale / 2); | |
| 868 record_address_regs (mode, arg0, 1, PLUS, code1, scale / 2); | |
| 869 record_address_regs (mode, arg1, 0, PLUS, code0, scale / 2); | |
| 870 record_address_regs (mode, arg1, 1, PLUS, code0, scale / 2); | |
| 871 } | |
| 872 } | |
| 873 break; | |
| 874 | |
| 875 /* Double the importance of an allocno that is incremented or | |
| 876 decremented, since it would take two extra insns if it ends | |
| 877 up in the wrong place. */ | |
| 878 case POST_MODIFY: | |
| 879 case PRE_MODIFY: | |
| 880 record_address_regs (mode, XEXP (x, 0), 0, code, | |
| 881 GET_CODE (XEXP (XEXP (x, 1), 1)), 2 * scale); | |
| 882 if (REG_P (XEXP (XEXP (x, 1), 1))) | |
| 883 record_address_regs (mode, XEXP (XEXP (x, 1), 1), 1, code, REG, | |
| 884 2 * scale); | |
| 885 break; | |
| 886 | |
| 887 case POST_INC: | |
| 888 case PRE_INC: | |
| 889 case POST_DEC: | |
| 890 case PRE_DEC: | |
| 891 /* Double the importance of an allocno that is incremented or | |
| 892 decremented, since it would take two extra insns if it ends | |
| 893 up in the wrong place. If the operand is a pseudo-register, | |
| 894 show it is being used in an INC_DEC context. */ | |
| 895 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 896 if (REG_P (XEXP (x, 0)) | |
| 897 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
|
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898 in_inc_dec[COST_INDEX (REGNO (XEXP (x, 0)))] = true; |
| 0 | 899 #endif |
| 900 record_address_regs (mode, XEXP (x, 0), 0, code, SCRATCH, 2 * scale); | |
| 901 break; | |
| 902 | |
| 903 case REG: | |
| 904 { | |
| 905 struct costs *pp; | |
|
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906 enum reg_class i; |
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907 int k; |
| 0 | 908 |
| 909 if (REGNO (x) < FIRST_PSEUDO_REGISTER) | |
| 910 break; | |
| 911 | |
|
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912 if (allocno_p) |
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913 ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map[REGNO (x)]) = true; |
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914 pp = COSTS (costs, COST_INDEX (REGNO (x))); |
| 0 | 915 pp->mem_cost += (ira_memory_move_cost[Pmode][rclass][1] * scale) / 2; |
| 916 for (k = 0; k < cost_classes_num; k++) | |
| 917 { | |
| 918 i = cost_classes[k]; | |
| 919 pp->cost[k] | |
|
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920 += (ira_get_may_move_cost (Pmode, i, rclass, true) * scale) / 2; |
| 0 | 921 } |
| 922 } | |
| 923 break; | |
| 924 | |
| 925 default: | |
| 926 { | |
| 927 const char *fmt = GET_RTX_FORMAT (code); | |
| 928 int i; | |
| 929 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
| 930 if (fmt[i] == 'e') | |
| 931 record_address_regs (mode, XEXP (x, i), context, code, SCRATCH, | |
| 932 scale); | |
| 933 } | |
| 934 } | |
| 935 } | |
| 936 | |
| 937 | |
| 938 | |
| 939 /* Calculate the costs of insn operands. */ | |
| 940 static void | |
|
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941 record_operand_costs (rtx insn, enum reg_class *pref) |
| 0 | 942 { |
| 943 const char *constraints[MAX_RECOG_OPERANDS]; | |
| 944 enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
| 945 int i; | |
| 946 | |
| 947 for (i = 0; i < recog_data.n_operands; i++) | |
| 948 { | |
| 949 constraints[i] = recog_data.constraints[i]; | |
| 950 modes[i] = recog_data.operand_mode[i]; | |
| 951 } | |
| 952 | |
| 953 /* If we get here, we are set up to record the costs of all the | |
| 954 operands for this insn. Start by initializing the costs. Then | |
| 955 handle any address registers. Finally record the desired classes | |
| 956 for any allocnos, doing it twice if some pair of operands are | |
| 957 commutative. */ | |
| 958 for (i = 0; i < recog_data.n_operands; i++) | |
| 959 { | |
| 960 memcpy (op_costs[i], init_cost, struct_costs_size); | |
| 961 | |
| 962 if (GET_CODE (recog_data.operand[i]) == SUBREG) | |
| 963 recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]); | |
| 964 | |
| 965 if (MEM_P (recog_data.operand[i])) | |
| 966 record_address_regs (GET_MODE (recog_data.operand[i]), | |
| 967 XEXP (recog_data.operand[i], 0), | |
| 968 0, MEM, SCRATCH, frequency * 2); | |
| 969 else if (constraints[i][0] == 'p' | |
| 970 || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], | |
| 971 constraints[i])) | |
| 972 record_address_regs (VOIDmode, recog_data.operand[i], 0, ADDRESS, | |
| 973 SCRATCH, frequency * 2); | |
| 974 } | |
| 975 | |
| 976 /* Check for commutative in a separate loop so everything will have | |
| 977 been initialized. We must do this even if one operand is a | |
| 978 constant--see addsi3 in m68k.md. */ | |
| 979 for (i = 0; i < (int) recog_data.n_operands - 1; i++) | |
| 980 if (constraints[i][0] == '%') | |
| 981 { | |
| 982 const char *xconstraints[MAX_RECOG_OPERANDS]; | |
| 983 int j; | |
| 984 | |
| 985 /* Handle commutative operands by swapping the constraints. | |
| 986 We assume the modes are the same. */ | |
| 987 for (j = 0; j < recog_data.n_operands; j++) | |
| 988 xconstraints[j] = constraints[j]; | |
| 989 | |
| 990 xconstraints[i] = constraints[i+1]; | |
| 991 xconstraints[i+1] = constraints[i]; | |
| 992 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
| 993 recog_data.operand, modes, | |
|
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994 xconstraints, insn, pref); |
| 0 | 995 } |
| 996 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
| 997 recog_data.operand, modes, | |
|
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998 constraints, insn, pref); |
| 0 | 999 } |
| 1000 | |
| 1001 | |
| 1002 | |
| 1003 /* Process one insn INSN. Scan it and record each time it would save | |
| 1004 code to put a certain allocnos in a certain class. Return the last | |
| 1005 insn processed, so that the scan can be continued from there. */ | |
| 1006 static rtx | |
| 1007 scan_one_insn (rtx insn) | |
| 1008 { | |
| 1009 enum rtx_code pat_code; | |
| 1010 rtx set, note; | |
| 1011 int i, k; | |
| 1012 | |
|
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1013 if (!NONDEBUG_INSN_P (insn)) |
| 0 | 1014 return insn; |
| 1015 | |
| 1016 pat_code = GET_CODE (PATTERN (insn)); | |
| 1017 if (pat_code == USE || pat_code == CLOBBER || pat_code == ASM_INPUT | |
| 1018 || pat_code == ADDR_VEC || pat_code == ADDR_DIFF_VEC) | |
| 1019 return insn; | |
| 1020 | |
| 1021 set = single_set (insn); | |
| 1022 extract_insn (insn); | |
| 1023 | |
| 1024 /* If this insn loads a parameter from its stack slot, then it | |
| 1025 represents a savings, rather than a cost, if the parameter is | |
| 1026 stored in memory. Record this fact. */ | |
| 1027 if (set != 0 && REG_P (SET_DEST (set)) && MEM_P (SET_SRC (set)) | |
| 1028 && (note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != NULL_RTX | |
| 1029 && MEM_P (XEXP (note, 0))) | |
| 1030 { | |
| 1031 enum reg_class cl = GENERAL_REGS; | |
| 1032 rtx reg = SET_DEST (set); | |
|
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1033 int num = COST_INDEX (REGNO (reg)); |
| 0 | 1034 |
|
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1035 if (pref) |
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1036 cl = pref[num]; |
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1037 COSTS (costs, num)->mem_cost |
| 0 | 1038 -= ira_memory_move_cost[GET_MODE (reg)][cl][1] * frequency; |
| 1039 record_address_regs (GET_MODE (SET_SRC (set)), XEXP (SET_SRC (set), 0), | |
| 1040 0, MEM, SCRATCH, frequency * 2); | |
| 1041 } | |
| 1042 | |
|
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1043 record_operand_costs (insn, pref); |
| 0 | 1044 |
| 1045 /* Now add the cost for each operand to the total costs for its | |
| 1046 allocno. */ | |
| 1047 for (i = 0; i < recog_data.n_operands; i++) | |
| 1048 if (REG_P (recog_data.operand[i]) | |
| 1049 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER) | |
| 1050 { | |
| 1051 int regno = REGNO (recog_data.operand[i]); | |
|
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1052 struct costs *p = COSTS (costs, COST_INDEX (regno)); |
| 0 | 1053 struct costs *q = op_costs[i]; |
| 1054 | |
| 1055 p->mem_cost += q->mem_cost; | |
| 1056 for (k = 0; k < cost_classes_num; k++) | |
| 1057 p->cost[k] += q->cost[k]; | |
| 1058 } | |
| 1059 | |
| 1060 return insn; | |
| 1061 } | |
| 1062 | |
| 1063 | |
| 1064 | |
| 1065 /* Print allocnos costs to file F. */ | |
| 1066 static void | |
|
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1067 print_allocno_costs (FILE *f) |
| 0 | 1068 { |
| 1069 int k; | |
| 1070 ira_allocno_t a; | |
| 1071 ira_allocno_iterator ai; | |
| 1072 | |
|
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1073 ira_assert (allocno_p); |
| 0 | 1074 fprintf (f, "\n"); |
| 1075 FOR_EACH_ALLOCNO (a, ai) | |
| 1076 { | |
| 1077 int i, rclass; | |
| 1078 basic_block bb; | |
| 1079 int regno = ALLOCNO_REGNO (a); | |
| 1080 | |
| 1081 i = ALLOCNO_NUM (a); | |
| 1082 fprintf (f, " a%d(r%d,", i, regno); | |
| 1083 if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) | |
| 1084 fprintf (f, "b%d", bb->index); | |
| 1085 else | |
| 1086 fprintf (f, "l%d", ALLOCNO_LOOP_TREE_NODE (a)->loop->num); | |
| 1087 fprintf (f, ") costs:"); | |
| 1088 for (k = 0; k < cost_classes_num; k++) | |
| 1089 { | |
| 1090 rclass = cost_classes[k]; | |
| 1091 if (contains_reg_of_mode[rclass][PSEUDO_REGNO_MODE (regno)] | |
| 1092 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 1093 && (! in_inc_dec[i] || ! forbidden_inc_dec_class[rclass]) | |
| 1094 #endif | |
| 1095 #ifdef CANNOT_CHANGE_MODE_CLASS | |
|
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1096 && ! invalid_mode_change_p (regno, (enum reg_class) rclass) |
| 0 | 1097 #endif |
| 1098 ) | |
| 1099 { | |
| 1100 fprintf (f, " %s:%d", reg_class_names[rclass], | |
|
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1101 COSTS (costs, i)->cost[k]); |
| 0 | 1102 if (flag_ira_region == IRA_REGION_ALL |
| 1103 || flag_ira_region == IRA_REGION_MIXED) | |
|
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1104 fprintf (f, ",%d", COSTS (total_allocno_costs, i)->cost[k]); |
| 0 | 1105 } |
| 1106 } | |
|
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1107 fprintf (f, " MEM:%i\n", COSTS (costs, i)->mem_cost); |
| 0 | 1108 } |
| 1109 } | |
| 1110 | |
|
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1111 /* Print pseudo costs to file F. */ |
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1112 static void |
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1113 print_pseudo_costs (FILE *f) |
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1114 { |
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1115 int regno, k; |
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1116 int rclass; |
|
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1117 |
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1118 ira_assert (! allocno_p); |
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1119 fprintf (f, "\n"); |
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1120 for (regno = max_reg_num () - 1; regno >= FIRST_PSEUDO_REGISTER; regno--) |
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1121 { |
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1122 if (regno_reg_rtx[regno] == NULL_RTX) |
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1123 continue; |
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1124 fprintf (f, " r%d costs:", regno); |
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1125 for (k = 0; k < cost_classes_num; k++) |
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1126 { |
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|
1127 rclass = cost_classes[k]; |
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1128 if (contains_reg_of_mode[rclass][PSEUDO_REGNO_MODE (regno)] |
|
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|
1129 #ifdef FORBIDDEN_INC_DEC_CLASSES |
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1130 && (! in_inc_dec[regno] || ! forbidden_inc_dec_class[rclass]) |
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|
1131 #endif |
|
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|
1132 #ifdef CANNOT_CHANGE_MODE_CLASS |
|
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1133 && ! invalid_mode_change_p (regno, (enum reg_class) rclass) |
|
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1134 #endif |
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|
1135 ) |
|
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|
1136 fprintf (f, " %s:%d", reg_class_names[rclass], |
|
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|
1137 COSTS (costs, regno)->cost[k]); |
|
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|
1138 } |
|
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1139 fprintf (f, " MEM:%i\n", COSTS (costs, regno)->mem_cost); |
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1140 } |
|
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1141 } |
|
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|
1142 |
|
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1143 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno |
|
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|
1144 costs. */ |
|
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|
1145 static void |
|
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|
1146 process_bb_for_costs (basic_block bb) |
|
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|
1147 { |
|
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|
1148 rtx insn; |
|
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|
1149 |
|
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|
1150 frequency = REG_FREQ_FROM_BB (bb); |
|
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|
1151 if (frequency == 0) |
|
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|
1152 frequency = 1; |
|
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|
1153 FOR_BB_INSNS (bb, insn) |
|
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|
1154 insn = scan_one_insn (insn); |
|
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1155 } |
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1156 |
| 0 | 1157 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno |
| 1158 costs. */ | |
| 1159 static void | |
| 1160 process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node) | |
| 1161 { | |
| 1162 basic_block bb; | |
| 1163 | |
| 1164 bb = loop_tree_node->bb; | |
|
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1165 if (bb != NULL) |
|
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1166 process_bb_for_costs (bb); |
| 0 | 1167 } |
| 1168 | |
|
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|
1169 /* Find costs of register classes and memory for allocnos or pseudos |
|
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1170 and their best costs. Set up preferred, alternative and cover |
|
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1171 classes for pseudos. */ |
| 0 | 1172 static void |
|
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1173 find_costs_and_classes (FILE *dump_file) |
| 0 | 1174 { |
|
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|
1175 int i, k, start; |
| 0 | 1176 int pass; |
| 1177 basic_block bb; | |
| 1178 | |
| 1179 init_recog (); | |
| 1180 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
|
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1181 in_inc_dec = ira_allocate (sizeof (bool) * cost_elements_num); |
| 0 | 1182 #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
|
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1183 pref = NULL; |
|
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1184 start = 0; |
|
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1185 if (!resize_reg_info () && allocno_p && pseudo_classes_defined_p) |
|
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1186 { |
|
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1187 ira_allocno_t a; |
|
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1188 ira_allocno_iterator ai; |
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1189 |
|
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1190 pref = pref_buffer; |
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1191 FOR_EACH_ALLOCNO (a, ai) |
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1192 pref[ALLOCNO_NUM (a)] = reg_preferred_class (ALLOCNO_REGNO (a)); |
|
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1193 if (flag_expensive_optimizations) |
|
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1194 start = 1; |
|
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1195 } |
|
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|
1196 if (allocno_p) |
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1197 /* Clear the flag for the next compiled function. */ |
|
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diff
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|
1198 pseudo_classes_defined_p = false; |
| 0 | 1199 /* Normally we scan the insns once and determine the best class to |
| 1200 use for each allocno. However, if -fexpensive-optimizations are | |
| 1201 on, we do so twice, the second time using the tentative best | |
| 1202 classes to guide the selection. */ | |
|
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diff
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|
1203 for (pass = start; pass <= flag_expensive_optimizations; pass++) |
| 0 | 1204 { |
|
55
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diff
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|
1205 if ((!allocno_p || internal_flag_ira_verbose > 0) && dump_file) |
|
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diff
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|
1206 fprintf (dump_file, |
|
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diff
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|
1207 "\nPass %i for finding pseudo/allocno costs\n\n", pass); |
| 0 | 1208 /* We could use only cover classes. Unfortunately it does not |
| 1209 work well for some targets where some subclass of cover class | |
| 1210 is costly and wrong cover class is chosen. */ | |
| 1211 for (i = 0; i < N_REG_CLASSES; i++) | |
| 1212 cost_class_nums[i] = -1; | |
| 1213 for (cost_classes_num = 0; | |
| 1214 cost_classes_num < ira_important_classes_num; | |
| 1215 cost_classes_num++) | |
| 1216 { | |
| 1217 cost_classes[cost_classes_num] | |
| 1218 = ira_important_classes[cost_classes_num]; | |
| 1219 cost_class_nums[cost_classes[cost_classes_num]] | |
| 1220 = cost_classes_num; | |
| 1221 } | |
| 1222 struct_costs_size | |
| 1223 = sizeof (struct costs) + sizeof (int) * (cost_classes_num - 1); | |
| 1224 /* Zero out our accumulation of the cost of each class for each | |
| 1225 allocno. */ | |
|
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diff
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|
1226 memset (costs, 0, cost_elements_num * struct_costs_size); |
| 0 | 1227 #ifdef FORBIDDEN_INC_DEC_CLASSES |
|
55
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diff
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|
1228 memset (in_inc_dec, 0, cost_elements_num * sizeof (bool)); |
| 0 | 1229 #endif |
| 1230 | |
|
55
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diff
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|
1231 if (allocno_p) |
|
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diff
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|
1232 { |
|
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19
diff
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|
1233 /* Scan the instructions and record each time it would save code |
|
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diff
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|
1234 to put a certain allocno in a certain class. */ |
|
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diff
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|
1235 ira_traverse_loop_tree (true, ira_loop_tree_root, |
|
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|
1236 process_bb_node_for_costs, NULL); |
| 0 | 1237 |
|
55
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diff
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|
1238 memcpy (total_allocno_costs, costs, |
|
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|
1239 max_struct_costs_size * ira_allocnos_num); |
|
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|
1240 } |
|
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|
1241 else |
|
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|
1242 { |
|
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diff
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|
1243 basic_block bb; |
|
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|
1244 |
|
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diff
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|
1245 FOR_EACH_BB (bb) |
|
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diff
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|
1246 process_bb_for_costs (bb); |
|
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|
1247 } |
|
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|
1248 |
| 0 | 1249 if (pass == 0) |
|
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|
1250 pref = pref_buffer; |
| 0 | 1251 |
| 1252 /* Now for each allocno look at how desirable each class is and | |
| 1253 find which class is preferred. */ | |
| 1254 for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--) | |
| 1255 { | |
| 1256 ira_allocno_t a, parent_a; | |
| 1257 int rclass, a_num, parent_a_num; | |
| 1258 ira_loop_tree_node_t parent; | |
| 1259 int best_cost, allocno_cost; | |
| 1260 enum reg_class best, alt_class; | |
| 1261 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 1262 int inc_dec_p = false; | |
| 1263 #endif | |
|
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|
1264 int equiv_savings = regno_equiv_gains[i]; |
| 0 | 1265 |
|
55
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|
1266 if (! allocno_p) |
| 0 | 1267 { |
|
55
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|
1268 if (regno_reg_rtx[i] == NULL_RTX) |
|
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|
1269 continue; |
|
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|
1270 #ifdef FORBIDDEN_INC_DEC_CLASSES |
|
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|
1271 inc_dec_p = in_inc_dec[i]; |
|
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1272 #endif |
|
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|
1273 memcpy (temp_costs, COSTS (costs, i), struct_costs_size); |
|
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1274 } |
|
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|
1275 else |
|
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1276 { |
|
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|
1277 if (ira_regno_allocno_map[i] == NULL) |
|
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|
1278 continue; |
|
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diff
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|
1279 memset (temp_costs, 0, struct_costs_size); |
|
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|
1280 /* Find cost of all allocnos with the same regno. */ |
|
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|
1281 for (a = ira_regno_allocno_map[i]; |
|
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diff
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|
1282 a != NULL; |
|
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diff
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1283 a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) |
| 0 | 1284 { |
|
55
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diff
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|
1285 a_num = ALLOCNO_NUM (a); |
|
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diff
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|
1286 if ((flag_ira_region == IRA_REGION_ALL |
|
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diff
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|
1287 || flag_ira_region == IRA_REGION_MIXED) |
|
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diff
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|
1288 && (parent = ALLOCNO_LOOP_TREE_NODE (a)->parent) != NULL |
|
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|
1289 && (parent_a = parent->regno_allocno_map[i]) != NULL |
|
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diff
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|
1290 /* There are no caps yet. */ |
|
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|
1291 && bitmap_bit_p (ALLOCNO_LOOP_TREE_NODE |
|
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diff
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|
1292 (a)->border_allocnos, |
|
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|
1293 ALLOCNO_NUM (a))) |
|
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|
1294 { |
|
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|
1295 /* Propagate costs to upper levels in the region |
|
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|
1296 tree. */ |
|
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|
1297 parent_a_num = ALLOCNO_NUM (parent_a); |
|
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diff
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|
1298 for (k = 0; k < cost_classes_num; k++) |
|
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|
1299 COSTS (total_allocno_costs, parent_a_num)->cost[k] |
|
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|
1300 += COSTS (total_allocno_costs, a_num)->cost[k]; |
|
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|
1301 COSTS (total_allocno_costs, parent_a_num)->mem_cost |
|
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1302 += COSTS (total_allocno_costs, a_num)->mem_cost; |
|
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|
1303 } |
| 0 | 1304 for (k = 0; k < cost_classes_num; k++) |
|
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|
1305 temp_costs->cost[k] += COSTS (costs, a_num)->cost[k]; |
|
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|
1306 temp_costs->mem_cost += COSTS (costs, a_num)->mem_cost; |
|
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|
1307 #ifdef FORBIDDEN_INC_DEC_CLASSES |
|
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|
1308 if (in_inc_dec[a_num]) |
|
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1309 inc_dec_p = true; |
|
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|
1310 #endif |
| 0 | 1311 } |
| 1312 } | |
|
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1313 if (equiv_savings < 0) |
|
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1314 temp_costs->mem_cost = -equiv_savings; |
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1315 else if (equiv_savings > 0) |
|
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1316 { |
|
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1317 temp_costs->mem_cost = 0; |
|
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1318 for (k = 0; k < cost_classes_num; k++) |
|
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1319 temp_costs->cost[k] += equiv_savings; |
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|
1320 } |
|
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1321 |
| 0 | 1322 best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
| 1323 best = ALL_REGS; | |
| 1324 alt_class = NO_REGS; | |
| 1325 /* Find best common class for all allocnos with the same | |
| 1326 regno. */ | |
| 1327 for (k = 0; k < cost_classes_num; k++) | |
| 1328 { | |
| 1329 rclass = cost_classes[k]; | |
| 1330 /* Ignore classes that are too small for this operand or | |
| 1331 invalid for an operand that was auto-incremented. */ | |
| 1332 if (! contains_reg_of_mode[rclass][PSEUDO_REGNO_MODE (i)] | |
| 1333 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 1334 || (inc_dec_p && forbidden_inc_dec_class[rclass]) | |
| 1335 #endif | |
| 1336 #ifdef CANNOT_CHANGE_MODE_CLASS | |
|
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1337 || invalid_mode_change_p (i, (enum reg_class) rclass) |
| 0 | 1338 #endif |
| 1339 ) | |
| 1340 continue; | |
| 1341 if (temp_costs->cost[k] < best_cost) | |
| 1342 { | |
| 1343 best_cost = temp_costs->cost[k]; | |
| 1344 best = (enum reg_class) rclass; | |
| 1345 } | |
| 1346 else if (temp_costs->cost[k] == best_cost) | |
| 1347 best = ira_reg_class_union[best][rclass]; | |
| 1348 if (pass == flag_expensive_optimizations | |
| 1349 && temp_costs->cost[k] < temp_costs->mem_cost | |
| 1350 && (reg_class_size[reg_class_subunion[alt_class][rclass]] | |
| 1351 > reg_class_size[alt_class])) | |
| 1352 alt_class = reg_class_subunion[alt_class][rclass]; | |
| 1353 } | |
| 1354 alt_class = ira_class_translate[alt_class]; | |
|
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1355 if (best_cost > temp_costs->mem_cost) |
|
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1356 regno_cover_class[i] = NO_REGS; |
|
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1357 else if (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY) |
|
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1358 /* Make the common class the biggest class of best and |
|
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1359 alt_class. */ |
|
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1360 regno_cover_class[i] = alt_class == NO_REGS ? best : alt_class; |
|
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1361 else |
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1362 /* Make the common class a cover class. Remember all |
|
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1363 allocnos with the same regno should have the same cover |
|
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1364 class. */ |
|
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1365 regno_cover_class[i] = ira_class_translate[best]; |
| 0 | 1366 if (pass == flag_expensive_optimizations) |
| 1367 { | |
| 1368 if (best_cost > temp_costs->mem_cost) | |
| 1369 best = alt_class = NO_REGS; | |
| 1370 else if (best == alt_class) | |
| 1371 alt_class = NO_REGS; | |
|
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1372 setup_reg_classes (i, best, alt_class, regno_cover_class[i]); |
|
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1373 if ((!allocno_p || internal_flag_ira_verbose > 2) |
|
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1374 && dump_file != NULL) |
|
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1375 fprintf (dump_file, |
|
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1376 " r%d: preferred %s, alternative %s, cover %s\n", |
|
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1377 i, reg_class_names[best], reg_class_names[alt_class], |
|
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1378 reg_class_names[regno_cover_class[i]]); |
| 0 | 1379 } |
|
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1380 if (! allocno_p) |
|
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1381 { |
|
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1382 pref[i] = best_cost > temp_costs->mem_cost ? NO_REGS : best; |
|
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1383 continue; |
|
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1384 } |
| 0 | 1385 for (a = ira_regno_allocno_map[i]; |
| 1386 a != NULL; | |
| 1387 a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) | |
| 1388 { | |
| 1389 a_num = ALLOCNO_NUM (a); | |
|
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|
1390 if (regno_cover_class[i] == NO_REGS) |
| 0 | 1391 best = NO_REGS; |
| 1392 else | |
|
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1393 { |
| 0 | 1394 /* Finding best class which is subset of the common |
| 1395 class. */ | |
| 1396 best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; | |
| 1397 allocno_cost = best_cost; | |
| 1398 best = ALL_REGS; | |
| 1399 for (k = 0; k < cost_classes_num; k++) | |
| 1400 { | |
| 1401 rclass = cost_classes[k]; | |
|
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1402 if (! ira_class_subset_p[rclass][regno_cover_class[i]]) |
| 0 | 1403 continue; |
| 1404 /* Ignore classes that are too small for this | |
| 1405 operand or invalid for an operand that was | |
| 1406 auto-incremented. */ | |
| 1407 if (! contains_reg_of_mode[rclass][PSEUDO_REGNO_MODE (i)] | |
| 1408 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 1409 || (inc_dec_p && forbidden_inc_dec_class[rclass]) | |
| 1410 #endif | |
| 1411 #ifdef CANNOT_CHANGE_MODE_CLASS | |
|
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|
1412 || invalid_mode_change_p (i, (enum reg_class) rclass) |
| 0 | 1413 #endif |
| 1414 ) | |
| 1415 ; | |
|
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1416 else if (COSTS (total_allocno_costs, a_num)->cost[k] |
| 0 | 1417 < best_cost) |
| 1418 { | |
| 1419 best_cost | |
|
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1420 = COSTS (total_allocno_costs, a_num)->cost[k]; |
|
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1421 allocno_cost = COSTS (costs, a_num)->cost[k]; |
| 0 | 1422 best = (enum reg_class) rclass; |
| 1423 } | |
|
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1424 else if (COSTS (total_allocno_costs, a_num)->cost[k] |
| 0 | 1425 == best_cost) |
| 1426 { | |
| 1427 best = ira_reg_class_union[best][rclass]; | |
| 1428 allocno_cost | |
|
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|
1429 = MAX (allocno_cost, COSTS (costs, a_num)->cost[k]); |
| 0 | 1430 } |
| 1431 } | |
| 1432 ALLOCNO_COVER_CLASS_COST (a) = allocno_cost; | |
| 1433 } | |
| 1434 ira_assert (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY | |
|
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1435 || ira_class_translate[best] == regno_cover_class[i]); |
|
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1436 if (internal_flag_ira_verbose > 2 && dump_file != NULL |
|
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1437 && (pass == 0 || pref[a_num] != best)) |
| 0 | 1438 { |
|
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1439 fprintf (dump_file, " a%d (r%d,", a_num, i); |
| 0 | 1440 if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) |
|
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1441 fprintf (dump_file, "b%d", bb->index); |
| 0 | 1442 else |
|
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1443 fprintf (dump_file, "l%d", |
| 0 | 1444 ALLOCNO_LOOP_TREE_NODE (a)->loop->num); |
|
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1445 fprintf (dump_file, ") best %s, cover %s\n", |
| 0 | 1446 reg_class_names[best], |
|
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1447 reg_class_names[regno_cover_class[i]]); |
| 0 | 1448 } |
|
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1449 pref[a_num] = best; |
| 0 | 1450 } |
| 1451 } | |
|
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1452 |
|
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1453 if (internal_flag_ira_verbose > 4 && dump_file) |
| 0 | 1454 { |
|
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1455 if (allocno_p) |
|
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1456 print_allocno_costs (dump_file); |
|
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1457 else |
|
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1458 print_pseudo_costs (dump_file); |
|
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1459 fprintf (dump_file,"\n"); |
| 0 | 1460 } |
| 1461 } | |
| 1462 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 1463 ira_free (in_inc_dec); | |
| 1464 #endif | |
| 1465 } | |
| 1466 | |
| 1467 | |
| 1468 | |
| 1469 /* Process moves involving hard regs to modify allocno hard register | |
| 1470 costs. We can do this only after determining allocno cover class. | |
| 1471 If a hard register forms a register class, than moves with the hard | |
| 1472 register are already taken into account in class costs for the | |
| 1473 allocno. */ | |
| 1474 static void | |
| 1475 process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node) | |
| 1476 { | |
| 1477 int i, freq, cost, src_regno, dst_regno, hard_regno; | |
| 1478 bool to_p; | |
| 1479 ira_allocno_t a; | |
| 1480 enum reg_class rclass, hard_reg_class; | |
| 1481 enum machine_mode mode; | |
| 1482 basic_block bb; | |
| 1483 rtx insn, set, src, dst; | |
| 1484 | |
| 1485 bb = loop_tree_node->bb; | |
| 1486 if (bb == NULL) | |
| 1487 return; | |
| 1488 freq = REG_FREQ_FROM_BB (bb); | |
| 1489 if (freq == 0) | |
| 1490 freq = 1; | |
| 1491 FOR_BB_INSNS (bb, insn) | |
| 1492 { | |
|
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|
1493 if (!NONDEBUG_INSN_P (insn)) |
| 0 | 1494 continue; |
| 1495 set = single_set (insn); | |
| 1496 if (set == NULL_RTX) | |
| 1497 continue; | |
| 1498 dst = SET_DEST (set); | |
| 1499 src = SET_SRC (set); | |
| 1500 if (! REG_P (dst) || ! REG_P (src)) | |
| 1501 continue; | |
| 1502 dst_regno = REGNO (dst); | |
| 1503 src_regno = REGNO (src); | |
| 1504 if (dst_regno >= FIRST_PSEUDO_REGISTER | |
| 1505 && src_regno < FIRST_PSEUDO_REGISTER) | |
| 1506 { | |
| 1507 hard_regno = src_regno; | |
| 1508 to_p = true; | |
| 1509 a = ira_curr_regno_allocno_map[dst_regno]; | |
| 1510 } | |
| 1511 else if (src_regno >= FIRST_PSEUDO_REGISTER | |
| 1512 && dst_regno < FIRST_PSEUDO_REGISTER) | |
| 1513 { | |
| 1514 hard_regno = dst_regno; | |
| 1515 to_p = false; | |
| 1516 a = ira_curr_regno_allocno_map[src_regno]; | |
| 1517 } | |
| 1518 else | |
| 1519 continue; | |
| 1520 rclass = ALLOCNO_COVER_CLASS (a); | |
| 1521 if (! TEST_HARD_REG_BIT (reg_class_contents[rclass], hard_regno)) | |
| 1522 continue; | |
| 1523 i = ira_class_hard_reg_index[rclass][hard_regno]; | |
| 1524 if (i < 0) | |
| 1525 continue; | |
| 1526 mode = ALLOCNO_MODE (a); | |
| 1527 hard_reg_class = REGNO_REG_CLASS (hard_regno); | |
|
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|
1528 cost |
|
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|
1529 = (to_p ? ira_get_register_move_cost (mode, hard_reg_class, rclass) |
|
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1530 : ira_get_register_move_cost (mode, rclass, hard_reg_class)) * freq; |
| 0 | 1531 ira_allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a), rclass, |
| 1532 ALLOCNO_COVER_CLASS_COST (a)); | |
| 1533 ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a), | |
| 1534 rclass, 0); | |
| 1535 ALLOCNO_HARD_REG_COSTS (a)[i] -= cost; | |
| 1536 ALLOCNO_CONFLICT_HARD_REG_COSTS (a)[i] -= cost; | |
| 1537 ALLOCNO_COVER_CLASS_COST (a) = MIN (ALLOCNO_COVER_CLASS_COST (a), | |
| 1538 ALLOCNO_HARD_REG_COSTS (a)[i]); | |
| 1539 } | |
| 1540 } | |
| 1541 | |
| 1542 /* After we find hard register and memory costs for allocnos, define | |
| 1543 its cover class and modify hard register cost because insns moving | |
| 1544 allocno to/from hard registers. */ | |
| 1545 static void | |
| 1546 setup_allocno_cover_class_and_costs (void) | |
| 1547 { | |
| 1548 int i, j, n, regno, num; | |
| 1549 int *reg_costs; | |
| 1550 enum reg_class cover_class, rclass; | |
| 1551 ira_allocno_t a; | |
| 1552 ira_allocno_iterator ai; | |
| 1553 | |
|
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1554 ira_assert (allocno_p); |
| 0 | 1555 FOR_EACH_ALLOCNO (a, ai) |
| 1556 { | |
| 1557 i = ALLOCNO_NUM (a); | |
|
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1558 cover_class = regno_cover_class[ALLOCNO_REGNO (a)]; |
|
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1559 ira_assert (pref[i] == NO_REGS || cover_class != NO_REGS); |
|
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1560 ALLOCNO_MEMORY_COST (a) = COSTS (costs, i)->mem_cost; |
| 0 | 1561 ira_set_allocno_cover_class (a, cover_class); |
| 1562 if (cover_class == NO_REGS) | |
| 1563 continue; | |
| 1564 ALLOCNO_AVAILABLE_REGS_NUM (a) = ira_available_class_regs[cover_class]; | |
|
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1565 if (optimize && ALLOCNO_COVER_CLASS (a) != pref[i]) |
| 0 | 1566 { |
| 1567 n = ira_class_hard_regs_num[cover_class]; | |
| 1568 ALLOCNO_HARD_REG_COSTS (a) | |
| 1569 = reg_costs = ira_allocate_cost_vector (cover_class); | |
| 1570 for (j = n - 1; j >= 0; j--) | |
| 1571 { | |
| 1572 regno = ira_class_hard_regs[cover_class][j]; | |
|
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1573 if (TEST_HARD_REG_BIT (reg_class_contents[pref[i]], regno)) |
| 0 | 1574 reg_costs[j] = ALLOCNO_COVER_CLASS_COST (a); |
| 1575 else | |
| 1576 { | |
| 1577 rclass = REGNO_REG_CLASS (regno); | |
| 1578 num = cost_class_nums[rclass]; | |
| 1579 if (num < 0) | |
| 1580 { | |
| 1581 /* The hard register class is not a cover class or a | |
| 1582 class not fully inside in a cover class -- use | |
| 1583 the allocno cover class. */ | |
| 1584 ira_assert (ira_hard_regno_cover_class[regno] | |
| 1585 == cover_class); | |
| 1586 num = cost_class_nums[cover_class]; | |
| 1587 } | |
|
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1588 reg_costs[j] = COSTS (costs, i)->cost[num]; |
| 0 | 1589 } |
| 1590 } | |
| 1591 } | |
| 1592 } | |
| 1593 if (optimize) | |
| 1594 ira_traverse_loop_tree (true, ira_loop_tree_root, | |
| 1595 process_bb_node_for_hard_reg_moves, NULL); | |
| 1596 } | |
| 1597 | |
| 1598 | |
| 1599 | |
| 1600 /* Function called once during compiler work. */ | |
| 1601 void | |
| 1602 ira_init_costs_once (void) | |
| 1603 { | |
| 1604 int i; | |
| 1605 | |
| 1606 init_cost = NULL; | |
| 1607 for (i = 0; i < MAX_RECOG_OPERANDS; i++) | |
| 1608 { | |
| 1609 op_costs[i] = NULL; | |
| 1610 this_op_costs[i] = NULL; | |
| 1611 } | |
| 1612 temp_costs = NULL; | |
| 1613 cost_classes = NULL; | |
| 1614 } | |
| 1615 | |
| 1616 /* Free allocated temporary cost vectors. */ | |
| 1617 static void | |
| 1618 free_ira_costs (void) | |
| 1619 { | |
| 1620 int i; | |
| 1621 | |
| 1622 if (init_cost != NULL) | |
| 1623 free (init_cost); | |
| 1624 init_cost = NULL; | |
| 1625 for (i = 0; i < MAX_RECOG_OPERANDS; i++) | |
| 1626 { | |
| 1627 if (op_costs[i] != NULL) | |
| 1628 free (op_costs[i]); | |
| 1629 if (this_op_costs[i] != NULL) | |
| 1630 free (this_op_costs[i]); | |
| 1631 op_costs[i] = this_op_costs[i] = NULL; | |
| 1632 } | |
| 1633 if (temp_costs != NULL) | |
| 1634 free (temp_costs); | |
| 1635 temp_costs = NULL; | |
| 1636 if (cost_classes != NULL) | |
| 1637 free (cost_classes); | |
| 1638 cost_classes = NULL; | |
| 1639 } | |
| 1640 | |
| 1641 /* This is called each time register related information is | |
| 1642 changed. */ | |
| 1643 void | |
| 1644 ira_init_costs (void) | |
| 1645 { | |
| 1646 int i; | |
| 1647 | |
| 1648 free_ira_costs (); | |
| 1649 max_struct_costs_size | |
| 1650 = sizeof (struct costs) + sizeof (int) * (ira_important_classes_num - 1); | |
| 1651 /* Don't use ira_allocate because vectors live through several IRA calls. */ | |
| 1652 init_cost = (struct costs *) xmalloc (max_struct_costs_size); | |
| 1653 init_cost->mem_cost = 1000000; | |
| 1654 for (i = 0; i < ira_important_classes_num; i++) | |
| 1655 init_cost->cost[i] = 1000000; | |
| 1656 for (i = 0; i < MAX_RECOG_OPERANDS; i++) | |
| 1657 { | |
| 1658 op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size); | |
| 1659 this_op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size); | |
| 1660 } | |
| 1661 temp_costs = (struct costs *) xmalloc (max_struct_costs_size); | |
| 1662 cost_classes = (enum reg_class *) xmalloc (sizeof (enum reg_class) | |
| 1663 * ira_important_classes_num); | |
| 1664 } | |
| 1665 | |
| 1666 /* Function called once at the end of compiler work. */ | |
| 1667 void | |
| 1668 ira_finish_costs_once (void) | |
| 1669 { | |
| 1670 free_ira_costs (); | |
| 1671 } | |
| 1672 | |
| 1673 | |
| 1674 | |
|
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1675 /* Common initialization function for ira_costs and |
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1676 ira_set_pseudo_classes. */ |
|
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1677 static void |
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1678 init_costs (void) |
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1679 { |
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1680 init_subregs_of_mode (); |
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1681 costs = (struct costs *) ira_allocate (max_struct_costs_size |
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1682 * cost_elements_num); |
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1683 pref_buffer |
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1684 = (enum reg_class *) ira_allocate (sizeof (enum reg_class) |
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1685 * cost_elements_num); |
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1686 regno_cover_class |
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1687 = (enum reg_class *) ira_allocate (sizeof (enum reg_class) |
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1688 * max_reg_num ()); |
|
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1689 regno_equiv_gains = (int *) ira_allocate (sizeof (int) * max_reg_num ()); |
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1690 memset (regno_equiv_gains, 0, sizeof (int) * max_reg_num ()); |
|
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1691 } |
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1692 |
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1693 /* Common finalization function for ira_costs and |
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1694 ira_set_pseudo_classes. */ |
|
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1695 static void |
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1696 finish_costs (void) |
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1697 { |
|
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1698 finish_subregs_of_mode (); |
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1699 ira_free (regno_equiv_gains); |
|
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1700 ira_free (regno_cover_class); |
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1701 ira_free (pref_buffer); |
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1702 ira_free (costs); |
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1703 } |
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1704 |
| 0 | 1705 /* Entry function which defines cover class, memory and hard register |
| 1706 costs for each allocno. */ | |
| 1707 void | |
| 1708 ira_costs (void) | |
| 1709 { | |
|
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1710 allocno_p = true; |
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1711 cost_elements_num = ira_allocnos_num; |
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1712 init_costs (); |
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1713 total_allocno_costs = (struct costs *) ira_allocate (max_struct_costs_size |
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1714 * ira_allocnos_num); |
|
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1715 calculate_elim_costs_all_insns (); |
|
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1716 find_costs_and_classes (ira_dump_file); |
| 0 | 1717 setup_allocno_cover_class_and_costs (); |
|
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1718 finish_costs (); |
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1719 ira_free (total_allocno_costs); |
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1720 } |
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1721 |
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1722 /* Entry function which defines classes for pseudos. */ |
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1723 void |
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1724 ira_set_pseudo_classes (FILE *dump_file) |
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1725 { |
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1726 allocno_p = false; |
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1727 internal_flag_ira_verbose = flag_ira_verbose; |
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1728 cost_elements_num = max_reg_num (); |
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1729 init_costs (); |
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1730 find_costs_and_classes (dump_file); |
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1731 pseudo_classes_defined_p = true; |
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1732 finish_costs (); |
| 0 | 1733 } |
| 1734 | |
| 1735 | |
| 1736 | |
| 1737 /* Change hard register costs for allocnos which lives through | |
| 1738 function calls. This is called only when we found all intersected | |
| 1739 calls during building allocno live ranges. */ | |
| 1740 void | |
| 1741 ira_tune_allocno_costs_and_cover_classes (void) | |
| 1742 { | |
| 1743 int j, n, regno; | |
| 1744 int cost, min_cost, *reg_costs; | |
| 1745 enum reg_class cover_class, rclass; | |
| 1746 enum machine_mode mode; | |
| 1747 ira_allocno_t a; | |
| 1748 ira_allocno_iterator ai; | |
| 1749 | |
| 1750 FOR_EACH_ALLOCNO (a, ai) | |
| 1751 { | |
| 1752 cover_class = ALLOCNO_COVER_CLASS (a); | |
| 1753 if (cover_class == NO_REGS) | |
| 1754 continue; | |
| 1755 mode = ALLOCNO_MODE (a); | |
| 1756 n = ira_class_hard_regs_num[cover_class]; | |
| 1757 min_cost = INT_MAX; | |
| 1758 if (ALLOCNO_CALLS_CROSSED_NUM (a) != 0) | |
| 1759 { | |
| 1760 ira_allocate_and_set_costs | |
| 1761 (&ALLOCNO_HARD_REG_COSTS (a), cover_class, | |
| 1762 ALLOCNO_COVER_CLASS_COST (a)); | |
| 1763 reg_costs = ALLOCNO_HARD_REG_COSTS (a); | |
| 1764 for (j = n - 1; j >= 0; j--) | |
| 1765 { | |
| 1766 regno = ira_class_hard_regs[cover_class][j]; | |
| 1767 rclass = REGNO_REG_CLASS (regno); | |
| 1768 cost = 0; | |
| 1769 if (! ira_hard_reg_not_in_set_p (regno, mode, call_used_reg_set) | |
| 1770 || HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)) | |
| 1771 cost += (ALLOCNO_CALL_FREQ (a) | |
| 1772 * (ira_memory_move_cost[mode][rclass][0] | |
| 1773 + ira_memory_move_cost[mode][rclass][1])); | |
| 1774 #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER | |
| 1775 cost += ((ira_memory_move_cost[mode][rclass][0] | |
| 1776 + ira_memory_move_cost[mode][rclass][1]) | |
| 1777 * ALLOCNO_FREQ (a) | |
| 1778 * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno) / 2); | |
| 1779 #endif | |
| 1780 reg_costs[j] += cost; | |
| 1781 if (min_cost > reg_costs[j]) | |
| 1782 min_cost = reg_costs[j]; | |
| 1783 } | |
| 1784 } | |
| 1785 if (min_cost != INT_MAX) | |
| 1786 ALLOCNO_COVER_CLASS_COST (a) = min_cost; | |
|
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1787 |
|
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1788 /* Some targets allow pseudos to be allocated to unaligned sequences |
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1789 of hard registers. However, selecting an unaligned sequence can |
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1790 unnecessarily restrict later allocations. So increase the cost of |
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1791 unaligned hard regs to encourage the use of aligned hard regs. */ |
|
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1792 { |
|
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1793 const int nregs = ira_reg_class_nregs[cover_class][ALLOCNO_MODE (a)]; |
|
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1794 |
|
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1795 if (nregs > 1) |
|
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1796 { |
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1797 ira_allocate_and_set_costs |
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1798 (&ALLOCNO_HARD_REG_COSTS (a), cover_class, |
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1799 ALLOCNO_COVER_CLASS_COST (a)); |
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1800 reg_costs = ALLOCNO_HARD_REG_COSTS (a); |
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1801 for (j = n - 1; j >= 0; j--) |
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1802 { |
|
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1803 regno = ira_non_ordered_class_hard_regs[cover_class][j]; |
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1804 if ((regno % nregs) != 0) |
|
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1805 { |
|
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1806 int index = ira_class_hard_reg_index[cover_class][regno]; |
|
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1807 ira_assert (index != -1); |
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1808 reg_costs[index] += ALLOCNO_FREQ (a); |
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1809 } |
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1810 } |
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1811 } |
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1812 } |
| 0 | 1813 } |
| 1814 } | |
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1815 |
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1816 /* Add COST to the estimated gain for eliminating REGNO with its |
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1817 equivalence. If COST is zero, record that no such elimination is |
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1818 possible. */ |
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1819 |
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1820 void |
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1821 ira_adjust_equiv_reg_cost (unsigned regno, int cost) |
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1822 { |
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1823 if (cost == 0) |
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1824 regno_equiv_gains[regno] = 0; |
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1825 else |
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1826 regno_equiv_gains[regno] += cost; |
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1827 } |