|
111
|
1 ;; Machine description for AArch64 architecture.
|
|
131
|
2 ;; Copyright (C) 2009-2018 Free Software Foundation, Inc.
|
|
111
|
3 ;; Contributed by ARM Ltd.
|
|
|
4 ;;
|
|
|
5 ;; This file is part of GCC.
|
|
|
6 ;;
|
|
|
7 ;; GCC is free software; you can redistribute it and/or modify it
|
|
|
8 ;; under the terms of the GNU General Public License as published by
|
|
|
9 ;; the Free Software Foundation; either version 3, or (at your option)
|
|
|
10 ;; any later version.
|
|
|
11 ;;
|
|
|
12 ;; GCC is distributed in the hope that it will be useful, but
|
|
|
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
|
15 ;; General Public License for more details.
|
|
|
16 ;;
|
|
|
17 ;; You should have received a copy of the GNU General Public License
|
|
|
18 ;; along with GCC; see the file COPYING3. If not see
|
|
|
19 ;; <http://www.gnu.org/licenses/>.
|
|
|
20
|
|
|
21 (define_register_constraint "k" "STACK_REG"
|
|
|
22 "@internal The stack register.")
|
|
|
23
|
|
131
|
24 (define_register_constraint "Ucs" "TAILCALL_ADDR_REGS"
|
|
|
25 "@internal Registers suitable for an indirect tail call")
|
|
111
|
26
|
|
|
27 (define_register_constraint "w" "FP_REGS"
|
|
|
28 "Floating point and SIMD vector registers.")
|
|
|
29
|
|
131
|
30 (define_register_constraint "Upa" "PR_REGS"
|
|
|
31 "SVE predicate registers p0 - p15.")
|
|
|
32
|
|
|
33 (define_register_constraint "Upl" "PR_LO_REGS"
|
|
|
34 "SVE predicate registers p0 - p7.")
|
|
|
35
|
|
111
|
36 (define_register_constraint "x" "FP_LO_REGS"
|
|
|
37 "Floating point and SIMD vector registers V0 - V15.")
|
|
|
38
|
|
|
39 (define_constraint "I"
|
|
|
40 "A constant that can be used with an ADD operation."
|
|
|
41 (and (match_code "const_int")
|
|
|
42 (match_test "aarch64_uimm12_shift (ival)")))
|
|
|
43
|
|
131
|
44 (define_constraint "Uaa"
|
|
111
|
45 "@internal A constant that matches two uses of add instructions."
|
|
|
46 (and (match_code "const_int")
|
|
|
47 (match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)")))
|
|
|
48
|
|
131
|
49 (define_constraint "Uav"
|
|
|
50 "@internal
|
|
|
51 A constraint that matches a VG-based constant that can be added by
|
|
|
52 a single ADDVL or ADDPL."
|
|
|
53 (match_operand 0 "aarch64_sve_addvl_addpl_immediate"))
|
|
|
54
|
|
|
55 (define_constraint "Uat"
|
|
|
56 "@internal
|
|
|
57 A constraint that matches a VG-based constant that can be added by
|
|
|
58 using multiple instructions, with one temporary register."
|
|
|
59 (match_operand 0 "aarch64_split_add_offset_immediate"))
|
|
|
60
|
|
111
|
61 (define_constraint "J"
|
|
|
62 "A constant that can be used with a SUB operation (once negated)."
|
|
|
63 (and (match_code "const_int")
|
|
|
64 (match_test "aarch64_uimm12_shift (-ival)")))
|
|
|
65
|
|
|
66 ;; We can't use the mode of a CONST_INT to determine the context in
|
|
|
67 ;; which it is being used, so we must have a separate constraint for
|
|
|
68 ;; each context.
|
|
|
69
|
|
|
70 (define_constraint "K"
|
|
|
71 "A constant that can be used with a 32-bit logical operation."
|
|
|
72 (and (match_code "const_int")
|
|
|
73 (match_test "aarch64_bitmask_imm (ival, SImode)")))
|
|
|
74
|
|
|
75 (define_constraint "L"
|
|
|
76 "A constant that can be used with a 64-bit logical operation."
|
|
|
77 (and (match_code "const_int")
|
|
|
78 (match_test "aarch64_bitmask_imm (ival, DImode)")))
|
|
|
79
|
|
|
80 (define_constraint "M"
|
|
|
81 "A constant that can be used with a 32-bit MOV immediate operation."
|
|
|
82 (and (match_code "const_int")
|
|
|
83 (match_test "aarch64_move_imm (ival, SImode)")))
|
|
|
84
|
|
|
85 (define_constraint "N"
|
|
|
86 "A constant that can be used with a 64-bit MOV immediate operation."
|
|
|
87 (and (match_code "const_int")
|
|
|
88 (match_test "aarch64_move_imm (ival, DImode)")))
|
|
|
89
|
|
131
|
90 (define_constraint "Uti"
|
|
|
91 "A constant that can be used with a 128-bit MOV immediate operation."
|
|
|
92 (and (ior (match_code "const_int")
|
|
|
93 (match_code "const_wide_int"))
|
|
|
94 (match_test "aarch64_mov128_immediate (op)")))
|
|
|
95
|
|
111
|
96 (define_constraint "UsO"
|
|
|
97 "A constant that can be used with a 32-bit and operation."
|
|
|
98 (and (match_code "const_int")
|
|
|
99 (match_test "aarch64_and_bitmask_imm (ival, SImode)")))
|
|
|
100
|
|
|
101 (define_constraint "UsP"
|
|
|
102 "A constant that can be used with a 64-bit and operation."
|
|
|
103 (and (match_code "const_int")
|
|
|
104 (match_test "aarch64_and_bitmask_imm (ival, DImode)")))
|
|
|
105
|
|
|
106 (define_constraint "S"
|
|
|
107 "A constraint that matches an absolute symbolic address."
|
|
|
108 (and (match_code "const,symbol_ref,label_ref")
|
|
|
109 (match_test "aarch64_symbolic_address_p (op)")))
|
|
|
110
|
|
|
111 (define_constraint "Y"
|
|
|
112 "Floating point constant zero."
|
|
|
113 (and (match_code "const_double")
|
|
|
114 (match_test "aarch64_float_const_zero_rtx_p (op)")))
|
|
|
115
|
|
|
116 (define_constraint "Z"
|
|
|
117 "Integer constant zero."
|
|
|
118 (match_test "op == const0_rtx"))
|
|
|
119
|
|
|
120 (define_constraint "Ush"
|
|
|
121 "A constraint that matches an absolute symbolic address high part."
|
|
|
122 (and (match_code "high")
|
|
|
123 (match_test "aarch64_valid_symref (XEXP (op, 0), GET_MODE (XEXP (op, 0)))")))
|
|
|
124
|
|
|
125 (define_constraint "Usa"
|
|
|
126 "@internal
|
|
|
127 A constraint that matches an absolute symbolic address that can be
|
|
|
128 loaded by a single ADR."
|
|
|
129 (and (match_code "const,symbol_ref,label_ref")
|
|
|
130 (match_test "aarch64_symbolic_address_p (op)")
|
|
|
131 (match_test "aarch64_mov_operand_p (op, GET_MODE (op))")))
|
|
|
132
|
|
|
133 (define_constraint "Uss"
|
|
|
134 "@internal
|
|
|
135 A constraint that matches an immediate shift constant in SImode."
|
|
|
136 (and (match_code "const_int")
|
|
|
137 (match_test "(unsigned HOST_WIDE_INT) ival < 32")))
|
|
|
138
|
|
|
139 (define_constraint "Usn"
|
|
|
140 "A constant that can be used with a CCMN operation (once negated)."
|
|
|
141 (and (match_code "const_int")
|
|
|
142 (match_test "IN_RANGE (ival, -31, 0)")))
|
|
|
143
|
|
|
144 (define_constraint "Usd"
|
|
|
145 "@internal
|
|
|
146 A constraint that matches an immediate shift constant in DImode."
|
|
|
147 (and (match_code "const_int")
|
|
|
148 (match_test "(unsigned HOST_WIDE_INT) ival < 64")))
|
|
|
149
|
|
|
150 (define_constraint "Usf"
|
|
|
151 "@internal Usf is a symbol reference under the context where plt stub allowed."
|
|
|
152 (and (match_code "symbol_ref")
|
|
|
153 (match_test "!(aarch64_is_noplt_call_p (op)
|
|
|
154 || aarch64_is_long_call_p (op))")))
|
|
|
155
|
|
131
|
156 (define_constraint "Usg"
|
|
|
157 "@internal
|
|
|
158 A constraint that matches an immediate right shift constant in SImode
|
|
|
159 suitable for a SISD instruction."
|
|
|
160 (and (match_code "const_int")
|
|
|
161 (match_test "IN_RANGE (ival, 1, 31)")))
|
|
|
162
|
|
|
163 (define_constraint "Usj"
|
|
|
164 "@internal
|
|
|
165 A constraint that matches an immediate right shift constant in DImode
|
|
|
166 suitable for a SISD instruction."
|
|
|
167 (and (match_code "const_int")
|
|
|
168 (match_test "IN_RANGE (ival, 1, 63)")))
|
|
|
169
|
|
111
|
170 (define_constraint "UsM"
|
|
|
171 "@internal
|
|
|
172 A constraint that matches the immediate constant -1."
|
|
|
173 (match_test "op == constm1_rtx"))
|
|
|
174
|
|
131
|
175 (define_constraint "Ulc"
|
|
|
176 "@internal
|
|
|
177 A constraint that matches a constant integer whose bits are consecutive ones
|
|
|
178 from the MSB."
|
|
|
179 (and (match_code "const_int")
|
|
|
180 (match_test "aarch64_high_bits_all_ones_p (ival)")))
|
|
|
181
|
|
|
182 (define_constraint "Usv"
|
|
|
183 "@internal
|
|
|
184 A constraint that matches a VG-based constant that can be loaded by
|
|
|
185 a single CNT[BHWD]."
|
|
|
186 (match_operand 0 "aarch64_sve_cnt_immediate"))
|
|
|
187
|
|
|
188 (define_constraint "Usi"
|
|
|
189 "@internal
|
|
|
190 A constraint that matches an immediate operand valid for
|
|
|
191 the SVE INDEX instruction."
|
|
|
192 (match_operand 0 "aarch64_sve_index_immediate"))
|
|
|
193
|
|
111
|
194 (define_constraint "Ui1"
|
|
|
195 "@internal
|
|
|
196 A constraint that matches the immediate constant +1."
|
|
|
197 (match_test "op == const1_rtx"))
|
|
|
198
|
|
131
|
199 (define_constraint "Ui2"
|
|
|
200 "@internal
|
|
|
201 A constraint that matches the integers 0...3."
|
|
|
202 (and (match_code "const_int")
|
|
|
203 (match_test "(unsigned HOST_WIDE_INT) ival <= 3")))
|
|
|
204
|
|
111
|
205 (define_constraint "Ui3"
|
|
|
206 "@internal
|
|
|
207 A constraint that matches the integers 0...4."
|
|
|
208 (and (match_code "const_int")
|
|
|
209 (match_test "(unsigned HOST_WIDE_INT) ival <= 4")))
|
|
|
210
|
|
131
|
211 (define_constraint "Ui7"
|
|
|
212 "@internal
|
|
|
213 A constraint that matches the integers 0...7."
|
|
|
214 (and (match_code "const_int")
|
|
|
215 (match_test "(unsigned HOST_WIDE_INT) ival <= 7")))
|
|
|
216
|
|
111
|
217 (define_constraint "Up3"
|
|
|
218 "@internal
|
|
|
219 A constraint that matches the integers 2^(0...4)."
|
|
|
220 (and (match_code "const_int")
|
|
|
221 (match_test "(unsigned) exact_log2 (ival) <= 4")))
|
|
|
222
|
|
|
223 (define_memory_constraint "Q"
|
|
|
224 "A memory address which uses a single base register with no offset."
|
|
|
225 (and (match_code "mem")
|
|
|
226 (match_test "REG_P (XEXP (op, 0))")))
|
|
|
227
|
|
131
|
228 (define_memory_constraint "Ust"
|
|
111
|
229 "@internal
|
|
131
|
230 A memory address with 9bit unscaled offset."
|
|
|
231 (match_operand 0 "aarch64_9bit_offset_memory_operand"))
|
|
111
|
232
|
|
|
233 (define_memory_constraint "Ump"
|
|
|
234 "@internal
|
|
|
235 A memory address suitable for a load/store pair operation."
|
|
|
236 (and (match_code "mem")
|
|
|
237 (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
|
|
131
|
238 true, ADDR_QUERY_LDP_STP)")))
|
|
|
239
|
|
|
240 ;; Used for storing or loading pairs in an AdvSIMD register using an STP/LDP
|
|
|
241 ;; as a vector-concat. The address mode uses the same constraints as if it
|
|
|
242 ;; were for a single value.
|
|
|
243 (define_memory_constraint "Umn"
|
|
|
244 "@internal
|
|
|
245 A memory address suitable for a load/store pair operation."
|
|
|
246 (and (match_code "mem")
|
|
|
247 (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
|
|
|
248 true,
|
|
|
249 ADDR_QUERY_LDP_STP_N)")))
|
|
|
250
|
|
|
251 (define_memory_constraint "Utr"
|
|
|
252 "@internal
|
|
|
253 An address valid for SVE LDR and STR instructions (as distinct from
|
|
|
254 LD[1234] and ST[1234] patterns)."
|
|
|
255 (and (match_code "mem")
|
|
|
256 (match_test "aarch64_sve_ldr_operand_p (op)")))
|
|
111
|
257
|
|
|
258 (define_memory_constraint "Utv"
|
|
|
259 "@internal
|
|
|
260 An address valid for loading/storing opaque structure
|
|
|
261 types wider than TImode."
|
|
|
262 (and (match_code "mem")
|
|
|
263 (match_test "aarch64_simd_mem_operand_p (op)")))
|
|
|
264
|
|
131
|
265 (define_memory_constraint "Utq"
|
|
|
266 "@internal
|
|
|
267 An address valid for loading or storing a 128-bit AdvSIMD register"
|
|
|
268 (and (match_code "mem")
|
|
|
269 (match_test "aarch64_legitimate_address_p (V2DImode,
|
|
|
270 XEXP (op, 0), 1)")))
|
|
|
271
|
|
|
272 (define_memory_constraint "Uty"
|
|
|
273 "@internal
|
|
|
274 An address valid for SVE LD1Rs."
|
|
|
275 (and (match_code "mem")
|
|
|
276 (match_test "aarch64_sve_ld1r_operand_p (op)")))
|
|
|
277
|
|
|
278 (define_memory_constraint "Utx"
|
|
|
279 "@internal
|
|
|
280 An address valid for SVE structure mov patterns (as distinct from
|
|
|
281 LD[234] and ST[234] patterns)."
|
|
|
282 (match_operand 0 "aarch64_sve_struct_memory_operand"))
|
|
|
283
|
|
111
|
284 (define_constraint "Ufc"
|
|
|
285 "A floating point constant which can be used with an\
|
|
|
286 FMOV immediate operation."
|
|
|
287 (and (match_code "const_double")
|
|
|
288 (match_test "aarch64_float_const_representable_p (op)")))
|
|
|
289
|
|
|
290 (define_constraint "Uvi"
|
|
|
291 "A floating point constant which can be used with a\
|
|
|
292 MOVI immediate operation."
|
|
|
293 (and (match_code "const_double")
|
|
|
294 (match_test "aarch64_can_const_movi_rtx_p (op, GET_MODE (op))")))
|
|
|
295
|
|
|
296 (define_constraint "Do"
|
|
|
297 "@internal
|
|
|
298 A constraint that matches vector of immediates for orr."
|
|
|
299 (and (match_code "const_vector")
|
|
131
|
300 (match_test "aarch64_simd_valid_immediate (op, NULL,
|
|
|
301 AARCH64_CHECK_ORR)")))
|
|
111
|
302
|
|
|
303 (define_constraint "Db"
|
|
|
304 "@internal
|
|
|
305 A constraint that matches vector of immediates for bic."
|
|
|
306 (and (match_code "const_vector")
|
|
131
|
307 (match_test "aarch64_simd_valid_immediate (op, NULL,
|
|
|
308 AARCH64_CHECK_BIC)")))
|
|
111
|
309
|
|
|
310 (define_constraint "Dn"
|
|
|
311 "@internal
|
|
|
312 A constraint that matches vector of immediates."
|
|
131
|
313 (and (match_code "const,const_vector")
|
|
|
314 (match_test "aarch64_simd_valid_immediate (op, NULL)")))
|
|
111
|
315
|
|
|
316 (define_constraint "Dh"
|
|
|
317 "@internal
|
|
|
318 A constraint that matches an immediate operand valid for\
|
|
|
319 AdvSIMD scalar move in HImode."
|
|
|
320 (and (match_code "const_int")
|
|
|
321 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
|
|
|
322 HImode)")))
|
|
|
323
|
|
|
324 (define_constraint "Dq"
|
|
|
325 "@internal
|
|
|
326 A constraint that matches an immediate operand valid for\
|
|
|
327 AdvSIMD scalar move in QImode."
|
|
|
328 (and (match_code "const_int")
|
|
|
329 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
|
|
|
330 QImode)")))
|
|
|
331
|
|
|
332 (define_constraint "Dl"
|
|
|
333 "@internal
|
|
|
334 A constraint that matches vector of immediates for left shifts."
|
|
131
|
335 (and (match_code "const,const_vector")
|
|
111
|
336 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
|
|
|
337 true)")))
|
|
|
338
|
|
|
339 (define_constraint "Dr"
|
|
|
340 "@internal
|
|
|
341 A constraint that matches vector of immediates for right shifts."
|
|
131
|
342 (and (match_code "const,const_vector")
|
|
111
|
343 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
|
|
|
344 false)")))
|
|
|
345 (define_constraint "Dz"
|
|
|
346 "@internal
|
|
131
|
347 A constraint that matches a vector of immediate zero."
|
|
|
348 (and (match_code "const,const_vector")
|
|
|
349 (match_test "op == CONST0_RTX (GET_MODE (op))")))
|
|
|
350
|
|
|
351 (define_constraint "Dm"
|
|
|
352 "@internal
|
|
|
353 A constraint that matches a vector of immediate minus one."
|
|
|
354 (and (match_code "const,const_vector")
|
|
|
355 (match_test "op == CONST1_RTX (GET_MODE (op))")))
|
|
111
|
356
|
|
|
357 (define_constraint "Dd"
|
|
|
358 "@internal
|
|
|
359 A constraint that matches an integer immediate operand valid\
|
|
|
360 for AdvSIMD scalar operations in DImode."
|
|
|
361 (and (match_code "const_int")
|
|
|
362 (match_test "aarch64_can_const_movi_rtx_p (op, DImode)")))
|
|
|
363
|
|
|
364 (define_constraint "Ds"
|
|
|
365 "@internal
|
|
|
366 A constraint that matches an integer immediate operand valid\
|
|
|
367 for AdvSIMD scalar operations in SImode."
|
|
|
368 (and (match_code "const_int")
|
|
|
369 (match_test "aarch64_can_const_movi_rtx_p (op, SImode)")))
|
|
|
370
|
|
|
371 (define_address_constraint "Dp"
|
|
|
372 "@internal
|
|
|
373 An address valid for a prefetch instruction."
|
|
|
374 (match_test "aarch64_address_valid_for_prefetch_p (op, true)"))
|
|
131
|
375
|
|
|
376 (define_constraint "vsa"
|
|
|
377 "@internal
|
|
|
378 A constraint that matches an immediate operand valid for SVE
|
|
|
379 arithmetic instructions."
|
|
|
380 (match_operand 0 "aarch64_sve_arith_immediate"))
|
|
|
381
|
|
|
382 (define_constraint "vsc"
|
|
|
383 "@internal
|
|
|
384 A constraint that matches a signed immediate operand valid for SVE
|
|
|
385 CMP instructions."
|
|
|
386 (match_operand 0 "aarch64_sve_cmp_vsc_immediate"))
|
|
|
387
|
|
|
388 (define_constraint "vsd"
|
|
|
389 "@internal
|
|
|
390 A constraint that matches an unsigned immediate operand valid for SVE
|
|
|
391 CMP instructions."
|
|
|
392 (match_operand 0 "aarch64_sve_cmp_vsd_immediate"))
|
|
|
393
|
|
|
394 (define_constraint "vsi"
|
|
|
395 "@internal
|
|
|
396 A constraint that matches a vector count operand valid for SVE INC and
|
|
|
397 DEC instructions."
|
|
|
398 (match_operand 0 "aarch64_sve_inc_dec_immediate"))
|
|
|
399
|
|
|
400 (define_constraint "vsn"
|
|
|
401 "@internal
|
|
|
402 A constraint that matches an immediate operand whose negative
|
|
|
403 is valid for SVE SUB instructions."
|
|
|
404 (match_operand 0 "aarch64_sve_sub_arith_immediate"))
|
|
|
405
|
|
|
406 (define_constraint "vsl"
|
|
|
407 "@internal
|
|
|
408 A constraint that matches an immediate operand valid for SVE logical
|
|
|
409 operations."
|
|
|
410 (match_operand 0 "aarch64_sve_logical_immediate"))
|
|
|
411
|
|
|
412 (define_constraint "vsm"
|
|
|
413 "@internal
|
|
|
414 A constraint that matches an immediate operand valid for SVE MUL
|
|
|
415 operations."
|
|
|
416 (match_operand 0 "aarch64_sve_mul_immediate"))
|
|
|
417
|
|
|
418 (define_constraint "vsA"
|
|
|
419 "@internal
|
|
|
420 A constraint that matches an immediate operand valid for SVE FADD
|
|
|
421 and FSUB operations."
|
|
|
422 (match_operand 0 "aarch64_sve_float_arith_immediate"))
|
|
|
423
|
|
|
424 (define_constraint "vsM"
|
|
|
425 "@internal
|
|
|
426 A constraint that matches an imediate operand valid for SVE FMUL
|
|
|
427 operations."
|
|
|
428 (match_operand 0 "aarch64_sve_float_mul_immediate"))
|
|
|
429
|
|
|
430 (define_constraint "vsN"
|
|
|
431 "@internal
|
|
|
432 A constraint that matches the negative of vsA"
|
|
|
433 (match_operand 0 "aarch64_sve_float_arith_with_sub_immediate"))
|
