Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/i386/cpuid.h @ 131:84e7813d76e9
gcc-8.2
author | mir3636 |
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date | Thu, 25 Oct 2018 07:37:49 +0900 |
parents | 04ced10e8804 |
children | 1830386684a0 |
rev | line source |
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0 | 1 /* |
131 | 2 * Copyright (C) 2007-2018 Free Software Foundation, Inc. |
0 | 3 * |
4 * This file is free software; you can redistribute it and/or modify it | |
5 * under the terms of the GNU General Public License as published by the | |
6 * Free Software Foundation; either version 3, or (at your option) any | |
7 * later version. | |
8 * | |
9 * This file is distributed in the hope that it will be useful, but | |
10 * WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
12 * General Public License for more details. | |
13 * | |
14 * Under Section 7 of GPL version 3, you are granted additional | |
15 * permissions described in the GCC Runtime Library Exception, version | |
16 * 3.1, as published by the Free Software Foundation. | |
17 * | |
18 * You should have received a copy of the GNU General Public License and | |
19 * a copy of the GCC Runtime Library Exception along with this program; | |
20 * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
21 * <http://www.gnu.org/licenses/>. | |
22 */ | |
23 | |
24 /* %ecx */ | |
25 #define bit_SSE3 (1 << 0) | |
26 #define bit_PCLMUL (1 << 1) | |
111 | 27 #define bit_LZCNT (1 << 5) |
0 | 28 #define bit_SSSE3 (1 << 9) |
29 #define bit_FMA (1 << 12) | |
30 #define bit_CMPXCHG16B (1 << 13) | |
31 #define bit_SSE4_1 (1 << 19) | |
32 #define bit_SSE4_2 (1 << 20) | |
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33 #define bit_MOVBE (1 << 22) |
0 | 34 #define bit_POPCNT (1 << 23) |
35 #define bit_AES (1 << 25) | |
36 #define bit_XSAVE (1 << 26) | |
37 #define bit_OSXSAVE (1 << 27) | |
38 #define bit_AVX (1 << 28) | |
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39 #define bit_F16C (1 << 29) |
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40 #define bit_RDRND (1 << 30) |
0 | 41 |
42 /* %edx */ | |
43 #define bit_CMPXCHG8B (1 << 8) | |
44 #define bit_CMOV (1 << 15) | |
45 #define bit_MMX (1 << 23) | |
46 #define bit_FXSAVE (1 << 24) | |
47 #define bit_SSE (1 << 25) | |
48 #define bit_SSE2 (1 << 26) | |
49 | |
111 | 50 /* Extended Features (%eax == 0x80000001) */ |
0 | 51 /* %ecx */ |
52 #define bit_LAHF_LM (1 << 0) | |
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53 #define bit_ABM (1 << 5) |
0 | 54 #define bit_SSE4a (1 << 6) |
111 | 55 #define bit_PRFCHW (1 << 8) |
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56 #define bit_XOP (1 << 11) |
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57 #define bit_LWP (1 << 15) |
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58 #define bit_FMA4 (1 << 16) |
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59 #define bit_TBM (1 << 21) |
111 | 60 #define bit_MWAITX (1 << 29) |
0 | 61 |
62 /* %edx */ | |
111 | 63 #define bit_MMXEXT (1 << 22) |
0 | 64 #define bit_LM (1 << 29) |
65 #define bit_3DNOWP (1 << 30) | |
111 | 66 #define bit_3DNOW (1u << 31) |
67 | |
68 /* %ebx */ | |
69 #define bit_CLZERO (1 << 0) | |
131 | 70 #define bit_WBNOINVD (1 << 9) |
0 | 71 |
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72 /* Extended Features (%eax == 7) */ |
111 | 73 /* %ebx */ |
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74 #define bit_FSGSBASE (1 << 0) |
111 | 75 #define bit_SGX (1 << 2) |
76 #define bit_BMI (1 << 3) | |
77 #define bit_HLE (1 << 4) | |
78 #define bit_AVX2 (1 << 5) | |
79 #define bit_BMI2 (1 << 8) | |
80 #define bit_RTM (1 << 11) | |
81 #define bit_MPX (1 << 14) | |
82 #define bit_AVX512F (1 << 16) | |
83 #define bit_AVX512DQ (1 << 17) | |
84 #define bit_RDSEED (1 << 18) | |
85 #define bit_ADX (1 << 19) | |
86 #define bit_AVX512IFMA (1 << 21) | |
87 #define bit_CLFLUSHOPT (1 << 23) | |
88 #define bit_CLWB (1 << 24) | |
89 #define bit_AVX512PF (1 << 26) | |
90 #define bit_AVX512ER (1 << 27) | |
91 #define bit_AVX512CD (1 << 28) | |
92 #define bit_SHA (1 << 29) | |
93 #define bit_AVX512BW (1 << 30) | |
94 #define bit_AVX512VL (1u << 31) | |
0 | 95 |
111 | 96 /* %ecx */ |
97 #define bit_PREFETCHWT1 (1 << 0) | |
98 #define bit_AVX512VBMI (1 << 1) | |
99 #define bit_PKU (1 << 3) | |
100 #define bit_OSPKE (1 << 4) | |
131 | 101 #define bit_WAITPKG (1 << 5) |
102 #define bit_AVX512VBMI2 (1 << 6) | |
111 | 103 #define bit_SHSTK (1 << 7) |
104 #define bit_GFNI (1 << 8) | |
131 | 105 #define bit_VAES (1 << 9) |
106 #define bit_AVX512VNNI (1 << 11) | |
107 #define bit_VPCLMULQDQ (1 << 10) | |
108 #define bit_AVX512BITALG (1 << 12) | |
111 | 109 #define bit_AVX512VPOPCNTDQ (1 << 14) |
110 #define bit_RDPID (1 << 22) | |
131 | 111 #define bit_MOVDIRI (1 << 27) |
112 #define bit_MOVDIR64B (1 << 28) | |
113 #define bit_CLDEMOTE (1 << 25) | |
111 | 114 |
115 /* %edx */ | |
116 #define bit_AVX5124VNNIW (1 << 2) | |
117 #define bit_AVX5124FMAPS (1 << 3) | |
118 #define bit_IBT (1 << 20) | |
131 | 119 #define bit_PCONFIG (1 << 18) |
111 | 120 /* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */ |
121 #define bit_BNDREGS (1 << 3) | |
122 #define bit_BNDCSR (1 << 4) | |
123 | |
124 /* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */ | |
125 #define bit_XSAVEOPT (1 << 0) | |
126 #define bit_XSAVEC (1 << 1) | |
127 #define bit_XSAVES (1 << 3) | |
0 | 128 |
111 | 129 /* Signatures for different CPU implementations as returned in uses |
130 of cpuid with level 0. */ | |
131 #define signature_AMD_ebx 0x68747541 | |
132 #define signature_AMD_ecx 0x444d4163 | |
133 #define signature_AMD_edx 0x69746e65 | |
134 | |
135 #define signature_CENTAUR_ebx 0x746e6543 | |
136 #define signature_CENTAUR_ecx 0x736c7561 | |
137 #define signature_CENTAUR_edx 0x48727561 | |
138 | |
139 #define signature_CYRIX_ebx 0x69727943 | |
140 #define signature_CYRIX_ecx 0x64616574 | |
141 #define signature_CYRIX_edx 0x736e4978 | |
142 | |
143 #define signature_INTEL_ebx 0x756e6547 | |
144 #define signature_INTEL_ecx 0x6c65746e | |
145 #define signature_INTEL_edx 0x49656e69 | |
146 | |
147 #define signature_TM1_ebx 0x6e617254 | |
148 #define signature_TM1_ecx 0x55504361 | |
149 #define signature_TM1_edx 0x74656d73 | |
150 | |
151 #define signature_TM2_ebx 0x756e6547 | |
152 #define signature_TM2_ecx 0x3638784d | |
153 #define signature_TM2_edx 0x54656e69 | |
0 | 154 |
111 | 155 #define signature_NSC_ebx 0x646f6547 |
156 #define signature_NSC_ecx 0x43534e20 | |
157 #define signature_NSC_edx 0x79622065 | |
158 | |
159 #define signature_NEXGEN_ebx 0x4778654e | |
160 #define signature_NEXGEN_ecx 0x6e657669 | |
161 #define signature_NEXGEN_edx 0x72446e65 | |
162 | |
163 #define signature_RISE_ebx 0x65736952 | |
164 #define signature_RISE_ecx 0x65736952 | |
165 #define signature_RISE_edx 0x65736952 | |
166 | |
167 #define signature_SIS_ebx 0x20536953 | |
168 #define signature_SIS_ecx 0x20536953 | |
169 #define signature_SIS_edx 0x20536953 | |
170 | |
171 #define signature_UMC_ebx 0x20434d55 | |
172 #define signature_UMC_ecx 0x20434d55 | |
173 #define signature_UMC_edx 0x20434d55 | |
174 | |
175 #define signature_VIA_ebx 0x20414956 | |
176 #define signature_VIA_ecx 0x20414956 | |
177 #define signature_VIA_edx 0x20414956 | |
178 | |
179 #define signature_VORTEX_ebx 0x74726f56 | |
180 #define signature_VORTEX_ecx 0x436f5320 | |
181 #define signature_VORTEX_edx 0x36387865 | |
182 | |
0 | 183 #define __cpuid(level, a, b, c, d) \ |
184 __asm__ ("cpuid\n\t" \ | |
185 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ | |
186 : "0" (level)) | |
187 | |
188 #define __cpuid_count(level, count, a, b, c, d) \ | |
189 __asm__ ("cpuid\n\t" \ | |
190 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ | |
191 : "0" (level), "2" (count)) | |
111 | 192 |
0 | 193 |
194 /* Return highest supported input value for cpuid instruction. ext can | |
111 | 195 be either 0x0 or 0x80000000 to return highest supported value for |
0 | 196 basic or extended cpuid information. Function returns 0 if cpuid |
197 is not supported or whatever cpuid returns in eax register. If sig | |
198 pointer is non-null, then first four bytes of the signature | |
199 (as found in ebx register) are returned in location pointed by sig. */ | |
200 | |
201 static __inline unsigned int | |
202 __get_cpuid_max (unsigned int __ext, unsigned int *__sig) | |
203 { | |
204 unsigned int __eax, __ebx, __ecx, __edx; | |
205 | |
206 #ifndef __x86_64__ | |
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207 /* See if we can use cpuid. On AMD64 we always can. */ |
0 | 208 #if __GNUC__ >= 3 |
209 __asm__ ("pushf{l|d}\n\t" | |
210 "pushf{l|d}\n\t" | |
211 "pop{l}\t%0\n\t" | |
212 "mov{l}\t{%0, %1|%1, %0}\n\t" | |
213 "xor{l}\t{%2, %0|%0, %2}\n\t" | |
214 "push{l}\t%0\n\t" | |
215 "popf{l|d}\n\t" | |
216 "pushf{l|d}\n\t" | |
217 "pop{l}\t%0\n\t" | |
218 "popf{l|d}\n\t" | |
219 : "=&r" (__eax), "=&r" (__ebx) | |
220 : "i" (0x00200000)); | |
221 #else | |
222 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax | |
223 nor alternatives in i386 code. */ | |
224 __asm__ ("pushfl\n\t" | |
225 "pushfl\n\t" | |
226 "popl\t%0\n\t" | |
227 "movl\t%0, %1\n\t" | |
228 "xorl\t%2, %0\n\t" | |
229 "pushl\t%0\n\t" | |
230 "popfl\n\t" | |
231 "pushfl\n\t" | |
232 "popl\t%0\n\t" | |
233 "popfl\n\t" | |
234 : "=&r" (__eax), "=&r" (__ebx) | |
235 : "i" (0x00200000)); | |
236 #endif | |
237 | |
238 if (!((__eax ^ __ebx) & 0x00200000)) | |
239 return 0; | |
240 #endif | |
241 | |
242 /* Host supports cpuid. Return highest supported cpuid input value. */ | |
243 __cpuid (__ext, __eax, __ebx, __ecx, __edx); | |
244 | |
245 if (__sig) | |
246 *__sig = __ebx; | |
247 | |
248 return __eax; | |
249 } | |
250 | |
111 | 251 /* Return cpuid data for requested cpuid leaf, as found in returned |
0 | 252 eax, ebx, ecx and edx registers. The function checks if cpuid is |
253 supported and returns 1 for valid cpuid information or 0 for | |
111 | 254 unsupported cpuid leaf. All pointers are required to be non-null. */ |
0 | 255 |
256 static __inline int | |
111 | 257 __get_cpuid (unsigned int __leaf, |
0 | 258 unsigned int *__eax, unsigned int *__ebx, |
259 unsigned int *__ecx, unsigned int *__edx) | |
260 { | |
111 | 261 unsigned int __ext = __leaf & 0x80000000; |
262 unsigned int __maxlevel = __get_cpuid_max (__ext, 0); | |
0 | 263 |
111 | 264 if (__maxlevel == 0 || __maxlevel < __leaf) |
0 | 265 return 0; |
266 | |
111 | 267 __cpuid (__leaf, *__eax, *__ebx, *__ecx, *__edx); |
0 | 268 return 1; |
269 } | |
111 | 270 |
271 /* Same as above, but sub-leaf can be specified. */ | |
272 | |
273 static __inline int | |
274 __get_cpuid_count (unsigned int __leaf, unsigned int __subleaf, | |
275 unsigned int *__eax, unsigned int *__ebx, | |
276 unsigned int *__ecx, unsigned int *__edx) | |
277 { | |
278 unsigned int __ext = __leaf & 0x80000000; | |
279 unsigned int __maxlevel = __get_cpuid_max (__ext, 0); | |
280 | |
281 if (__maxlevel == 0 || __maxlevel < __leaf) | |
282 return 0; | |
283 | |
284 __cpuid_count (__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx); | |
285 return 1; | |
286 } |