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1 ;; Octeon pipeline description.
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2 ;; Copyright (C) 2008-2018 Free Software Foundation, Inc.
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3
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4 ;; This file is part of GCC.
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5
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19 ;; Copyright (C) 2004, 2005, 2006 Cavium Networks.
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20
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21
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22 ;; Octeon is a dual-issue processor that can issue all instructions on
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23 ;; pipe0 and a subset on pipe1.
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24
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111
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25 (define_automaton "octeon_main, octeon_mult, octeon_fpu")
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0
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26
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27 (define_cpu_unit "octeon_pipe0" "octeon_main")
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28 (define_cpu_unit "octeon_pipe1" "octeon_main")
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29 (define_cpu_unit "octeon_mult" "octeon_mult")
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111
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30 (define_cpu_unit "octeon_fpu" "octeon_fpu")
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31
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32 (define_insn_reservation "octeon_arith" 1
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111
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33 (and (eq_attr "cpu" "octeon,octeon2,octeon3")
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34 (eq_attr "type" "arith,const,logical,move,shift,signext,slt,nop"))
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35 "octeon_pipe0 | octeon_pipe1")
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36
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111
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37 (define_insn_reservation "octeon_condmove_o1" 2
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38 (and (eq_attr "cpu" "octeon")
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39 (eq_attr "type" "condmove"))
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40 "octeon_pipe0 | octeon_pipe1")
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41
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111
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42 (define_insn_reservation "octeon_condmove_o2" 3
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43 (and (eq_attr "cpu" "octeon2,octeon3")
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44 (eq_attr "type" "condmove")
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45 (not (eq_attr "mode" "SF, DF")))
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46 "octeon_pipe0 | octeon_pipe1")
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47
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48 ;; movt/movf can only issue in pipe1
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49 (define_insn_reservation "octeon_condmove_o3_int_on_cc" 3
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50 (and (eq_attr "cpu" "octeon2,octeon3")
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51 (eq_attr "type" "condmove")
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52 (not (eq_attr "mode" "SF, DF")))
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53 "octeon_pipe1")
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54
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55 (define_insn_reservation "octeon_load_o1" 2
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56 (and (eq_attr "cpu" "octeon")
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57 (eq_attr "type" "load,prefetch,mtc,mfc"))
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58 "octeon_pipe0")
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59
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111
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60 (define_insn_reservation "octeon_load_o2" 3
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61 (and (eq_attr "cpu" "octeon2,octeon3")
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62 (eq_attr "type" "load,prefetch"))
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63 "octeon_pipe0")
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64
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65 ;; ??? memory-related cop0 reads are pipe0 with 3-cycle latency.
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66 ;; Front-end-related ones are 1-cycle on pipe1. Assume front-end for now.
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67 (define_insn_reservation "octeon_cop_o2" 1
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68 (and (eq_attr "cpu" "octeon2,octeon3")
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69 (eq_attr "type" "mtc,mfc"))
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70 "octeon_pipe1")
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71
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0
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72 (define_insn_reservation "octeon_store" 1
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111
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73 (and (eq_attr "cpu" "octeon,octeon2,octeon3")
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74 (eq_attr "type" "store"))
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75 "octeon_pipe0")
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76
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111
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77 (define_insn_reservation "octeon_brj_o1" 1
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78 (and (eq_attr "cpu" "octeon")
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79 (eq_attr "type" "branch,jump,call,trap"))
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80 "octeon_pipe0")
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81
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111
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82 (define_insn_reservation "octeon_brj_o2" 2
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83 (and (eq_attr "cpu" "octeon2,octeon3")
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84 (eq_attr "type" "branch,jump,call,trap"))
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85 "octeon_pipe1")
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86
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87 (define_insn_reservation "octeon_imul3_o1" 5
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88 (and (eq_attr "cpu" "octeon")
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89 (eq_attr "type" "imul3,pop,clz"))
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90 "(octeon_pipe0 | octeon_pipe1) + octeon_mult")
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91
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111
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92 (define_insn_reservation "octeon_imul3_o2" 6
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93 (and (eq_attr "cpu" "octeon2,octeon3")
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94 (eq_attr "type" "imul3,pop,clz"))
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95 "octeon_pipe1 + octeon_mult")
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96
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97 (define_insn_reservation "octeon_imul_o1" 2
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98 (and (eq_attr "cpu" "octeon")
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111
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99 (eq_attr "type" "imul,mthi,mtlo"))
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100 "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult")
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101
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111
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102 (define_insn_reservation "octeon_imul_o2" 1
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103 (and (eq_attr "cpu" "octeon2,octeon3")
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104 (eq_attr "type" "imul,mthi,mtlo"))
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105 "octeon_pipe1 + octeon_mult")
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106
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107 (define_insn_reservation "octeon_mfhilo_o1" 5
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108 (and (eq_attr "cpu" "octeon")
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111
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109 (eq_attr "type" "mfhi,mflo"))
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110 "(octeon_pipe0 | octeon_pipe1) + octeon_mult")
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111
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111
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112 (define_insn_reservation "octeon_mfhilo_o2" 6
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113 (and (eq_attr "cpu" "octeon2,octeon3")
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114 (eq_attr "type" "mfhi,mflo"))
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115 "octeon_pipe1 + octeon_mult")
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116
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117 (define_insn_reservation "octeon_imadd_o1" 4
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118 (and (eq_attr "cpu" "octeon")
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119 (eq_attr "type" "imadd"))
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120 "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*3")
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121
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111
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122 (define_insn_reservation "octeon_imadd_o2" 1
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123 (and (eq_attr "cpu" "octeon2,octeon3")
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124 (eq_attr "type" "imadd"))
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125 "octeon_pipe1 + octeon_mult")
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126
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127 (define_insn_reservation "octeon_idiv_o1" 72
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128 (and (eq_attr "cpu" "octeon")
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129 (eq_attr "type" "idiv"))
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130 "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*71")
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131
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111
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132 (define_insn_reservation "octeon_idiv_o2_si" 18
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133 (and (eq_attr "cpu" "octeon2,octeon3")
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134 (eq_attr "mode" "SI")
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135 (eq_attr "type" "idiv"))
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136 "octeon_pipe1 + octeon_mult, octeon_mult*17")
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137
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138 (define_insn_reservation "octeon_idiv_o2_di" 35
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139 (and (eq_attr "cpu" "octeon2,octeon3")
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140 (eq_attr "mode" "DI")
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141 (eq_attr "type" "idiv"))
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142 "octeon_pipe1 + octeon_mult, octeon_mult*34")
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143
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0
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144 ;; Assume both pipes are needed for unknown and multiple-instruction
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145 ;; patterns.
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146
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147 (define_insn_reservation "octeon_unknown" 1
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111
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148 (and (eq_attr "cpu" "octeon,octeon2,octeon3")
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149 (eq_attr "type" "unknown,multi,atomic,syncloop"))
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150 "octeon_pipe0 + octeon_pipe1")
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111
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151
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152 ;; Octeon3 FPU
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153
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154 (define_insn_reservation "octeon3_faddsubcvt" 4
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155 (and (eq_attr "cpu" "octeon3")
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156 (eq_attr "type" "fadd, fcvt"))
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157 "octeon_pipe1 + octeon_fpu")
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158
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159 (define_insn_reservation "octeon3_fmul" 5
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160 (and (eq_attr "cpu" "octeon3")
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161 (eq_attr "type" "fmul"))
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162 "octeon_pipe1 + octeon_fpu")
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163
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164 (define_insn_reservation "octeon3_fmadd" 9
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165 (and (eq_attr "cpu" "octeon3")
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166 (eq_attr "type" "fmadd"))
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167 "octeon_pipe1 + octeon_fpu, octeon_fpu")
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168
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169 (define_insn_reservation "octeon3_div_sf" 12
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170 (and (eq_attr "cpu" "octeon3")
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171 (eq_attr "type" "fdiv, frdiv")
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172 (eq_attr "mode" "SF"))
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173 "octeon_pipe1 + octeon_fpu, octeon_fpu*8")
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174
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175 (define_insn_reservation "octeon3_div_df" 22
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176 (and (eq_attr "cpu" "octeon3")
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177 (eq_attr "type" "fdiv, frdiv")
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178 (eq_attr "mode" "SF"))
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179 "octeon_pipe1 + octeon_fpu, octeon_fpu*18")
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180
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181 (define_insn_reservation "octeon3_sqrt_sf" 16
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182 (and (eq_attr "cpu" "octeon3")
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183 (eq_attr "type" "fsqrt")
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184 (eq_attr "mode" "SF"))
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185 "octeon_pipe1 + octeon_fpu, octeon_fpu*12")
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186
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187 (define_insn_reservation "octeon3_sqrt_df" 30
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188 (and (eq_attr "cpu" "octeon3")
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189 (eq_attr "type" "fsqrt")
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190 (eq_attr "mode" "DF"))
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191 "octeon_pipe1 + octeon_fpu, octeon_fpu*26")
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192
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193 (define_insn_reservation "octeon3_rsqrt_sf" 27
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194 (and (eq_attr "cpu" "octeon3")
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195 (eq_attr "type" "frsqrt")
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196 (eq_attr "mode" "SF"))
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197 "octeon_pipe1 + octeon_fpu, octeon_fpu*23")
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198
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199 (define_insn_reservation "octeon3_rsqrt_df" 51
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200 (and (eq_attr "cpu" "octeon3")
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201 (eq_attr "type" "frsqrt")
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202 (eq_attr "mode" "DF"))
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203 "octeon_pipe1 + octeon_fpu, octeon_fpu*47")
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204
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205 (define_insn_reservation "octeon3_fabsnegmov" 2
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206 (and (eq_attr "cpu" "octeon3")
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207 (eq_attr "type" "fabs, fneg, fmove"))
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208 "octeon_pipe1 + octeon_fpu")
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209
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210 (define_insn_reservation "octeon_fcond" 1
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211 (and (eq_attr "cpu" "octeon3")
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212 (eq_attr "type" "fcmp"))
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213 "octeon_pipe1 + octeon_fpu")
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214
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215 (define_insn_reservation "octeon_fcondmov" 2
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216 (and (eq_attr "cpu" "octeon3")
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217 (eq_attr "type" "condmove")
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218 (eq_attr "mode" "SF,DF"))
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219 "octeon_pipe1 + octeon_fpu")
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220
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221 (define_insn_reservation "octeon_fpmtc1" 2
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222 (and (eq_attr "cpu" "octeon3")
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223 (eq_attr "type" "mtc"))
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224 "octeon_pipe1 + octeon_fpu")
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225
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226 (define_insn_reservation "octeon_fpmfc1" 6
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227 (and (eq_attr "cpu" "octeon3")
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228 (eq_attr "type" "mtc"))
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229 "octeon_pipe1 + octeon_fpu")
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230
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231 (define_insn_reservation "octeon_fpload" 3
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232 (and (eq_attr "cpu" "octeon3")
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233 (eq_attr "type" "fpload,fpidxload"))
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234 "octeon_pipe0 + octeon_fpu")
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235
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236 (define_insn_reservation "octeon_fpstore" 3
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237 (and (eq_attr "cpu" "octeon3")
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238 (eq_attr "type" "fpstore,fpidxstore"))
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239 "octeon_pipe0 + octeon_pipe1")
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