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111
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1 /* Predicate functions of Andes NDS32 cpu for GNU compiler
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131
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2 Copyright (C) 2012-2018 Free Software Foundation, Inc.
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111
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3 Contributed by Andes Technology Corporation.
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify it
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8 under the terms of the GNU General Public License as published
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9 by the Free Software Foundation; either version 3, or (at your
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10 option) any later version.
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11
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12 GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 License for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21 /* ------------------------------------------------------------------------ */
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22
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131
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23 #define IN_TARGET_CODE 1
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24
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111
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25 #include "config.h"
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26 #include "system.h"
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27 #include "coretypes.h"
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28 #include "backend.h"
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29 #include "target.h"
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30 #include "rtl.h"
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31 #include "tree.h"
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32 #include "memmodel.h"
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33 #include "tm_p.h"
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34 #include "optabs.h" /* For GEN_FCN. */
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35 #include "emit-rtl.h"
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36 #include "recog.h"
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37 #include "tm-constrs.h"
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131
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38 #include "insn-attr.h"
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111
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39
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40 /* ------------------------------------------------------------------------ */
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41
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42 /* A subroutine that checks multiple load and store
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43 using consecutive registers.
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44 OP is a parallel rtx we would like to check.
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45 LOAD_P indicates whether we are checking load operation.
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46 PAR_INDEX is starting element of parallel rtx.
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47 FIRST_ELT_REGNO is used to tell starting register number.
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48 COUNT helps us to check consecutive register numbers. */
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49 static bool
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50 nds32_consecutive_registers_load_store_p (rtx op,
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51 bool load_p,
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52 int par_index,
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53 int first_elt_regno,
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54 int count)
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55 {
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56 int i;
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57 int check_regno;
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58 rtx elt;
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59 rtx elt_reg;
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60 rtx elt_mem;
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61
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62 for (i = 0; i < count; i++)
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63 {
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64 /* Pick up each element from parallel rtx. */
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65 elt = XVECEXP (op, 0, i + par_index);
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66
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67 /* If this element is not a 'set' rtx, return false immediately. */
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68 if (GET_CODE (elt) != SET)
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69 return false;
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70
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71 /* Pick up reg and mem of this element. */
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72 elt_reg = load_p ? SET_DEST (elt) : SET_SRC (elt);
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73 elt_mem = load_p ? SET_SRC (elt) : SET_DEST (elt);
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74
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75 /* If elt_reg is not a expected reg rtx, return false. */
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76 if (GET_CODE (elt_reg) != REG || GET_MODE (elt_reg) != SImode)
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77 return false;
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78 /* If elt_mem is not a expected mem rtx, return false. */
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79 if (GET_CODE (elt_mem) != MEM || GET_MODE (elt_mem) != SImode)
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80 return false;
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81
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82 /* The consecutive registers should be in (Rb,Rb+1...Re) order. */
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83 check_regno = first_elt_regno + i;
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84
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85 /* If the register number is not continuous, return false. */
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86 if (REGNO (elt_reg) != (unsigned int) check_regno)
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87 return false;
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88 }
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89
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90 return true;
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91 }
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92
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93 /* Function to check whether the OP is a valid load/store operation.
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94 This is a helper function for the predicates:
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95 'nds32_load_multiple_operation' and 'nds32_store_multiple_operation'
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96 in predicates.md file.
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97
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98 The OP is supposed to be a parallel rtx.
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99 For each element within this parallel rtx:
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100 (set (reg) (mem addr)) is the form for load operation.
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101 (set (mem addr) (reg)) is the form for store operation.
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102 We have to extract reg and mem of every element and
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103 check if the information is valid for multiple load/store operation. */
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104 bool
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131
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105 nds32_valid_multiple_load_store_p (rtx op, bool load_p, bool bim_p)
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111
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106 {
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107 int count;
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108 int first_elt_regno;
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131
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109 int update_base_elt_idx;
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110 int offset;
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111
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111 rtx elt;
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131
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112 rtx update_base;
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111
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113
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131
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114 /* Get the counts of elements in the parallel rtx.
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115 Last one is update base register if bim_p.
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116 and pick up the first element. */
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117 if (bim_p)
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118 {
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119 count = XVECLEN (op, 0) - 1;
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120 elt = XVECEXP (op, 0, 1);
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121 }
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122 else
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123 {
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124 count = XVECLEN (op, 0);
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125 elt = XVECEXP (op, 0, 0);
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126 }
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111
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127
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128 /* Perform some quick check for the first element in the parallel rtx. */
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129 if (GET_CODE (elt) != SET
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130 || count <= 1
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131
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131 || count > 25)
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111
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132 return false;
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133
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134 /* Pick up regno of first element for further detail checking.
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135 Note that the form is different between load and store operation. */
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136 if (load_p)
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137 {
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138 if (GET_CODE (SET_DEST (elt)) != REG
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139 || GET_CODE (SET_SRC (elt)) != MEM)
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140 return false;
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141
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142 first_elt_regno = REGNO (SET_DEST (elt));
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143 }
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144 else
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145 {
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146 if (GET_CODE (SET_SRC (elt)) != REG
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147 || GET_CODE (SET_DEST (elt)) != MEM)
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148 return false;
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149
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150 first_elt_regno = REGNO (SET_SRC (elt));
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151 }
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152
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153 /* Perform detail check for each element.
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154 Refer to nds32-multiple.md for more information
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155 about following checking.
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156 The starting element of parallel rtx is index 0. */
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131
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157 if (!nds32_consecutive_registers_load_store_p (op, load_p, bim_p ? 1 : 0,
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111
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158 first_elt_regno,
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159 count))
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160 return false;
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161
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131
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162 if (bim_p)
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163 {
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164 update_base_elt_idx = 0;
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165 update_base = XVECEXP (op, 0, update_base_elt_idx);
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166 if (!REG_P (SET_DEST (update_base)))
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167 return false;
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168 if (GET_CODE (SET_SRC (update_base)) != PLUS)
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169 return false;
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170 else
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171 {
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172 offset = count * UNITS_PER_WORD;
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173 elt = XEXP (SET_SRC (update_base), 1);
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174 if (GET_CODE (elt) != CONST_INT
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175 || (INTVAL (elt) != offset))
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176 return false;
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177 }
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178 }
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179
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111
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180 /* Pass all test, this is a valid rtx. */
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181 return true;
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182 }
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183
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184 /* Function to check whether the OP is a valid stack push/pop operation.
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185 For a valid stack operation, it must satisfy following conditions:
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186 1. Consecutive registers push/pop operations.
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187 2. Valid $fp/$gp/$lp push/pop operations.
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188 3. The last element must be stack adjustment rtx.
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189 See the prologue/epilogue implementation for details. */
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190 bool
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191 nds32_valid_stack_push_pop_p (rtx op, bool push_p)
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192 {
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193 int index;
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194 int total_count;
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195 int rest_count;
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196 int first_regno;
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197 int save_fp, save_gp, save_lp;
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198 rtx elt;
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199 rtx elt_reg;
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200 rtx elt_mem;
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201 rtx elt_plus;
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202
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203 /* Get the counts of elements in the parallel rtx. */
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204 total_count = XVECLEN (op, 0);
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205
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206 /* Perform some quick check for that every element should be 'set'. */
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207 for (index = 0; index < total_count; index++)
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208 {
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209 elt = XVECEXP (op, 0, index);
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210 if (GET_CODE (elt) != SET)
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211 return false;
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212 }
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213
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214 /* For push operation, the parallel rtx looks like:
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215 (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
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216 (reg:SI Rb))
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217 (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
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218 (reg:SI Rb+1))
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219 ...
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220 (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
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221 (reg:SI Re))
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222 (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
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223 (reg:SI FP_REGNUM))
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224 (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
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225 (reg:SI GP_REGNUM))
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226 (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
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227 (reg:SI LP_REGNUM))
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228 (set (reg:SI SP_REGNUM)
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229 (plus (reg:SI SP_REGNUM) (const_int -32)))])
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230
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231 For pop operation, the parallel rtx looks like:
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232 (parallel [(set (reg:SI Rb)
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233 (mem (reg:SI SP_REGNUM)))
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234 (set (reg:SI Rb+1)
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235 (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
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236 ...
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237 (set (reg:SI Re)
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238 (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
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239 (set (reg:SI FP_REGNUM)
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240 (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
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241 (set (reg:SI GP_REGNUM)
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242 (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
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243 (set (reg:SI LP_REGNUM)
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244 (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
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245 (set (reg:SI SP_REGNUM)
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246 (plus (reg:SI SP_REGNUM) (const_int 32)))]) */
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247
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248 /* 1. Consecutive registers push/pop operations.
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249 We need to calculate how many registers should be consecutive.
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250 The $sp adjustment rtx, $fp push rtx, $gp push rtx,
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251 and $lp push rtx are excluded. */
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252
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253 /* Detect whether we have $fp, $gp, or $lp in the parallel rtx. */
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254 save_fp = reg_mentioned_p (gen_rtx_REG (SImode, FP_REGNUM), op);
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255 save_gp = reg_mentioned_p (gen_rtx_REG (SImode, GP_REGNUM), op);
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256 save_lp = reg_mentioned_p (gen_rtx_REG (SImode, LP_REGNUM), op);
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257 /* Exclude last $sp adjustment rtx. */
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258 rest_count = total_count - 1;
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259 /* Exclude $fp, $gp, and $lp if they are in the parallel rtx. */
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260 if (save_fp)
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261 rest_count--;
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262 if (save_gp)
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263 rest_count--;
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264 if (save_lp)
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265 rest_count--;
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266
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267 if (rest_count > 0)
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268 {
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269 elt = XVECEXP (op, 0, 0);
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270 /* Pick up register element. */
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271 elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
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272 first_regno = REGNO (elt_reg);
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273
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274 /* The 'push' operation is a kind of store operation.
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275 The 'pop' operation is a kind of load operation.
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276 Pass corresponding false/true as second argument (bool load_p).
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277 The par_index is supposed to start with index 0. */
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278 if (!nds32_consecutive_registers_load_store_p (op,
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279 !push_p ? true : false,
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280 0,
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281 first_regno,
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282 rest_count))
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283 return false;
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284 }
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285
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286 /* 2. Valid $fp/$gp/$lp push/pop operations.
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287 Remember to set start index for checking them. */
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288
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289 /* The rest_count is the start index for checking $fp/$gp/$lp. */
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290 index = rest_count;
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291 /* If index < 0, this parallel rtx is definitely
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292 not a valid stack push/pop operation. */
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293 if (index < 0)
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294 return false;
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295
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296 /* Check $fp/$gp/$lp one by one.
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297 We use 'push_p' to pick up reg rtx and mem rtx. */
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298 if (save_fp)
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299 {
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300 elt = XVECEXP (op, 0, index);
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301 elt_mem = push_p ? SET_DEST (elt) : SET_SRC (elt);
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302 elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
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303 index++;
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304
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305 if (GET_CODE (elt_mem) != MEM
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306 || GET_CODE (elt_reg) != REG
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307 || REGNO (elt_reg) != FP_REGNUM)
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308 return false;
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309 }
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310 if (save_gp)
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311 {
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312 elt = XVECEXP (op, 0, index);
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313 elt_mem = push_p ? SET_DEST (elt) : SET_SRC (elt);
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314 elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
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315 index++;
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316
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317 if (GET_CODE (elt_mem) != MEM
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318 || GET_CODE (elt_reg) != REG
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319 || REGNO (elt_reg) != GP_REGNUM)
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320 return false;
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321 }
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322 if (save_lp)
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323 {
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324 elt = XVECEXP (op, 0, index);
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325 elt_mem = push_p ? SET_DEST (elt) : SET_SRC (elt);
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326 elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
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327 index++;
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328
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329 if (GET_CODE (elt_mem) != MEM
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330 || GET_CODE (elt_reg) != REG
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331 || REGNO (elt_reg) != LP_REGNUM)
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332 return false;
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333 }
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334
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335 /* 3. The last element must be stack adjustment rtx.
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336 Its form of rtx should be:
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337 (set (reg:SI SP_REGNUM)
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338 (plus (reg:SI SP_REGNUM) (const_int X)))
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339 The X could be positive or negative value. */
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340
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341 /* Pick up the last element. */
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342 elt = XVECEXP (op, 0, total_count - 1);
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343
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344 /* Extract its destination and source rtx. */
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345 elt_reg = SET_DEST (elt);
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346 elt_plus = SET_SRC (elt);
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347
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348 /* Check this is (set (stack_reg) (plus stack_reg const)) pattern. */
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349 if (GET_CODE (elt_reg) != REG
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350 || GET_CODE (elt_plus) != PLUS
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351 || REGNO (elt_reg) != SP_REGNUM)
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352 return false;
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353
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354 /* Pass all test, this is a valid rtx. */
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355 return true;
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356 }
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357
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358 /* Function to check if 'bclr' instruction can be used with IVAL. */
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131
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359 bool
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360 nds32_can_use_bclr_p (HOST_WIDE_INT ival)
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111
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361 {
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362 int one_bit_count;
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131
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363 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (SImode);
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111
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364
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365 /* Calculate the number of 1-bit of (~ival), if there is only one 1-bit,
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366 it means the original ival has only one 0-bit,
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367 So it is ok to perform 'bclr' operation. */
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368
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131
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369 one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (~ival) & mask);
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111
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370
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371 /* 'bclr' is a performance extension instruction. */
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131
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372 return (TARGET_EXT_PERF && (one_bit_count == 1));
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111
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373 }
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374
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375 /* Function to check if 'bset' instruction can be used with IVAL. */
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131
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376 bool
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377 nds32_can_use_bset_p (HOST_WIDE_INT ival)
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111
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378 {
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379 int one_bit_count;
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131
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380 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (SImode);
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111
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381
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382 /* Caculate the number of 1-bit of ival, if there is only one 1-bit,
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383 it is ok to perform 'bset' operation. */
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384
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131
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385 one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival) & mask);
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|
111
|
386
|
|
|
387 /* 'bset' is a performance extension instruction. */
|
|
131
|
388 return (TARGET_EXT_PERF && (one_bit_count == 1));
|
|
111
|
389 }
|
|
|
390
|
|
|
391 /* Function to check if 'btgl' instruction can be used with IVAL. */
|
|
131
|
392 bool
|
|
|
393 nds32_can_use_btgl_p (HOST_WIDE_INT ival)
|
|
111
|
394 {
|
|
|
395 int one_bit_count;
|
|
131
|
396 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (SImode);
|
|
111
|
397
|
|
|
398 /* Caculate the number of 1-bit of ival, if there is only one 1-bit,
|
|
|
399 it is ok to perform 'btgl' operation. */
|
|
|
400
|
|
131
|
401 one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival) & mask);
|
|
111
|
402
|
|
|
403 /* 'btgl' is a performance extension instruction. */
|
|
131
|
404 return (TARGET_EXT_PERF && (one_bit_count == 1));
|
|
111
|
405 }
|
|
|
406
|
|
|
407 /* Function to check if 'bitci' instruction can be used with IVAL. */
|
|
131
|
408 bool
|
|
|
409 nds32_can_use_bitci_p (HOST_WIDE_INT ival)
|
|
111
|
410 {
|
|
|
411 /* If we are using V3 ISA, we have 'bitci' instruction.
|
|
|
412 Try to see if we can present 'andi' semantic with
|
|
|
413 such 'bit-clear-immediate' operation.
|
|
|
414 For example, 'andi $r0,$r0,0xfffffffc' can be
|
|
|
415 presented with 'bitci $r0,$r0,3'. */
|
|
|
416 return (TARGET_ISA_V3
|
|
|
417 && (ival < 0)
|
|
|
418 && satisfies_constraint_Iu15 (gen_int_mode (~ival, SImode)));
|
|
|
419 }
|
|
|
420
|
|
131
|
421 /* Return true if is load/store with SYMBOL_REF addressing mode
|
|
|
422 and memory mode is SImode. */
|
|
|
423 bool
|
|
|
424 nds32_symbol_load_store_p (rtx_insn *insn)
|
|
|
425 {
|
|
|
426 rtx mem_src = NULL_RTX;
|
|
|
427
|
|
|
428 switch (get_attr_type (insn))
|
|
|
429 {
|
|
|
430 case TYPE_LOAD:
|
|
|
431 mem_src = SET_SRC (PATTERN (insn));
|
|
|
432 break;
|
|
|
433 case TYPE_STORE:
|
|
|
434 mem_src = SET_DEST (PATTERN (insn));
|
|
|
435 break;
|
|
|
436 default:
|
|
|
437 break;
|
|
|
438 }
|
|
|
439
|
|
|
440 /* Find load/store insn with addressing mode is SYMBOL_REF. */
|
|
|
441 if (mem_src != NULL_RTX)
|
|
|
442 {
|
|
|
443 if ((GET_CODE (mem_src) == ZERO_EXTEND)
|
|
|
444 || (GET_CODE (mem_src) == SIGN_EXTEND))
|
|
|
445 mem_src = XEXP (mem_src, 0);
|
|
|
446
|
|
|
447 if ((GET_CODE (XEXP (mem_src, 0)) == SYMBOL_REF)
|
|
|
448 || (GET_CODE (XEXP (mem_src, 0)) == LO_SUM))
|
|
|
449 return true;
|
|
|
450 }
|
|
|
451
|
|
|
452 return false;
|
|
|
453 }
|
|
|
454
|
|
|
455 /* Vaild memory operand for floating-point loads and stores */
|
|
|
456 bool
|
|
|
457 nds32_float_mem_operand_p (rtx op)
|
|
|
458 {
|
|
|
459 machine_mode mode = GET_MODE (op);
|
|
|
460 rtx addr = XEXP (op, 0);
|
|
|
461
|
|
|
462 /* Not support [symbol] [const] memory */
|
|
|
463 if (GET_CODE (addr) == SYMBOL_REF
|
|
|
464 || GET_CODE (addr) == CONST
|
|
|
465 || GET_CODE (addr) == LO_SUM)
|
|
|
466 return false;
|
|
|
467
|
|
|
468 if (GET_CODE (addr) == PLUS)
|
|
|
469 {
|
|
|
470 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF)
|
|
|
471 return false;
|
|
|
472
|
|
|
473 /* Restrict const range: (imm12s << 2) */
|
|
|
474 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
|
|
|
475 {
|
|
|
476 if ((mode == SImode || mode == SFmode)
|
|
|
477 && NDS32_SINGLE_WORD_ALIGN_P (INTVAL (XEXP (addr, 1)))
|
|
|
478 && !satisfies_constraint_Is14 ( XEXP(addr, 1)))
|
|
|
479 return false;
|
|
|
480
|
|
|
481 if ((mode == DImode || mode == DFmode)
|
|
|
482 && NDS32_DOUBLE_WORD_ALIGN_P (INTVAL (XEXP (addr, 1)))
|
|
|
483 && !satisfies_constraint_Is14 (XEXP (addr, 1)))
|
|
|
484 return false;
|
|
|
485 }
|
|
|
486 }
|
|
|
487
|
|
|
488 return true;
|
|
|
489 }
|
|
|
490
|
|
|
491 int
|
|
|
492 nds32_cond_move_p (rtx cmp_rtx)
|
|
|
493 {
|
|
|
494 machine_mode cmp0_mode = GET_MODE (XEXP (cmp_rtx, 0));
|
|
|
495 machine_mode cmp1_mode = GET_MODE (XEXP (cmp_rtx, 1));
|
|
|
496 enum rtx_code cond = GET_CODE (cmp_rtx);
|
|
|
497
|
|
|
498 if ((cmp0_mode == DFmode || cmp0_mode == SFmode)
|
|
|
499 && (cmp1_mode == DFmode || cmp1_mode == SFmode)
|
|
|
500 && (cond == ORDERED || cond == UNORDERED))
|
|
|
501 return true;
|
|
|
502 return false;
|
|
|
503 }
|
|
|
504
|
|
|
505 bool
|
|
|
506 nds32_const_double_range_ok_p (rtx op, machine_mode mode,
|
|
|
507 HOST_WIDE_INT lower, HOST_WIDE_INT upper)
|
|
|
508 {
|
|
|
509 if (GET_CODE (op) != CONST_DOUBLE
|
|
|
510 || GET_MODE (op) != mode)
|
|
|
511 return false;
|
|
|
512
|
|
|
513 const REAL_VALUE_TYPE *rv;
|
|
|
514 long val;
|
|
|
515
|
|
|
516 rv = CONST_DOUBLE_REAL_VALUE (op);
|
|
|
517 REAL_VALUE_TO_TARGET_SINGLE (*rv, val);
|
|
|
518
|
|
|
519 return val >= lower && val < upper;
|
|
|
520 }
|
|
|
521
|
|
|
522 bool
|
|
|
523 nds32_const_unspec_p (rtx x)
|
|
|
524 {
|
|
|
525 if (GET_CODE (x) == CONST)
|
|
|
526 {
|
|
|
527 x = XEXP (x, 0);
|
|
|
528
|
|
|
529 if (GET_CODE (x) == PLUS)
|
|
|
530 x = XEXP (x, 0);
|
|
|
531
|
|
|
532 if (GET_CODE (x) == UNSPEC)
|
|
|
533 {
|
|
|
534 switch (XINT (x, 1))
|
|
|
535 {
|
|
|
536 case UNSPEC_GOTINIT:
|
|
|
537 case UNSPEC_GOT:
|
|
|
538 case UNSPEC_GOTOFF:
|
|
|
539 case UNSPEC_PLT:
|
|
|
540 case UNSPEC_TLSGD:
|
|
|
541 case UNSPEC_TLSLD:
|
|
|
542 case UNSPEC_TLSIE:
|
|
|
543 case UNSPEC_TLSLE:
|
|
|
544 return false;
|
|
|
545 default:
|
|
|
546 return true;
|
|
|
547 }
|
|
|
548 }
|
|
|
549 }
|
|
|
550
|
|
|
551 if (GET_CODE (x) == SYMBOL_REF
|
|
|
552 && SYMBOL_REF_TLS_MODEL (x))
|
|
|
553 return false;
|
|
|
554
|
|
|
555 return true;
|
|
|
556 }
|
|
|
557
|
|
|
558 HOST_WIDE_INT
|
|
|
559 const_vector_to_hwint (rtx op)
|
|
|
560 {
|
|
|
561 HOST_WIDE_INT hwint = 0;
|
|
|
562 HOST_WIDE_INT mask;
|
|
|
563 int i;
|
|
|
564 int shift_adv;
|
|
|
565 int shift = 0;
|
|
|
566 int nelem;
|
|
|
567
|
|
|
568 switch (GET_MODE (op))
|
|
|
569 {
|
|
|
570 case E_V2HImode:
|
|
|
571 mask = 0xffff;
|
|
|
572 shift_adv = 16;
|
|
|
573 nelem = 2;
|
|
|
574 break;
|
|
|
575 case E_V4QImode:
|
|
|
576 mask = 0xff;
|
|
|
577 shift_adv = 8;
|
|
|
578 nelem = 4;
|
|
|
579 break;
|
|
|
580 default:
|
|
|
581 gcc_unreachable ();
|
|
|
582 }
|
|
|
583
|
|
|
584 if (TARGET_BIG_ENDIAN)
|
|
|
585 {
|
|
|
586 for (i = 0; i < nelem; ++i)
|
|
|
587 {
|
|
|
588 HOST_WIDE_INT val = XINT (XVECEXP (op, 0, nelem - i - 1), 0);
|
|
|
589 hwint |= (val & mask) << shift;
|
|
|
590 shift = shift + shift_adv;
|
|
|
591 }
|
|
|
592 }
|
|
|
593 else
|
|
|
594 {
|
|
|
595 for (i = 0; i < nelem; ++i)
|
|
|
596 {
|
|
|
597 HOST_WIDE_INT val = XINT (XVECEXP (op, 0, i), 0);
|
|
|
598 hwint |= (val & mask) << shift;
|
|
|
599 shift = shift + shift_adv;
|
|
|
600 }
|
|
|
601 }
|
|
|
602
|
|
|
603 return hwint;
|
|
|
604 }
|
|
|
605
|
|
|
606 bool
|
|
|
607 nds32_valid_CVp5_p (rtx op)
|
|
|
608 {
|
|
|
609 HOST_WIDE_INT ival = const_vector_to_hwint (op);
|
|
|
610 return (ival < ((1 << 5) + 16)) && (ival >= (0 + 16));
|
|
|
611 }
|
|
|
612
|
|
|
613 bool
|
|
|
614 nds32_valid_CVs5_p (rtx op)
|
|
|
615 {
|
|
|
616 HOST_WIDE_INT ival = const_vector_to_hwint (op);
|
|
|
617 return (ival < (1 << 4)) && (ival >= -(1 << 4));
|
|
|
618 }
|
|
|
619
|
|
|
620 bool
|
|
|
621 nds32_valid_CVs2_p (rtx op)
|
|
|
622 {
|
|
|
623 HOST_WIDE_INT ival = const_vector_to_hwint (op);
|
|
|
624 return (ival < (1 << 19)) && (ival >= -(1 << 19));
|
|
|
625 }
|
|
|
626
|
|
|
627 bool
|
|
|
628 nds32_valid_CVhi_p (rtx op)
|
|
|
629 {
|
|
|
630 HOST_WIDE_INT ival = const_vector_to_hwint (op);
|
|
|
631 return (ival != 0) && ((ival & 0xfff) == 0);
|
|
|
632 }
|
|
|
633
|
|
111
|
634 /* ------------------------------------------------------------------------ */
|
