Mercurial > hg > CbC > CbC_gcc

annotate gcc/config/rs6000/power9.md @ 131:84e7813d76e9

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
111
kono
parents:
diff changeset
1 ;; Scheduling description for IBM POWER9 processor.
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
2 ;; Copyright (C) 2016-2018 Free Software Foundation, Inc.
111
kono
parents:
diff changeset
3 ;;
kono
parents:
diff changeset
4 ;; Contributed by Pat Haugen (pthaugen@us.ibm.com).
kono
parents:
diff changeset
5
kono
parents:
diff changeset
6 ;; This file is part of GCC.
kono
parents:
diff changeset
7 ;;
kono
parents:
diff changeset
8 ;; GCC is free software; you can redistribute it and/or modify it
kono
parents:
diff changeset
9 ;; under the terms of the GNU General Public License as published
kono
parents:
diff changeset
10 ;; by the Free Software Foundation; either version 3, or (at your
kono
parents:
diff changeset
11 ;; option) any later version.
kono
parents:
diff changeset
12 ;;
kono
parents:
diff changeset
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
kono
parents:
diff changeset
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
kono
parents:
diff changeset
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
kono
parents:
diff changeset
16 ;; License for more details.
kono
parents:
diff changeset
17 ;;
kono
parents:
diff changeset
18 ;; You should have received a copy of the GNU General Public License
kono
parents:
diff changeset
19 ;; along with GCC; see the file COPYING3. If not see
kono
parents:
diff changeset
20 ;; <http://www.gnu.org/licenses/>.
kono
parents:
diff changeset
21
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
22 (define_automaton "power9dsp,power9lsu,power9vsu,power9fpdiv,power9misc")
111
kono
parents:
diff changeset
23
kono
parents:
diff changeset
24 (define_cpu_unit "lsu0_power9,lsu1_power9,lsu2_power9,lsu3_power9" "power9lsu")
kono
parents:
diff changeset
25 (define_cpu_unit "vsu0_power9,vsu1_power9,vsu2_power9,vsu3_power9" "power9vsu")
kono
parents:
diff changeset
26 ; Two vector permute units, part of vsu
kono
parents:
diff changeset
27 (define_cpu_unit "prm0_power9,prm1_power9" "power9vsu")
kono
parents:
diff changeset
28 ; Two fixed point divide units, not pipelined
kono
parents:
diff changeset
29 (define_cpu_unit "fx_div0_power9,fx_div1_power9" "power9misc")
kono
parents:
diff changeset
30 (define_cpu_unit "bru_power9,cryptu_power9,dfu_power9" "power9misc")
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
31 ; Create a false unit for use by non-pipelined FP div/sqrt
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
32 (define_cpu_unit "fp_div0_power9,fp_div1_power9,fp_div2_power9,fp_div3_power9"
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
33 "power9fpdiv")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
34
111
kono
parents:
diff changeset
35
kono
parents:
diff changeset
36 (define_cpu_unit "x0_power9,x1_power9,xa0_power9,xa1_power9,
kono
parents:
diff changeset
37 x2_power9,x3_power9,xb0_power9,xb1_power9,
kono
parents:
diff changeset
38 br0_power9,br1_power9" "power9dsp")
kono
parents:
diff changeset
39
kono
parents:
diff changeset
40
kono
parents:
diff changeset
41 ; Dispatch port reservations
kono
parents:
diff changeset
42 ;
kono
parents:
diff changeset
43 ; Power9 can dispatch a maximum of 6 iops per cycle with the following
kono
parents:
diff changeset
44 ; general restrictions (other restrictions also apply):
kono
parents:
diff changeset
45 ; 1) At most 2 iops per execution slice
kono
parents:
diff changeset
46 ; 2) At most 2 iops to the branch unit
kono
parents:
diff changeset
47 ; Note that insn position in a dispatch group of 6 insns does not infer which
kono
parents:
diff changeset
48 ; execution slice the insn is routed to. The units are used to infer the
kono
parents:
diff changeset
49 ; conflicts that exist (i.e. an 'even' requirement will preclude dispatch
kono
parents:
diff changeset
50 ; with 2 insns with 'superslice' requirement).
kono
parents:
diff changeset
51
kono
parents:
diff changeset
52 ; The xa0/xa1 units really represent the 3rd dispatch port for a superslice but
kono
parents:
diff changeset
53 ; are listed as separate units to allow those insns that preclude its use to
kono
parents:
diff changeset
54 ; still be scheduled two to a superslice while reserving the 3rd slot. The
kono
parents:
diff changeset
55 ; same applies for xb0/xb1.
kono
parents:
diff changeset
56 (define_reservation "DU_xa_power9" "xa0_power9+xa1_power9")
kono
parents:
diff changeset
57 (define_reservation "DU_xb_power9" "xb0_power9+xb1_power9")
kono
parents:
diff changeset
58
kono
parents:
diff changeset
59 ; Any execution slice dispatch
kono
parents:
diff changeset
60 (define_reservation "DU_any_power9"
kono
parents:
diff changeset
61 "x0_power9|x1_power9|DU_xa_power9|x2_power9|x3_power9|
kono
parents:
diff changeset
62 DU_xb_power9")
kono
parents:
diff changeset
63
kono
parents:
diff changeset
64 ; Even slice, actually takes even/odd slots
kono
parents:
diff changeset
65 (define_reservation "DU_even_power9" "x0_power9+x1_power9|x2_power9+x3_power9")
kono
parents:
diff changeset
66
kono
parents:
diff changeset
67 ; Slice plus 3rd slot
kono
parents:
diff changeset
68 (define_reservation "DU_slice_3_power9"
kono
parents:
diff changeset
69 "x0_power9+xa0_power9|x1_power9+xa1_power9|
kono
parents:
diff changeset
70 x2_power9+xb0_power9|x3_power9+xb1_power9")
kono
parents:
diff changeset
71
kono
parents:
diff changeset
72 ; Superslice
kono
parents:
diff changeset
73 (define_reservation "DU_super_power9"
kono
parents:
diff changeset
74 "x0_power9+x1_power9|x2_power9+x3_power9")
kono
parents:
diff changeset
75
kono
parents:
diff changeset
76 ; 2-way cracked
kono
parents:
diff changeset
77 (define_reservation "DU_C2_power9" "x0_power9+x1_power9|
kono
parents:
diff changeset
78 x1_power9+DU_xa_power9|
kono
parents:
diff changeset
79 x1_power9+x2_power9|
kono
parents:
diff changeset
80 DU_xa_power9+x2_power9|
kono
parents:
diff changeset
81 x2_power9+x3_power9|
kono
parents:
diff changeset
82 x3_power9+DU_xb_power9")
kono
parents:
diff changeset
83
kono
parents:
diff changeset
84 ; 2-way cracked plus 3rd slot
kono
parents:
diff changeset
85 (define_reservation "DU_C2_3_power9" "x0_power9+x1_power9+xa0_power9|
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
86 x1_power9+x2_power9+xa1_power9|
111
kono
parents:
diff changeset
87 x2_power9+x3_power9+xb0_power9")
kono
parents:
diff changeset
88
kono
parents:
diff changeset
89 ; 3-way cracked (consumes whole decode/dispatch cycle)
kono
parents:
diff changeset
90 (define_reservation "DU_C3_power9"
kono
parents:
diff changeset
91 "x0_power9+x1_power9+xa0_power9+xa1_power9+x2_power9+
kono
parents:
diff changeset
92 x3_power9+xb0_power9+xb1_power9+br0_power9+br1_power9")
kono
parents:
diff changeset
93
kono
parents:
diff changeset
94 ; Branch ports
kono
parents:
diff changeset
95 (define_reservation "DU_branch_power9" "br0_power9|br1_power9")
kono
parents:
diff changeset
96
kono
parents:
diff changeset
97
kono
parents:
diff changeset
98 ; Execution unit reservations
kono
parents:
diff changeset
99 (define_reservation "LSU_power9"
kono
parents:
diff changeset
100 "lsu0_power9|lsu1_power9|lsu2_power9|lsu3_power9")
kono
parents:
diff changeset
101
kono
parents:
diff changeset
102 (define_reservation "LSU_pair_power9"
kono
parents:
diff changeset
103 "lsu0_power9+lsu1_power9|lsu1_power9+lsu2_power9|
kono
parents:
diff changeset
104 lsu2_power9+lsu3_power9|lsu3_power9+lsu0_power9")
kono
parents:
diff changeset
105
kono
parents:
diff changeset
106 (define_reservation "VSU_power9"
kono
parents:
diff changeset
107 "vsu0_power9|vsu1_power9|vsu2_power9|vsu3_power9")
kono
parents:
diff changeset
108
kono
parents:
diff changeset
109 (define_reservation "VSU_super_power9"
kono
parents:
diff changeset
110 "vsu0_power9+vsu1_power9|vsu2_power9+vsu3_power9")
kono
parents:
diff changeset
111
kono
parents:
diff changeset
112 (define_reservation "VSU_PRM_power9" "prm0_power9|prm1_power9")
kono
parents:
diff changeset
113
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
114 ; Define the reservation to be used by FP div/sqrt which allows other insns
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
115 ; to be issued to the VSU, but blocks other div/sqrt for a number of cycles.
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
116 ; Note that the number of cycles blocked varies depending on insn, but we
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
117 ; just use the same number for all in order to keep the number of DFA states
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
118 ; reasonable.
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
119 (define_reservation "FP_DIV_power9"
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
120 "fp_div0_power9*8|fp_div1_power9*8|fp_div2_power9*8|
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
121 fp_div3_power9*8")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
122 (define_reservation "VEC_DIV_power9"
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
123 "fp_div0_power9*8+fp_div1_power9*8|
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
124 fp_div2_power9*8+fp_div3_power9*8")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
125
111
kono
parents:
diff changeset
126
kono
parents:
diff changeset
127 ; LS Unit
kono
parents:
diff changeset
128 (define_insn_reservation "power9-load" 4
kono
parents:
diff changeset
129 (and (eq_attr "type" "load")
kono
parents:
diff changeset
130 (eq_attr "sign_extend" "no")
kono
parents:
diff changeset
131 (eq_attr "update" "no")
kono
parents:
diff changeset
132 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
133 "DU_any_power9,LSU_power9")
kono
parents:
diff changeset
134
kono
parents:
diff changeset
135 (define_insn_reservation "power9-load-update" 4
kono
parents:
diff changeset
136 (and (eq_attr "type" "load")
kono
parents:
diff changeset
137 (eq_attr "sign_extend" "no")
kono
parents:
diff changeset
138 (eq_attr "update" "yes")
kono
parents:
diff changeset
139 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
140 "DU_C2_power9,LSU_power9+VSU_power9")
kono
parents:
diff changeset
141
kono
parents:
diff changeset
142 (define_insn_reservation "power9-load-ext" 6
kono
parents:
diff changeset
143 (and (eq_attr "type" "load")
kono
parents:
diff changeset
144 (eq_attr "sign_extend" "yes")
kono
parents:
diff changeset
145 (eq_attr "update" "no")
kono
parents:
diff changeset
146 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
147 "DU_C2_power9,LSU_power9")
kono
parents:
diff changeset
148
kono
parents:
diff changeset
149 (define_insn_reservation "power9-load-ext-update" 6
kono
parents:
diff changeset
150 (and (eq_attr "type" "load")
kono
parents:
diff changeset
151 (eq_attr "sign_extend" "yes")
kono
parents:
diff changeset
152 (eq_attr "update" "yes")
kono
parents:
diff changeset
153 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
154 "DU_C3_power9,LSU_power9+VSU_power9")
kono
parents:
diff changeset
155
kono
parents:
diff changeset
156 (define_insn_reservation "power9-fpload-double" 4
kono
parents:
diff changeset
157 (and (eq_attr "type" "fpload")
kono
parents:
diff changeset
158 (eq_attr "update" "no")
kono
parents:
diff changeset
159 (eq_attr "size" "64")
kono
parents:
diff changeset
160 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
161 "DU_slice_3_power9,LSU_power9")
kono
parents:
diff changeset
162
kono
parents:
diff changeset
163 (define_insn_reservation "power9-fpload-update-double" 4
kono
parents:
diff changeset
164 (and (eq_attr "type" "fpload")
kono
parents:
diff changeset
165 (eq_attr "update" "yes")
kono
parents:
diff changeset
166 (eq_attr "size" "64")
kono
parents:
diff changeset
167 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
168 "DU_C2_3_power9,LSU_power9+VSU_power9")
kono
parents:
diff changeset
169
kono
parents:
diff changeset
170 ; SFmode loads are cracked and have additional 2 cycles over DFmode
kono
parents:
diff changeset
171 (define_insn_reservation "power9-fpload-single" 6
kono
parents:
diff changeset
172 (and (eq_attr "type" "fpload")
kono
parents:
diff changeset
173 (eq_attr "update" "no")
kono
parents:
diff changeset
174 (eq_attr "size" "32")
kono
parents:
diff changeset
175 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
176 "DU_C2_3_power9,LSU_power9")
kono
parents:
diff changeset
177
kono
parents:
diff changeset
178 (define_insn_reservation "power9-fpload-update-single" 6
kono
parents:
diff changeset
179 (and (eq_attr "type" "fpload")
kono
parents:
diff changeset
180 (eq_attr "update" "yes")
kono
parents:
diff changeset
181 (eq_attr "size" "32")
kono
parents:
diff changeset
182 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
183 "DU_C3_power9,LSU_power9+VSU_power9")
kono
parents:
diff changeset
184
kono
parents:
diff changeset
185 (define_insn_reservation "power9-vecload" 5
kono
parents:
diff changeset
186 (and (eq_attr "type" "vecload")
kono
parents:
diff changeset
187 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
188 "DU_any_power9,LSU_pair_power9")
kono
parents:
diff changeset
189
kono
parents:
diff changeset
190 ; Store data can issue 2 cycles after AGEN issue, 3 cycles for vector store
kono
parents:
diff changeset
191 (define_insn_reservation "power9-store" 0
kono
parents:
diff changeset
192 (and (eq_attr "type" "store")
kono
parents:
diff changeset
193 (eq_attr "update" "no")
kono
parents:
diff changeset
194 (eq_attr "indexed" "no")
kono
parents:
diff changeset
195 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
196 "DU_slice_3_power9,LSU_power9")
kono
parents:
diff changeset
197
kono
parents:
diff changeset
198 (define_insn_reservation "power9-store-indexed" 0
kono
parents:
diff changeset
199 (and (eq_attr "type" "store")
kono
parents:
diff changeset
200 (eq_attr "update" "no")
kono
parents:
diff changeset
201 (eq_attr "indexed" "yes")
kono
parents:
diff changeset
202 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
203 "DU_slice_3_power9,LSU_power9")
kono
parents:
diff changeset
204
kono
parents:
diff changeset
205 ; Update forms have 2 cycle latency for updated addr reg
kono
parents:
diff changeset
206 (define_insn_reservation "power9-store-update" 2
kono
parents:
diff changeset
207 (and (eq_attr "type" "store")
kono
parents:
diff changeset
208 (eq_attr "update" "yes")
kono
parents:
diff changeset
209 (eq_attr "indexed" "no")
kono
parents:
diff changeset
210 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
211 "DU_C2_3_power9,LSU_power9+VSU_power9")
kono
parents:
diff changeset
212
kono
parents:
diff changeset
213 ; Update forms have 2 cycle latency for updated addr reg
kono
parents:
diff changeset
214 (define_insn_reservation "power9-store-update-indexed" 2
kono
parents:
diff changeset
215 (and (eq_attr "type" "store")
kono
parents:
diff changeset
216 (eq_attr "update" "yes")
kono
parents:
diff changeset
217 (eq_attr "indexed" "yes")
kono
parents:
diff changeset
218 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
219 "DU_C2_3_power9,LSU_power9+VSU_power9")
kono
parents:
diff changeset
220
kono
parents:
diff changeset
221 (define_insn_reservation "power9-fpstore" 0
kono
parents:
diff changeset
222 (and (eq_attr "type" "fpstore")
kono
parents:
diff changeset
223 (eq_attr "update" "no")
kono
parents:
diff changeset
224 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
225 "DU_slice_3_power9,LSU_power9")
kono
parents:
diff changeset
226
kono
parents:
diff changeset
227 ; Update forms have 2 cycle latency for updated addr reg
kono
parents:
diff changeset
228 (define_insn_reservation "power9-fpstore-update" 2
kono
parents:
diff changeset
229 (and (eq_attr "type" "fpstore")
kono
parents:
diff changeset
230 (eq_attr "update" "yes")
kono
parents:
diff changeset
231 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
232 "DU_C2_3_power9,LSU_power9+VSU_power9")
kono
parents:
diff changeset
233
kono
parents:
diff changeset
234 (define_insn_reservation "power9-vecstore" 0
kono
parents:
diff changeset
235 (and (eq_attr "type" "vecstore")
kono
parents:
diff changeset
236 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
237 "DU_super_power9,LSU_pair_power9")
kono
parents:
diff changeset
238
kono
parents:
diff changeset
239 (define_insn_reservation "power9-larx" 4
kono
parents:
diff changeset
240 (and (eq_attr "type" "load_l")
kono
parents:
diff changeset
241 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
242 "DU_any_power9,LSU_power9")
kono
parents:
diff changeset
243
kono
parents:
diff changeset
244 (define_insn_reservation "power9-stcx" 2
kono
parents:
diff changeset
245 (and (eq_attr "type" "store_c")
kono
parents:
diff changeset
246 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
247 "DU_C2_3_power9,LSU_power9+VSU_power9")
kono
parents:
diff changeset
248
kono
parents:
diff changeset
249 (define_insn_reservation "power9-sync" 4
kono
parents:
diff changeset
250 (and (eq_attr "type" "sync,isync")
kono
parents:
diff changeset
251 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
252 "DU_any_power9,LSU_power9")
kono
parents:
diff changeset
253
kono
parents:
diff changeset
254
kono
parents:
diff changeset
255 ; VSU Execution Unit
kono
parents:
diff changeset
256
kono
parents:
diff changeset
257 ; Fixed point ops
kono
parents:
diff changeset
258
kono
parents:
diff changeset
259 ; Most ALU insns are simple 2 cycle, including record form
kono
parents:
diff changeset
260 (define_insn_reservation "power9-alu" 2
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
261 (and (eq_attr "type" "add,exts,integer,logical,isel")
111
kono
parents:
diff changeset
262 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
263 "DU_any_power9,VSU_power9")
kono
parents:
diff changeset
264 ; 5 cycle CR latency
kono
parents:
diff changeset
265 (define_bypass 5 "power9-alu"
kono
parents:
diff changeset
266 "power9-crlogical,power9-mfcr,power9-mfcrf")
kono
parents:
diff changeset
267
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
268 ; Rotate/shift prevent use of third slot
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
269 (define_insn_reservation "power9-rot" 2
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
270 (and (eq_attr "type" "insert,shift")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
271 (eq_attr "dot" "no")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
272 (eq_attr "cpu" "power9"))
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
273 "DU_slice_3_power9,VSU_power9")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
274
111
kono
parents:
diff changeset
275 ; Record form rotate/shift are cracked
kono
parents:
diff changeset
276 (define_insn_reservation "power9-cracked-alu" 2
kono
parents:
diff changeset
277 (and (eq_attr "type" "insert,shift")
kono
parents:
diff changeset
278 (eq_attr "dot" "yes")
kono
parents:
diff changeset
279 (eq_attr "cpu" "power9"))
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
280 "DU_C2_3_power9,VSU_power9")
111
kono
parents:
diff changeset
281 ; 7 cycle CR latency
kono
parents:
diff changeset
282 (define_bypass 7 "power9-cracked-alu"
kono
parents:
diff changeset
283 "power9-crlogical,power9-mfcr,power9-mfcrf")
kono
parents:
diff changeset
284
kono
parents:
diff changeset
285 (define_insn_reservation "power9-alu2" 3
kono
parents:
diff changeset
286 (and (eq_attr "type" "cntlz,popcnt,trap")
kono
parents:
diff changeset
287 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
288 "DU_any_power9,VSU_power9")
kono
parents:
diff changeset
289 ; 6 cycle CR latency
kono
parents:
diff changeset
290 (define_bypass 6 "power9-alu2"
kono
parents:
diff changeset
291 "power9-crlogical,power9-mfcr,power9-mfcrf")
kono
parents:
diff changeset
292
kono
parents:
diff changeset
293 (define_insn_reservation "power9-cmp" 2
kono
parents:
diff changeset
294 (and (eq_attr "type" "cmp")
kono
parents:
diff changeset
295 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
296 "DU_any_power9,VSU_power9")
kono
parents:
diff changeset
297
kono
parents:
diff changeset
298
kono
parents:
diff changeset
299 ; Treat 'two' and 'three' types as 2 or 3 way cracked
kono
parents:
diff changeset
300 (define_insn_reservation "power9-two" 4
kono
parents:
diff changeset
301 (and (eq_attr "type" "two")
kono
parents:
diff changeset
302 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
303 "DU_C2_power9,VSU_power9")
kono
parents:
diff changeset
304
kono
parents:
diff changeset
305 (define_insn_reservation "power9-three" 6
kono
parents:
diff changeset
306 (and (eq_attr "type" "three")
kono
parents:
diff changeset
307 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
308 "DU_C3_power9,VSU_power9")
kono
parents:
diff changeset
309
kono
parents:
diff changeset
310 (define_insn_reservation "power9-mul" 5
kono
parents:
diff changeset
311 (and (eq_attr "type" "mul")
kono
parents:
diff changeset
312 (eq_attr "dot" "no")
kono
parents:
diff changeset
313 (eq_attr "cpu" "power9"))
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
314 "DU_slice_3_power9,VSU_power9")
111
kono
parents:
diff changeset
315
kono
parents:
diff changeset
316 (define_insn_reservation "power9-mul-compare" 5
kono
parents:
diff changeset
317 (and (eq_attr "type" "mul")
kono
parents:
diff changeset
318 (eq_attr "dot" "yes")
kono
parents:
diff changeset
319 (eq_attr "cpu" "power9"))
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
320 "DU_C2_3_power9,VSU_power9")
111
kono
parents:
diff changeset
321 ; 10 cycle CR latency
kono
parents:
diff changeset
322 (define_bypass 10 "power9-mul-compare"
kono
parents:
diff changeset
323 "power9-crlogical,power9-mfcr,power9-mfcrf")
kono
parents:
diff changeset
324
kono
parents:
diff changeset
325 ; Fixed point divides reserve the divide units for a minimum of 8 cycles
kono
parents:
diff changeset
326 (define_insn_reservation "power9-idiv" 16
kono
parents:
diff changeset
327 (and (eq_attr "type" "div")
kono
parents:
diff changeset
328 (eq_attr "size" "32")
kono
parents:
diff changeset
329 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
330 "DU_even_power9,fx_div0_power9*8|fx_div1_power9*8")
kono
parents:
diff changeset
331
kono
parents:
diff changeset
332 (define_insn_reservation "power9-ldiv" 24
kono
parents:
diff changeset
333 (and (eq_attr "type" "div")
kono
parents:
diff changeset
334 (eq_attr "size" "64")
kono
parents:
diff changeset
335 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
336 "DU_even_power9,fx_div0_power9*8|fx_div1_power9*8")
kono
parents:
diff changeset
337
kono
parents:
diff changeset
338 (define_insn_reservation "power9-crlogical" 2
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
339 (and (eq_attr "type" "cr_logical")
111
kono
parents:
diff changeset
340 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
341 "DU_any_power9,VSU_power9")
kono
parents:
diff changeset
342
kono
parents:
diff changeset
343 (define_insn_reservation "power9-mfcrf" 2
kono
parents:
diff changeset
344 (and (eq_attr "type" "mfcrf")
kono
parents:
diff changeset
345 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
346 "DU_any_power9,VSU_power9")
kono
parents:
diff changeset
347
kono
parents:
diff changeset
348 (define_insn_reservation "power9-mfcr" 6
kono
parents:
diff changeset
349 (and (eq_attr "type" "mfcr")
kono
parents:
diff changeset
350 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
351 "DU_C3_power9,VSU_power9")
kono
parents:
diff changeset
352
kono
parents:
diff changeset
353 ; Should differentiate between 1 cr field and > 1 since target of > 1 cr
kono
parents:
diff changeset
354 ; is cracked
kono
parents:
diff changeset
355 (define_insn_reservation "power9-mtcr" 2
kono
parents:
diff changeset
356 (and (eq_attr "type" "mtcr")
kono
parents:
diff changeset
357 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
358 "DU_any_power9,VSU_power9")
kono
parents:
diff changeset
359
kono
parents:
diff changeset
360 ; Move to LR/CTR are executed in VSU
kono
parents:
diff changeset
361 (define_insn_reservation "power9-mtjmpr" 5
kono
parents:
diff changeset
362 (and (eq_attr "type" "mtjmpr")
kono
parents:
diff changeset
363 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
364 "DU_any_power9,VSU_power9")
kono
parents:
diff changeset
365
kono
parents:
diff changeset
366 ; Floating point/Vector ops
kono
parents:
diff changeset
367 (define_insn_reservation "power9-fpsimple" 2
kono
parents:
diff changeset
368 (and (eq_attr "type" "fpsimple")
kono
parents:
diff changeset
369 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
370 "DU_slice_3_power9,VSU_power9")
kono
parents:
diff changeset
371
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
372 (define_insn_reservation "power9-fp" 5
111
kono
parents:
diff changeset
373 (and (eq_attr "type" "fp,dmul")
kono
parents:
diff changeset
374 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
375 "DU_slice_3_power9,VSU_power9")
kono
parents:
diff changeset
376
kono
parents:
diff changeset
377 (define_insn_reservation "power9-fpcompare" 3
kono
parents:
diff changeset
378 (and (eq_attr "type" "fpcompare")
kono
parents:
diff changeset
379 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
380 "DU_slice_3_power9,VSU_power9")
kono
parents:
diff changeset
381
kono
parents:
diff changeset
382 ; FP div/sqrt are executed in the VSU slices. They are not pipelined wrt other
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
383 ; div/sqrt insns, but for the most part do not block pipelined ops.
111
kono
parents:
diff changeset
384 (define_insn_reservation "power9-sdiv" 22
kono
parents:
diff changeset
385 (and (eq_attr "type" "sdiv")
kono
parents:
diff changeset
386 (eq_attr "cpu" "power9"))
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
387 "DU_slice_3_power9,VSU_power9,FP_DIV_power9")
111
kono
parents:
diff changeset
388
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
389 (define_insn_reservation "power9-ddiv" 27
111
kono
parents:
diff changeset
390 (and (eq_attr "type" "ddiv")
kono
parents:
diff changeset
391 (eq_attr "cpu" "power9"))
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
392 "DU_slice_3_power9,VSU_power9,FP_DIV_power9")
111
kono
parents:
diff changeset
393
kono
parents:
diff changeset
394 (define_insn_reservation "power9-sqrt" 26
kono
parents:
diff changeset
395 (and (eq_attr "type" "ssqrt")
kono
parents:
diff changeset
396 (eq_attr "cpu" "power9"))
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
397 "DU_slice_3_power9,VSU_power9,FP_DIV_power9")
111
kono
parents:
diff changeset
398
kono
parents:
diff changeset
399 (define_insn_reservation "power9-dsqrt" 36
kono
parents:
diff changeset
400 (and (eq_attr "type" "dsqrt")
kono
parents:
diff changeset
401 (eq_attr "cpu" "power9"))
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
402 "DU_slice_3_power9,VSU_power9,FP_DIV_power9")
111
kono
parents:
diff changeset
403
kono
parents:
diff changeset
404 (define_insn_reservation "power9-vec-2cyc" 2
kono
parents:
diff changeset
405 (and (eq_attr "type" "vecmove,veclogical,vecexts,veccmpfx")
kono
parents:
diff changeset
406 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
407 "DU_super_power9,VSU_super_power9")
kono
parents:
diff changeset
408
kono
parents:
diff changeset
409 (define_insn_reservation "power9-veccmp" 3
kono
parents:
diff changeset
410 (and (eq_attr "type" "veccmp")
kono
parents:
diff changeset
411 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
412 "DU_super_power9,VSU_super_power9")
kono
parents:
diff changeset
413
kono
parents:
diff changeset
414 (define_insn_reservation "power9-vecsimple" 3
kono
parents:
diff changeset
415 (and (eq_attr "type" "vecsimple")
kono
parents:
diff changeset
416 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
417 "DU_super_power9,VSU_super_power9")
kono
parents:
diff changeset
418
kono
parents:
diff changeset
419 (define_insn_reservation "power9-vecnormal" 7
kono
parents:
diff changeset
420 (and (eq_attr "type" "vecfloat,vecdouble")
kono
parents:
diff changeset
421 (eq_attr "size" "!128")
kono
parents:
diff changeset
422 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
423 "DU_super_power9,VSU_super_power9")
kono
parents:
diff changeset
424
kono
parents:
diff changeset
425 ; Quad-precision FP ops, execute in DFU
kono
parents:
diff changeset
426 (define_insn_reservation "power9-qp" 12
kono
parents:
diff changeset
427 (and (eq_attr "type" "vecfloat,vecdouble")
kono
parents:
diff changeset
428 (eq_attr "size" "128")
kono
parents:
diff changeset
429 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
430 "DU_super_power9,dfu_power9")
kono
parents:
diff changeset
431
kono
parents:
diff changeset
432 (define_insn_reservation "power9-vecperm" 3
kono
parents:
diff changeset
433 (and (eq_attr "type" "vecperm")
kono
parents:
diff changeset
434 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
435 "DU_super_power9,VSU_PRM_power9")
kono
parents:
diff changeset
436
kono
parents:
diff changeset
437 (define_insn_reservation "power9-veccomplex" 7
kono
parents:
diff changeset
438 (and (eq_attr "type" "veccomplex")
kono
parents:
diff changeset
439 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
440 "DU_super_power9,VSU_super_power9")
kono
parents:
diff changeset
441
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
442 (define_insn_reservation "power9-vecfdiv" 24
111
kono
parents:
diff changeset
443 (and (eq_attr "type" "vecfdiv")
kono
parents:
diff changeset
444 (eq_attr "cpu" "power9"))
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
445 "DU_super_power9,VSU_super_power9,VEC_DIV_power9")
111
kono
parents:
diff changeset
446
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
447 (define_insn_reservation "power9-vecdiv" 27
111
kono
parents:
diff changeset
448 (and (eq_attr "type" "vecdiv")
kono
parents:
diff changeset
449 (eq_attr "size" "!128")
kono
parents:
diff changeset
450 (eq_attr "cpu" "power9"))
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
451 "DU_super_power9,VSU_super_power9,VEC_DIV_power9")
111
kono
parents:
diff changeset
452
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
453 ; Use 8 for DFU reservation on QP div/mul to limit DFA state size
111
kono
parents:
diff changeset
454 (define_insn_reservation "power9-qpdiv" 56
kono
parents:
diff changeset
455 (and (eq_attr "type" "vecdiv")
kono
parents:
diff changeset
456 (eq_attr "size" "128")
kono
parents:
diff changeset
457 (eq_attr "cpu" "power9"))
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
458 "DU_super_power9,dfu_power9*8")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
459
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
460 (define_insn_reservation "power9-qpmul" 24
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
461 (and (eq_attr "type" "qmul")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
462 (eq_attr "size" "128")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
463 (eq_attr "cpu" "power9"))
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
464 "DU_super_power9,dfu_power9*8")
111
kono
parents:
diff changeset
465
kono
parents:
diff changeset
466 (define_insn_reservation "power9-mffgpr" 2
kono
parents:
diff changeset
467 (and (eq_attr "type" "mffgpr")
kono
parents:
diff changeset
468 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
469 "DU_slice_3_power9,VSU_power9")
kono
parents:
diff changeset
470
kono
parents:
diff changeset
471 (define_insn_reservation "power9-mftgpr" 2
kono
parents:
diff changeset
472 (and (eq_attr "type" "mftgpr")
kono
parents:
diff changeset
473 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
474 "DU_slice_3_power9,VSU_power9")
kono
parents:
diff changeset
475
kono
parents:
diff changeset
476
kono
parents:
diff changeset
477 ; Branch Unit
kono
parents:
diff changeset
478 ; Move from LR/CTR are executed in BRU but consume a writeback port from an
kono
parents:
diff changeset
479 ; execution slice.
kono
parents:
diff changeset
480 (define_insn_reservation "power9-mfjmpr" 6
kono
parents:
diff changeset
481 (and (eq_attr "type" "mfjmpr")
kono
parents:
diff changeset
482 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
483 "DU_branch_power9,bru_power9+VSU_power9")
kono
parents:
diff changeset
484
kono
parents:
diff changeset
485 ; Branch is 2 cycles
kono
parents:
diff changeset
486 (define_insn_reservation "power9-branch" 2
kono
parents:
diff changeset
487 (and (eq_attr "type" "jmpreg,branch")
kono
parents:
diff changeset
488 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
489 "DU_branch_power9,bru_power9")
kono
parents:
diff changeset
490
kono
parents:
diff changeset
491
kono
parents:
diff changeset
492 ; Crypto Unit
kono
parents:
diff changeset
493 (define_insn_reservation "power9-crypto" 6
kono
parents:
diff changeset
494 (and (eq_attr "type" "crypto")
kono
parents:
diff changeset
495 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
496 "DU_super_power9,cryptu_power9")
kono
parents:
diff changeset
497
kono
parents:
diff changeset
498
kono
parents:
diff changeset
499 ; HTM Unit
kono
parents:
diff changeset
500 (define_insn_reservation "power9-htm" 4
kono
parents:
diff changeset
501 (and (eq_attr "type" "htm")
kono
parents:
diff changeset
502 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
503 "DU_C2_power9,LSU_power9")
kono
parents:
diff changeset
504
kono
parents:
diff changeset
505 (define_insn_reservation "power9-htm-simple" 2
kono
parents:
diff changeset
506 (and (eq_attr "type" "htmsimple")
kono
parents:
diff changeset
507 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
508 "DU_any_power9,VSU_power9")
kono
parents:
diff changeset
509
kono
parents:
diff changeset
510
kono
parents:
diff changeset
511 ; DFP Unit
kono
parents:
diff changeset
512 (define_insn_reservation "power9-dfp" 12
kono
parents:
diff changeset
513 (and (eq_attr "type" "dfp")
kono
parents:
diff changeset
514 (eq_attr "cpu" "power9"))
kono
parents:
diff changeset
515 "DU_even_power9,dfu_power9")
kono
parents:
diff changeset
516