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1 ;; DFA scheduling description for ST40-300.
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2 ;; Copyright (C) 2004-2018 Free Software Foundation, Inc.
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3
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4 ;; This file is part of GCC.
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5
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; Load and store instructions save a cycle if they are aligned on a
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21 ;; four byte boundary. Using a function unit for stores encourages
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22 ;; gcc to separate load and store instructions by one instruction,
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23 ;; which makes it more likely that the linker will be able to word
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24 ;; align them when relaxing.
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25
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26 ;; The following description models the ST40-300 pipeline using the DFA based
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27 ;; scheduler.
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28
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29 ;; Two automata are defined to reduce number of states
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30 ;; which a single large automaton will have. (Factoring)
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31
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32 (define_automaton "sh4_300_inst_pipeline,sh4_300_fpu_pipe")
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33
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34 ;; This unit is basically the decode unit of the processor.
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35 ;; Since SH4 is a dual issue machine,it is as if there are two
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36 ;; units so that any insn can be processed by either one
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37 ;; of the decoding unit.
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38 (define_cpu_unit "sh4_300_pipe_01,sh4_300_pipe_02" "sh4_300_inst_pipeline")
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39
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40 ;; The floating point units.
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41 (define_cpu_unit "sh4_300_fpt,sh4_300_fpu,sh4_300_fds" "sh4_300_fpu_pipe")
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42
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43 ;; integer multiplier unit
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44 (define_cpu_unit "sh4_300_mul" "sh4_300_inst_pipeline")
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45
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46 ;; LS unit
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47 (define_cpu_unit "sh4_300_ls" "sh4_300_inst_pipeline")
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48
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49 ;; The address calculator used for branch instructions.
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50 ;; This will be reserved after "issue" of branch instructions
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51 ;; and this is to make sure that no two branch instructions
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52 ;; can be issued in parallel.
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53 (define_cpu_unit "sh4_300_br" "sh4_300_inst_pipeline")
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54
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55 ;; ----------------------------------------------------
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56 ;; This reservation is to simplify the dual issue description.
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57
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58 (define_reservation "sh4_300_issue" "sh4_300_pipe_01|sh4_300_pipe_02")
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59
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60 (define_reservation "all" "sh4_300_pipe_01+sh4_300_pipe_02")
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61
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62 ;;(define_insn_reservation "nil" 0 (eq_attr "type" "nil") "nothing")
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63
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64 ;; MOV RM,RN / MOV #imm8,RN / STS PR,RN
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65 (define_insn_reservation "sh4_300_mov" 0
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66 (and (eq_attr "pipe_model" "sh4_300")
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67 (eq_attr "type" "move,movi8,prget"))
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68 "sh4_300_issue")
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69
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70 ;; Fixed STS from MACL / MACH
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71 (define_insn_reservation "sh4_300_mac_gp" 0
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72 (and (eq_attr "pipe_model" "sh4_300")
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73 (eq_attr "type" "mac_gp"))
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74 "sh4_300_issue+sh4_300_mul")
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75
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76 ;; Fixed LDS to MACL / MACH
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77 (define_insn_reservation "sh4_300_gp_mac" 1
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78 (and (eq_attr "pipe_model" "sh4_300")
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79 (eq_attr "type" "gp_mac"))
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80 "sh4_300_issue+sh4_300_mul")
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81
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82 ;; Instructions without specific resource requirements with latency 1.
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83 (define_insn_reservation "sh4_300_simple_arith" 1
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84 (and (eq_attr "pipe_model" "sh4_300")
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85 (eq_attr "type" "mt_group,arith,dyn_shift,prset"))
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86 "sh4_300_issue")
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87
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88 ;; Load and store instructions have no alignment peculiarities for the ST40-300,
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89 ;; but they use the load-store unit, which they share with the fmove type
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90 ;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
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91 ;; Loads have a latency of three.
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92
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93 ;; Load Store instructions.
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94 (define_insn_reservation "sh4_300_load" 3
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95 (and (eq_attr "pipe_model" "sh4_300")
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96 (eq_attr "type" "load,pcload,load_si,pcload_si,pload"))
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97 "sh4_300_issue+sh4_300_ls")
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98
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99 (define_insn_reservation "sh4_300_mac_load" 3
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100 (and (eq_attr "pipe_model" "sh4_300")
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101 (eq_attr "type" "mem_mac"))
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102 "sh4_300_issue+sh4_300_ls+sh4_300_mul")
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103
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104 (define_insn_reservation "sh4_300_fload" 4
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105 (and (eq_attr "pipe_model" "sh4_300")
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106 (eq_attr "type" "fload,pcfload"))
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107 "sh4_300_issue+sh4_300_ls+sh4_300_fpt")
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108
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109 ;; sh_adjust_cost describes the reduced latency of the feeding insns of a store.
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110 ;; The latency of an auto-increment register is 1; the latency of the memory
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111 ;; output is not actually considered here anyway.
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112 (define_insn_reservation "sh4_300_store" 1
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113 (and (eq_attr "pipe_model" "sh4_300")
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114 (eq_attr "type" "store,pstore"))
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115 "sh4_300_issue+sh4_300_ls")
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116
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117 (define_insn_reservation "sh4_300_fstore" 1
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118 (and (eq_attr "pipe_model" "sh4_300")
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119 (eq_attr "type" "fstore"))
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120 "sh4_300_issue+sh4_300_ls+sh4_300_fpt")
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121
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122 ;; Fixed STS.L from MACL / MACH
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123 (define_insn_reservation "sh4_300_mac_store" 1
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124 (and (eq_attr "pipe_model" "sh4_300")
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125 (eq_attr "type" "mac_mem"))
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126 "sh4_300_issue+sh4_300_mul+sh4_300_ls")
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127
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128 (define_insn_reservation "sh4_300_gp_fpul" 2
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129 (and (eq_attr "pipe_model" "sh4_300")
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130 (eq_attr "type" "gp_fpul"))
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131 "sh4_300_issue+sh4_300_fpt")
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132
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133 (define_insn_reservation "sh4_300_fpul_gp" 1
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134 (and (eq_attr "pipe_model" "sh4_300")
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135 (eq_attr "type" "fpul_gp"))
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136 "sh4_300_issue+sh4_300_fpt")
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137
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138 ;; Branch (BF,BF/S,BT,BT/S,BRA)
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139 ;; Branch Far (JMP,RTS,BRAF)
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140 ;; Group: BR
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141 ;; When displacement is 0 for BF / BT, we have effectively conditional
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142 ;; execution of one instruction, without pipeline disruption.
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143 ;; Otherwise, the latency depends on prediction success.
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144 ;; We can't really do much with the latency, even if we could express it,
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145 ;; but the pairing restrictions are useful to take into account.
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146 ;; ??? If the branch is likely, and not paired with a preceding insn,
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147 ;; or likely and likely not predicted, we might want to fill the delay slot.
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148 ;; However, there appears to be no machinery to make the compiler
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149 ;; recognize these scenarios.
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150 (define_insn_reservation "sh4_300_branch" 1
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151 (and (eq_attr "pipe_model" "sh4_300")
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152 (eq_attr "type" "cbranch,jump,return,jump_ind"))
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153 "sh4_300_issue+sh4_300_br")
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154
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155 ;; RTE
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156 (define_insn_reservation "sh4_300_return_from_exp" 9
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157 (and (eq_attr "pipe_model" "sh4_300")
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158 (eq_attr "type" "rte"))
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159 "sh4_300_pipe_01+sh4_300_pipe_02*9")
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160
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161 ;; OCBP, OCBWB
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162 ;; Group: CO
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163 ;; Latency: 1-5
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164 ;; Issue Rate: 1
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111
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165 ;; cwb is used for the sequence
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166 ;; ocbwb @%0
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167 ;; extu.w %0,%2
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168 ;; or %1,%2
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169 ;; mov.l %0,@%2
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170 ;; This description is likely inexact, but this pattern should not actually
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171 ;; appear when compiling for sh4-300; we should use isbi instead.
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172 ;; If a -mtune option is added later, we should use the icache array
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173 ;; dispatch method instead.
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174 (define_insn_reservation "sh4_300_ocbwb" 3
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175 (and (eq_attr "pipe_model" "sh4_300")
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176 (eq_attr "type" "cwb"))
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177 "all*3")
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178
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179 ;; JSR,BSR,BSRF
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180 ;; Calls have a mandatory delay slot, which we'd like to fill with an insn
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181 ;; that can be paired with the call itself.
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182 ;; Scheduling runs before reorg, so we approximate this by saying that we
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183 ;; want the call to be paired with a preceding insn.
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184 ;; In most cases, the insn that loads the address of the call should have
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185 ;; a nonzero latency (mov rn,rm doesn't make sense since we could use rn
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186 ;; for the address then). Thus, a preceding insn that can be paired with
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187 ;; a call should be eligible for the delay slot.
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188 ;;
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189 ;; calls introduce a longisch delay that is likely to flush the pipelines
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190 ;; of the caller's instructions. Ordinary functions tend to end with a
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191 ;; load to restore a register (in the delay slot of rts), while sfuncs
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192 ;; tend to end with an EX or MT insn. But that is not actually relevant,
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193 ;; since there are no instructions that contend for memory access early.
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194 ;; We could, of course, provide exact scheduling information for specific
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195 ;; sfuncs, if that should prove useful.
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196 (define_insn_reservation "sh4_300_call" 16
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197 (and (eq_attr "pipe_model" "sh4_300")
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198 (eq_attr "type" "call,sfunc"))
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199 "sh4_300_issue+sh4_300_br,all*15")
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200
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201 ;; FMOV.S / FMOV.D
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202 (define_insn_reservation "sh4_300_fmov" 1
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203 (and (eq_attr "pipe_model" "sh4_300")
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204 (eq_attr "type" "fmove"))
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205 "sh4_300_issue+sh4_300_fpt")
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206
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207 ;; LDS to FPSCR
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208 (define_insn_reservation "sh4_300_fpscr_load" 8
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209 (and (eq_attr "pipe_model" "sh4_300")
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210 (eq_attr "type" "gp_fpscr"))
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211 "sh4_300_issue+sh4_300_fpu+sh4_300_fpt")
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212
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213 ;; LDS.L to FPSCR
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214 (define_insn_reservation "sh4_300_fpscr_load_mem" 8
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215 (and (eq_attr "pipe_model" "sh4_300")
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216 (eq_attr "type" "mem_fpscr"))
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217 "sh4_300_issue+sh4_300_fpu+sh4_300_fpt+sh4_300_ls")
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218
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219
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220 ;; Fixed point multiplication (DMULS.L DMULU.L MUL.L MULS.W,MULU.W)
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221 (define_insn_reservation "multi" 2
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222 (and (eq_attr "pipe_model" "sh4_300")
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223 (eq_attr "type" "smpy,dmpy"))
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224 "sh4_300_issue+sh4_300_mul")
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225
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226 ;; FPCHG, FRCHG, FSCHG
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227 (define_insn_reservation "fpscr_toggle" 1
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228 (and (eq_attr "pipe_model" "sh4_300")
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229 (eq_attr "type" "fpscr_toggle"))
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230 "sh4_300_issue+sh4_300_fpu+sh4_300_fpt")
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231
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232 ;; FCMP/EQ, FCMP/GT
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233 (define_insn_reservation "fp_cmp" 3
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234 (and (eq_attr "pipe_model" "sh4_300")
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235 (eq_attr "type" "fp_cmp,dfp_cmp"))
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236 "sh4_300_issue+sh4_300_fpu")
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237
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238 ;; Single precision floating point (FADD,FLOAT,FMAC,FMUL,FSUB,FTRC)
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239 ;; Double-precision floating-point (FADD,FCNVDS,FCNVSD,FLOAT,FSUB,FTRC)
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240 (define_insn_reservation "fp_arith" 6
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241 (and (eq_attr "pipe_model" "sh4_300")
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242 (eq_attr "type" "fp,ftrc_s,dfp_arith,dfp_conv"))
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243 "sh4_300_issue+sh4_300_fpu")
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244
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245 ;; Single Precision FDIV/SQRT
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246 (define_insn_reservation "fp_div" 19
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247 (and (eq_attr "pipe_model" "sh4_300")
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248 (eq_attr "type" "fdiv"))
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249 "sh4_300_issue+sh4_300_fpu+sh4_300_fds,sh4_300_fds*15")
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250
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251 ;; Double-precision floating-point FMUL
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252 (define_insn_reservation "dfp_mul" 9
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253 (and (eq_attr "pipe_model" "sh4_300")
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254 (eq_attr "type" "dfp_mul"))
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255 "sh4_300_issue+sh4_300_fpu,sh4_300_fpu*3")
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256
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257 ;; Double precision FDIV/SQRT
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258 (define_insn_reservation "dp_div" 35
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259 (and (eq_attr "pipe_model" "sh4_300")
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260 (eq_attr "type" "dfdiv"))
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261 "sh4_300_issue+sh4_300_fpu+sh4_300_fds,sh4_300_fds*31")
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262
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263 ;; ??? We don't really want these for sh4-300.
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264 ;; this pattern itself is likely to finish in 3 cycles, but also
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265 ;; to disrupt branch prediction for taken branches for the following
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266 ;; condbranch.
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267 (define_insn_reservation "sh4_300_arith3" 5
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268 (and (eq_attr "pipe_model" "sh4_300")
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269 (eq_attr "type" "arith3"))
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270 "sh4_300_issue,all*4")
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271
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272 ;; arith3b insns without brach redirection make use of the 0-offset 0-latency
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273 ;; branch feature, and thus schedule the same no matter if the branch is taken
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274 ;; or not. If the branch is redirected, the taken branch might take longer,
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275 ;; but then, we don't have to take the next branch.
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276 ;; ??? should we suppress branch redirection for sh4-300 to improve branch
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277 ;; target hit rates?
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278 (define_insn_reservation "arith3b" 2
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279 (and (eq_attr "pipe_model" "sh4")
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280 (eq_attr "type" "arith3"))
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281 "issue,all")
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