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annotate gcc/testsuite/g++.target/aarch64/sve/catch_5.C @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
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131
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1 /* { dg-do run { target aarch64_sve_hw } } */
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2 /* { dg-options "-O3 -fopenmp-simd -fno-omit-frame-pointer" } */
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3
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4 /* Invoke X (P##n) for n in [0, 7]. */
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5 #define REPEAT8(X, P) \
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6 X (P##0) X (P##1) X (P##2) X (P##3) X (P##4) X (P##5) X (P##6) X (P##7)
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7
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8 /* Invoke X (n) for all octal n in [0, 39]. */
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9 #define REPEAT40(X) \
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10 REPEAT8 (X, 0) REPEAT8 (X, 1) REPEAT8 (X, 2) REPEAT8 (X, 3) REPEAT8 (X, 4)
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11
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12 volatile int testi, sink;
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13 volatile void *ptr;
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14
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15 /* Take 2 stack arguments and throw to f3. */
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16 void __attribute__ ((weak))
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17 f1 (int x[40][100], int *y, int z1, int z2, int z3, int z4,
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18 int z5, int z6, int z7, int z8)
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19 {
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20 /* A wild write to x and y. */
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21 sink = z1;
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22 sink = z2;
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23 sink = z3;
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24 sink = z4;
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25 sink = z5;
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26 sink = z6;
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27 sink = z7;
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28 sink = z8;
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29 asm volatile ("" ::: "memory");
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30 if (y[testi] == x[testi][testi])
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31 throw 100;
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32 }
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33
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34 /* Expect vector work to be done, with spilling of vector registers. */
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35 void __attribute__ ((weak))
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36 f2 (int x[40][100], int *y)
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37 {
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38 /* Create a true variable-sized frame. */
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39 ptr = __builtin_alloca (testi + 40);
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40 /* Try to force some spilling. */
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41 #define DECLARE(N) int y##N = y[N];
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42 REPEAT40 (DECLARE);
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43 for (int j = 0; j < 20; ++j)
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44 {
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45 f1 (x, y, 1, 2, 3, 4, 5, 6, 7, 8);
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46 #pragma omp simd
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47 for (int i = 0; i < 100; ++i)
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48 {
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49 #define INC(N) x[N][i] += y##N;
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50 REPEAT40 (INC);
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51 }
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52 }
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53 }
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54
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55 /* Catch an exception thrown from f1, via f2. */
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56 void __attribute__ ((weak))
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57 f3 (int x[40][100], int *y, int *z)
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58 {
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59 volatile int extra = 111;
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60 try
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61 {
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62 f2 (x, y);
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63 }
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64 catch (int val)
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65 {
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66 *z = val + extra;
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67 }
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68 }
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69
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70 static int x[40][100];
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71 static int y[40];
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72 static int z;
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73
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74 int
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75 main (void)
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76 {
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77 f3 (x, y, &z);
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78 if (z != 211)
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79 __builtin_abort ();
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80 return 0;
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81 }