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1 ; Options for the IA-32 and AMD64 ports of the compiler.
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2
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3 ; Copyright (C) 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
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4 ;
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5 ; This file is part of GCC.
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6 ;
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7 ; GCC is free software; you can redistribute it and/or modify it under
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8 ; the terms of the GNU General Public License as published by the Free
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9 ; Software Foundation; either version 3, or (at your option) any later
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10 ; version.
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11 ;
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12 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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13 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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14 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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15 ; for more details.
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16 ;
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17 ; You should have received a copy of the GNU General Public License
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18 ; along with GCC; see the file COPYING3. If not see
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19 ; <http://www.gnu.org/licenses/>.
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20
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21 ;; Definitions to add to the cl_target_option structure
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22 ;; -march= processor
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23 TargetSave
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24 unsigned char arch
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25
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26 ;; -mtune= processor
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27 TargetSave
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28 unsigned char tune
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29
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30 ;; -mfpath=
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31 TargetSave
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32 unsigned char fpmath
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33
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34 ;; CPU schedule model
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35 TargetSave
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36 unsigned char schedule
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37
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38 ;; branch cost
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39 TargetSave
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40 unsigned char branch_cost
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41
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42 ;; which flags were passed by the user
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43 TargetSave
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44 int ix86_isa_flags_explicit
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45
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46 ;; which flags were passed by the user
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47 TargetSave
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48 int target_flags_explicit
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49
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50 ;; whether -mtune was not specified
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51 TargetSave
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52 unsigned char tune_defaulted
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53
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54 ;; whether -march was specified
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55 TargetSave
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56 unsigned char arch_specified
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57
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58 ;; x86 options
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59 m128bit-long-double
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60 Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
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61 sizeof(long double) is 16
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62
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63 m80387
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64 Target Report Mask(80387) Save
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65 Use hardware fp
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66
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67 m96bit-long-double
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68 Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save
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69 sizeof(long double) is 12
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70
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71 maccumulate-outgoing-args
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72 Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save
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73 Reserve space for outgoing arguments in the function prologue
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74
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75 malign-double
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76 Target Report Mask(ALIGN_DOUBLE) Save
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77 Align some doubles on dword boundary
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78
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79 malign-functions=
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80 Target RejectNegative Joined Var(ix86_align_funcs_string)
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81 Function starts are aligned to this power of 2
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82
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83 malign-jumps=
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84 Target RejectNegative Joined Var(ix86_align_jumps_string)
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85 Jump targets are aligned to this power of 2
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86
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87 malign-loops=
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88 Target RejectNegative Joined Var(ix86_align_loops_string)
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89 Loop code aligned to this power of 2
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90
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91 malign-stringops
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92 Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save
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93 Align destination of the string operations
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94
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95 march=
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96 Target RejectNegative Joined Var(ix86_arch_string)
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97 Generate code for given CPU
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98
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99 masm=
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100 Target RejectNegative Joined Var(ix86_asm_string)
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101 Use given assembler dialect
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102
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103 mbranch-cost=
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104 Target RejectNegative Joined Var(ix86_branch_cost_string)
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105 Branches are this expensive (1-5, arbitrary units)
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106
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107 mlarge-data-threshold=
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108 Target RejectNegative Joined Var(ix86_section_threshold_string)
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109 Data greater than given threshold will go into .ldata section in x86-64 medium model
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110
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111 mcmodel=
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112 Target RejectNegative Joined Var(ix86_cmodel_string)
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113 Use given x86-64 code model
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114
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115 mfancy-math-387
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116 Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save
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117 Generate sin, cos, sqrt for FPU
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118
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119 mforce-drap
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120 Target Report Var(ix86_force_drap)
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121 Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack
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122
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123 mfp-ret-in-387
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124 Target Report Mask(FLOAT_RETURNS) Save
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125 Return values of functions in FPU registers
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126
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127 mfpmath=
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128 Target RejectNegative Joined Var(ix86_fpmath_string)
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129 Generate floating point mathematics using given instruction set
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130
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131 mhard-float
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132 Target RejectNegative Mask(80387) MaskExists Save
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133 Use hardware fp
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134
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135 mieee-fp
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136 Target Report Mask(IEEE_FP) Save
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137 Use IEEE math for fp comparisons
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138
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139 minline-all-stringops
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140 Target Report Mask(INLINE_ALL_STRINGOPS) Save
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141 Inline all known string operations
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142
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143 minline-stringops-dynamically
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144 Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save
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145 Inline memset/memcpy string operations, but perform inline version only for small blocks
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146
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147 mintel-syntax
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148 Target Undocumented
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149 ;; Deprecated
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150
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151 mms-bitfields
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152 Target Report Mask(MS_BITFIELD_LAYOUT) Save
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153 Use native (MS) bitfield layout
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154
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155 mno-align-stringops
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156 Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save
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157
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158 mno-fancy-math-387
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159 Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save
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160
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161 mno-push-args
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162 Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save
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163
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164 mno-red-zone
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165 Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save
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166
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167 momit-leaf-frame-pointer
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168 Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save
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169 Omit the frame pointer in leaf functions
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170
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171 mpc
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172 Target RejectNegative Report Joined Var(ix87_precision_string)
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173 Set 80387 floating-point precision (-mpc32, -mpc64, -mpc80)
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174
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175 mpreferred-stack-boundary=
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176 Target RejectNegative Joined Var(ix86_preferred_stack_boundary_string)
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177 Attempt to keep stack aligned to this power of 2
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178
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179 mincoming-stack-boundary=
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180 Target RejectNegative Joined Var(ix86_incoming_stack_boundary_string)
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181 Assume incoming stack aligned to this power of 2
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182
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183 mpush-args
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184 Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save
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185 Use push instructions to save outgoing arguments
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186
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187 mred-zone
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188 Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save
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189 Use red-zone in the x86-64 code
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190
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191 mregparm=
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192 Target RejectNegative Joined Var(ix86_regparm_string)
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193 Number of registers used to pass integer arguments
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194
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195 mrtd
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196 Target Report Mask(RTD) Save
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197 Alternate calling convention
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198
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199 msoft-float
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200 Target InverseMask(80387) Save
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201 Do not use hardware fp
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202
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203 msseregparm
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204 Target RejectNegative Mask(SSEREGPARM) Save
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205 Use SSE register passing conventions for SF and DF mode
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206
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207 mstackrealign
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208 Target Report Var(ix86_force_align_arg_pointer) Init(-1)
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209 Realign stack in prologue
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210
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211 mstack-arg-probe
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212 Target Report Mask(STACK_PROBE) Save
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213 Enable stack probing
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214
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215 mstringop-strategy=
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216 Target RejectNegative Joined Var(ix86_stringop_string)
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217 Chose strategy to generate stringop using
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218
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219 mtls-dialect=
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220 Target RejectNegative Joined Var(ix86_tls_dialect_string)
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221 Use given thread-local storage dialect
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222
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223 mtls-direct-seg-refs
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224 Target Report Mask(TLS_DIRECT_SEG_REFS)
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225 Use direct references against %gs when accessing tls data
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226
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227 mtune=
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228 Target RejectNegative Joined Var(ix86_tune_string)
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229 Schedule code for given CPU
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230
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231 mveclibabi=
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232 Target RejectNegative Joined Var(ix86_veclibabi_string)
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233 Vector library ABI to use
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234
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235 mrecip
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236 Target Report Mask(RECIP) Save
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237 Generate reciprocals instead of divss and sqrtss.
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238
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239 mcld
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240 Target Report Mask(CLD) Save
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241 Generate cld instruction in the function prologue.
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242
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243 mno-fused-madd
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244 Target RejectNegative Report Mask(NO_FUSED_MADD) Undocumented Save
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245
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246 mfused-madd
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247 Target Report InverseMask(NO_FUSED_MADD, FUSED_MADD) Save
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248 Enable automatic generation of fused floating point multiply-add instructions
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249 if the ISA supports such instructions. The -mfused-madd option is on by
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250 default.
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251
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252 ;; ISA support
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253
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254 m32
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255 Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) VarExists Save
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256 Generate 32bit i386 code
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257
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258 m64
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259 Target RejectNegative Negative(m32) Report Mask(ISA_64BIT) Var(ix86_isa_flags) VarExists Save
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260 Generate 64bit x86-64 code
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261
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262 mmmx
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263 Target Report Mask(ISA_MMX) Var(ix86_isa_flags) VarExists Save
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264 Support MMX built-in functions
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265
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266 m3dnow
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267 Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) VarExists Save
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268 Support 3DNow! built-in functions
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269
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270 m3dnowa
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271 Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) VarExists Save
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272 Support Athlon 3Dnow! built-in functions
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273
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274 msse
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275 Target Report Mask(ISA_SSE) Var(ix86_isa_flags) VarExists Save
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276 Support MMX and SSE built-in functions and code generation
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277
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278 msse2
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279 Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) VarExists Save
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280 Support MMX, SSE and SSE2 built-in functions and code generation
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281
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282 msse3
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283 Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) VarExists Save
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284 Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
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285
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286 mssse3
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287 Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) VarExists Save
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288 Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
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289
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290 msse4.1
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291 Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) VarExists Save
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292 Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation
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293
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294 msse4.2
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295 Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) VarExists Save
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296 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
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297
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298 msse4
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299 Target RejectNegative Report Mask(ISA_SSE4_2) MaskExists Var(ix86_isa_flags) VarExists Save
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300 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
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301
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302 mno-sse4
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303 Target RejectNegative Report InverseMask(ISA_SSE4_1) MaskExists Var(ix86_isa_flags) VarExists Save
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304 Do not support SSE4.1 and SSE4.2 built-in functions and code generation
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305
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306 mavx
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307 Target Report Mask(ISA_AVX) Var(ix86_isa_flags) VarExists
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308 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation
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309
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310 mfma
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311 Target Report Mask(ISA_FMA) Var(ix86_isa_flags) VarExists
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312 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation
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313
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314 msse4a
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315 Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) VarExists Save
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316 Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
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317
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318 msse5
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319 Target Report Mask(ISA_SSE5) Var(ix86_isa_flags) VarExists Save
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320 Support SSE5 built-in functions and code generation
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321
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322 mabm
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323 Target Report Mask(ISA_ABM) Var(ix86_isa_flags) VarExists Save
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324 Support code generation of Advanced Bit Manipulation (ABM) instructions.
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325
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326 mpopcnt
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327 Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) VarExists Save
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328 Support code generation of popcnt instruction.
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329
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330 mcx16
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331 Target Report Mask(ISA_CX16) Var(ix86_isa_flags) VarExists Save
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332 Support code generation of cmpxchg16b instruction.
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333
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334 msahf
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335 Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) VarExists Save
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336 Support code generation of sahf instruction in 64bit x86-64 code.
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337
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338 maes
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339 Target Report Mask(ISA_AES) Var(ix86_isa_flags) VarExists Save
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340 Support AES built-in functions and code generation
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341
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342 mpclmul
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343 Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) VarExists Save
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344 Support PCLMUL built-in functions and code generation
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345
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346 msse2avx
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347 Target Report Var(ix86_sse2avx)
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348 Encode SSE instructions with VEX prefix
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