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1 /* Definitions of target machine GNU compiler. IA-64 version.
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2 Copyright (C) 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
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3 Contributed by James E. Wilson <wilson@cygnus.com> and
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4 David Mosberger <davidm@hpl.hp.com>.
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5
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6 This file is part of GCC.
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7
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8 GCC is free software; you can redistribute it and/or modify
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9 it under the terms of the GNU General Public License as published by
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10 the Free Software Foundation; either version 3, or (at your option)
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11 any later version.
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12
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13 GCC is distributed in the hope that it will be useful,
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14 but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 GNU General Public License for more details.
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17
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18 You should have received a copy of the GNU General Public License
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19 along with GCC; see the file COPYING3. If not see
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20 <http://www.gnu.org/licenses/>. */
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21
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22 /* IA64 requires both XF and TF modes.
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23 XFmode is __float80 is IEEE extended; TFmode is __float128
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24 is IEEE quad. Both these modes occupy 16 bytes, but XFmode
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25 only has 80 significant bits. RFmode is __fpreg is IA64 internal
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26 register format with 82 significant bits but otherwise handled like
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27 XFmode. */
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28
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29 FRACTIONAL_FLOAT_MODE (XF, 80, 16, ieee_extended_intel_128_format);
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30 FRACTIONAL_FLOAT_MODE (RF, 82, 16, ieee_extended_intel_128_format);
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31 FLOAT_MODE (TF, 16, ieee_quad_format);
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32
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33 /* The above produces:
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34
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35 mode ILP32 size/align LP64 size/align
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36 XF 16/16 16/16
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37 TF 16/16 16/16
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38
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39 psABI expectations:
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40
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41 mode ILP32 size/align LP64 size/align
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42 XF 12/4 -
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43 TF - -
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44
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45 HPUX expectations:
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46
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47 mode ILP32 size/align LP64 size/align
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48 XF - -
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49 TF 16/8 -
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50
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51 We fix this up here. */
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52
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53 ADJUST_FLOAT_FORMAT (XF, (TARGET_ILP32 && !TARGET_HPUX)
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54 ? &ieee_extended_intel_96_format
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55 : &ieee_extended_intel_128_format);
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56 ADJUST_BYTESIZE (XF, (TARGET_ILP32 && !TARGET_HPUX) ? 12 : 16);
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57 ADJUST_ALIGNMENT (XF, (TARGET_ILP32 && !TARGET_HPUX) ? 4 : 16);
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58
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59 ADJUST_FLOAT_FORMAT (RF, (TARGET_ILP32 && !TARGET_HPUX)
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60 ? &ieee_extended_intel_96_format
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61 : &ieee_extended_intel_128_format);
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62 ADJUST_BYTESIZE (RF, (TARGET_ILP32 && !TARGET_HPUX) ? 12 : 16);
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63 ADJUST_ALIGNMENT (RF, (TARGET_ILP32 && !TARGET_HPUX) ? 4 : 16);
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64
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65 ADJUST_ALIGNMENT (TF, (TARGET_ILP32 && TARGET_HPUX) ? 8 : 16);
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66
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67 /* 256-bit integer mode is needed for STACK_SAVEAREA_MODE. */
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68 INT_MODE (OI, 32);
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69
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70 /* Add any extra modes needed to represent the condition code.
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71
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72 CCImode is used to mark a single predicate register instead
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73 of a register pair. This is currently only used in reg_raw_mode
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74 so that flow doesn't do something stupid. */
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75
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76 CC_MODE (CCI);
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77
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78 /* Vector modes. */
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79 VECTOR_MODES (INT, 4); /* V4QI V2HI */
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80 VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
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81 VECTOR_MODE (INT, QI, 16);
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82 VECTOR_MODE (INT, HI, 8);
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83 VECTOR_MODE (INT, SI, 4);
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84 VECTOR_MODE (FLOAT, SF, 2);
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85 VECTOR_MODE (FLOAT, SF, 4);
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86
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