Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/i386/i386.h @ 63:b7f97abdc517 gcc-4.6-20100522
update gcc from gcc-4.5.0 to gcc-4.6
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Mon, 24 May 2010 12:47:05 +0900 |
| parents | 77e2b8dfacca |
| children | f6334be47118 |
| rev | line source |
|---|---|
| 0 | 1 /* Definitions of target machine for GCC for IA-32. |
| 2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, | |
|
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3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
| 0 | 4 Free Software Foundation, Inc. |
| 5 | |
| 6 This file is part of GCC. | |
| 7 | |
| 8 GCC is free software; you can redistribute it and/or modify | |
| 9 it under the terms of the GNU General Public License as published by | |
| 10 the Free Software Foundation; either version 3, or (at your option) | |
| 11 any later version. | |
| 12 | |
| 13 GCC is distributed in the hope that it will be useful, | |
| 14 but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 GNU General Public License for more details. | |
| 17 | |
| 18 Under Section 7 of GPL version 3, you are granted additional | |
| 19 permissions described in the GCC Runtime Library Exception, version | |
| 20 3.1, as published by the Free Software Foundation. | |
| 21 | |
| 22 You should have received a copy of the GNU General Public License and | |
| 23 a copy of the GCC Runtime Library Exception along with this program; | |
| 24 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
| 25 <http://www.gnu.org/licenses/>. */ | |
| 26 | |
| 27 /* The purpose of this file is to define the characteristics of the i386, | |
| 28 independent of assembler syntax or operating system. | |
| 29 | |
| 30 Three other files build on this one to describe a specific assembler syntax: | |
| 31 bsd386.h, att386.h, and sun386.h. | |
| 32 | |
| 33 The actual tm.h file for a particular system should include | |
| 34 this file, and then the file for the appropriate assembler syntax. | |
| 35 | |
| 36 Many macros that specify assembler syntax are omitted entirely from | |
| 37 this file because they really belong in the files for particular | |
| 38 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, | |
| 39 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many | |
| 40 that start with ASM_ or end in ASM_OP. */ | |
| 41 | |
| 42 /* Redefines for option macros. */ | |
| 43 | |
| 44 #define TARGET_64BIT OPTION_ISA_64BIT | |
| 45 #define TARGET_MMX OPTION_ISA_MMX | |
| 46 #define TARGET_3DNOW OPTION_ISA_3DNOW | |
| 47 #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A | |
| 48 #define TARGET_SSE OPTION_ISA_SSE | |
| 49 #define TARGET_SSE2 OPTION_ISA_SSE2 | |
| 50 #define TARGET_SSE3 OPTION_ISA_SSE3 | |
| 51 #define TARGET_SSSE3 OPTION_ISA_SSSE3 | |
| 52 #define TARGET_SSE4_1 OPTION_ISA_SSE4_1 | |
| 53 #define TARGET_SSE4_2 OPTION_ISA_SSE4_2 | |
| 54 #define TARGET_AVX OPTION_ISA_AVX | |
| 55 #define TARGET_FMA OPTION_ISA_FMA | |
| 56 #define TARGET_SSE4A OPTION_ISA_SSE4A | |
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57 #define TARGET_FMA4 OPTION_ISA_FMA4 |
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58 #define TARGET_XOP OPTION_ISA_XOP |
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59 #define TARGET_LWP OPTION_ISA_LWP |
| 0 | 60 #define TARGET_ROUND OPTION_ISA_ROUND |
| 61 #define TARGET_ABM OPTION_ISA_ABM | |
| 62 #define TARGET_POPCNT OPTION_ISA_POPCNT | |
| 63 #define TARGET_SAHF OPTION_ISA_SAHF | |
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64 #define TARGET_MOVBE OPTION_ISA_MOVBE |
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65 #define TARGET_CRC32 OPTION_ISA_CRC32 |
| 0 | 66 #define TARGET_AES OPTION_ISA_AES |
| 67 #define TARGET_PCLMUL OPTION_ISA_PCLMUL | |
| 68 #define TARGET_CMPXCHG16B OPTION_ISA_CX16 | |
| 69 | |
| 70 | |
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71 /* SSE4.1 defines round instructions */ |
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72 #define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1 |
| 0 | 73 #define OPTION_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0) |
| 74 | |
| 75 #include "config/vxworks-dummy.h" | |
| 76 | |
| 77 /* Algorithm to expand string function with. */ | |
| 78 enum stringop_alg | |
| 79 { | |
| 80 no_stringop, | |
| 81 libcall, | |
| 82 rep_prefix_1_byte, | |
| 83 rep_prefix_4_byte, | |
| 84 rep_prefix_8_byte, | |
| 85 loop_1_byte, | |
| 86 loop, | |
| 87 unrolled_loop | |
| 88 }; | |
| 89 | |
| 90 #define NAX_STRINGOP_ALGS 4 | |
| 91 | |
| 92 /* Specify what algorithm to use for stringops on known size. | |
| 93 When size is unknown, the UNKNOWN_SIZE alg is used. When size is | |
| 94 known at compile time or estimated via feedback, the SIZE array | |
| 95 is walked in order until MAX is greater then the estimate (or -1 | |
| 96 means infinity). Corresponding ALG is used then. | |
| 97 For example initializer: | |
| 98 {{256, loop}, {-1, rep_prefix_4_byte}} | |
| 99 will use loop for blocks smaller or equal to 256 bytes, rep prefix will | |
| 100 be used otherwise. */ | |
| 101 struct stringop_algs | |
| 102 { | |
| 103 const enum stringop_alg unknown_size; | |
| 104 const struct stringop_strategy { | |
| 105 const int max; | |
| 106 const enum stringop_alg alg; | |
| 107 } size [NAX_STRINGOP_ALGS]; | |
| 108 }; | |
| 109 | |
| 110 /* Define the specific costs for a given cpu */ | |
| 111 | |
| 112 struct processor_costs { | |
| 113 const int add; /* cost of an add instruction */ | |
| 114 const int lea; /* cost of a lea instruction */ | |
| 115 const int shift_var; /* variable shift costs */ | |
| 116 const int shift_const; /* constant shift costs */ | |
| 117 const int mult_init[5]; /* cost of starting a multiply | |
| 118 in QImode, HImode, SImode, DImode, TImode*/ | |
| 119 const int mult_bit; /* cost of multiply per each bit set */ | |
| 120 const int divide[5]; /* cost of a divide/mod | |
| 121 in QImode, HImode, SImode, DImode, TImode*/ | |
| 122 int movsx; /* The cost of movsx operation. */ | |
| 123 int movzx; /* The cost of movzx operation. */ | |
| 124 const int large_insn; /* insns larger than this cost more */ | |
| 125 const int move_ratio; /* The threshold of number of scalar | |
| 126 memory-to-memory move insns. */ | |
| 127 const int movzbl_load; /* cost of loading using movzbl */ | |
| 128 const int int_load[3]; /* cost of loading integer registers | |
| 129 in QImode, HImode and SImode relative | |
| 130 to reg-reg move (2). */ | |
| 131 const int int_store[3]; /* cost of storing integer register | |
| 132 in QImode, HImode and SImode */ | |
| 133 const int fp_move; /* cost of reg,reg fld/fst */ | |
| 134 const int fp_load[3]; /* cost of loading FP register | |
| 135 in SFmode, DFmode and XFmode */ | |
| 136 const int fp_store[3]; /* cost of storing FP register | |
| 137 in SFmode, DFmode and XFmode */ | |
| 138 const int mmx_move; /* cost of moving MMX register. */ | |
| 139 const int mmx_load[2]; /* cost of loading MMX register | |
| 140 in SImode and DImode */ | |
| 141 const int mmx_store[2]; /* cost of storing MMX register | |
| 142 in SImode and DImode */ | |
| 143 const int sse_move; /* cost of moving SSE register. */ | |
| 144 const int sse_load[3]; /* cost of loading SSE register | |
| 145 in SImode, DImode and TImode*/ | |
| 146 const int sse_store[3]; /* cost of storing SSE register | |
| 147 in SImode, DImode and TImode*/ | |
| 148 const int mmxsse_to_integer; /* cost of moving mmxsse register to | |
| 149 integer and vice versa. */ | |
| 150 const int l1_cache_size; /* size of l1 cache, in kilobytes. */ | |
| 151 const int l2_cache_size; /* size of l2 cache, in kilobytes. */ | |
| 152 const int prefetch_block; /* bytes moved to cache for prefetch. */ | |
| 153 const int simultaneous_prefetches; /* number of parallel prefetch | |
| 154 operations. */ | |
| 155 const int branch_cost; /* Default value for BRANCH_COST. */ | |
| 156 const int fadd; /* cost of FADD and FSUB instructions. */ | |
| 157 const int fmul; /* cost of FMUL instruction. */ | |
| 158 const int fdiv; /* cost of FDIV instruction. */ | |
| 159 const int fabs; /* cost of FABS instruction. */ | |
| 160 const int fchs; /* cost of FCHS instruction. */ | |
| 161 const int fsqrt; /* cost of FSQRT instruction. */ | |
| 162 /* Specify what algorithm | |
| 163 to use for stringops on unknown size. */ | |
| 164 struct stringop_algs memcpy[2], memset[2]; | |
| 165 const int scalar_stmt_cost; /* Cost of any scalar operation, excluding | |
| 166 load and store. */ | |
| 167 const int scalar_load_cost; /* Cost of scalar load. */ | |
| 168 const int scalar_store_cost; /* Cost of scalar store. */ | |
| 169 const int vec_stmt_cost; /* Cost of any vector operation, excluding | |
| 170 load, store, vector-to-scalar and | |
| 171 scalar-to-vector operation. */ | |
| 172 const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */ | |
| 173 const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */ | |
| 174 const int vec_align_load_cost; /* Cost of aligned vector load. */ | |
| 175 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ | |
| 176 const int vec_store_cost; /* Cost of vector store. */ | |
| 177 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer | |
| 178 cost model. */ | |
| 179 const int cond_not_taken_branch_cost;/* Cost of not taken branch for | |
| 180 vectorizer cost model. */ | |
| 181 }; | |
| 182 | |
| 183 extern const struct processor_costs *ix86_cost; | |
| 184 extern const struct processor_costs ix86_size_cost; | |
| 185 | |
| 186 #define ix86_cur_cost() \ | |
| 187 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) | |
| 188 | |
| 189 /* Macros used in the machine description to test the flags. */ | |
| 190 | |
| 191 /* configure can arrange to make this 2, to force a 486. */ | |
| 192 | |
| 193 #ifndef TARGET_CPU_DEFAULT | |
| 194 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic | |
| 195 #endif | |
| 196 | |
| 197 #ifndef TARGET_FPMATH_DEFAULT | |
| 198 #define TARGET_FPMATH_DEFAULT \ | |
| 199 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) | |
| 200 #endif | |
| 201 | |
| 202 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS | |
| 203 | |
| 204 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a | |
| 205 compile-time constant. */ | |
| 206 #ifdef IN_LIBGCC2 | |
| 207 #undef TARGET_64BIT | |
| 208 #ifdef __x86_64__ | |
| 209 #define TARGET_64BIT 1 | |
| 210 #else | |
| 211 #define TARGET_64BIT 0 | |
| 212 #endif | |
| 213 #else | |
| 214 #ifndef TARGET_BI_ARCH | |
| 215 #undef TARGET_64BIT | |
| 216 #if TARGET_64BIT_DEFAULT | |
| 217 #define TARGET_64BIT 1 | |
| 218 #else | |
| 219 #define TARGET_64BIT 0 | |
| 220 #endif | |
| 221 #endif | |
| 222 #endif | |
| 223 | |
| 224 #define HAS_LONG_COND_BRANCH 1 | |
| 225 #define HAS_LONG_UNCOND_BRANCH 1 | |
| 226 | |
| 227 #define TARGET_386 (ix86_tune == PROCESSOR_I386) | |
| 228 #define TARGET_486 (ix86_tune == PROCESSOR_I486) | |
| 229 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) | |
| 230 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) | |
| 231 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) | |
| 232 #define TARGET_K6 (ix86_tune == PROCESSOR_K6) | |
| 233 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) | |
| 234 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) | |
| 235 #define TARGET_K8 (ix86_tune == PROCESSOR_K8) | |
| 236 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) | |
| 237 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) | |
| 238 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) | |
| 239 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32) | |
| 240 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64) | |
| 241 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64) | |
| 242 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) | |
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243 #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1) |
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244 #define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM) |
| 0 | 245 |
| 246 /* Feature tests against the various tunings. */ | |
| 247 enum ix86_tune_indices { | |
| 248 X86_TUNE_USE_LEAVE, | |
| 249 X86_TUNE_PUSH_MEMORY, | |
| 250 X86_TUNE_ZERO_EXTEND_WITH_AND, | |
| 251 X86_TUNE_UNROLL_STRLEN, | |
| 252 X86_TUNE_DEEP_BRANCH_PREDICTION, | |
| 253 X86_TUNE_BRANCH_PREDICTION_HINTS, | |
| 254 X86_TUNE_DOUBLE_WITH_ADD, | |
| 255 X86_TUNE_USE_SAHF, | |
| 256 X86_TUNE_MOVX, | |
| 257 X86_TUNE_PARTIAL_REG_STALL, | |
| 258 X86_TUNE_PARTIAL_FLAG_REG_STALL, | |
| 259 X86_TUNE_USE_HIMODE_FIOP, | |
| 260 X86_TUNE_USE_SIMODE_FIOP, | |
| 261 X86_TUNE_USE_MOV0, | |
| 262 X86_TUNE_USE_CLTD, | |
| 263 X86_TUNE_USE_XCHGB, | |
| 264 X86_TUNE_SPLIT_LONG_MOVES, | |
| 265 X86_TUNE_READ_MODIFY_WRITE, | |
| 266 X86_TUNE_READ_MODIFY, | |
| 267 X86_TUNE_PROMOTE_QIMODE, | |
| 268 X86_TUNE_FAST_PREFIX, | |
| 269 X86_TUNE_SINGLE_STRINGOP, | |
| 270 X86_TUNE_QIMODE_MATH, | |
| 271 X86_TUNE_HIMODE_MATH, | |
| 272 X86_TUNE_PROMOTE_QI_REGS, | |
| 273 X86_TUNE_PROMOTE_HI_REGS, | |
| 274 X86_TUNE_ADD_ESP_4, | |
| 275 X86_TUNE_ADD_ESP_8, | |
| 276 X86_TUNE_SUB_ESP_4, | |
| 277 X86_TUNE_SUB_ESP_8, | |
| 278 X86_TUNE_INTEGER_DFMODE_MOVES, | |
| 279 X86_TUNE_PARTIAL_REG_DEPENDENCY, | |
| 280 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, | |
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281 X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, |
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282 X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, |
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283 X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, |
| 0 | 284 X86_TUNE_SSE_SPLIT_REGS, |
| 285 X86_TUNE_SSE_TYPELESS_STORES, | |
| 286 X86_TUNE_SSE_LOAD0_BY_PXOR, | |
| 287 X86_TUNE_MEMORY_MISMATCH_STALL, | |
| 288 X86_TUNE_PROLOGUE_USING_MOVE, | |
| 289 X86_TUNE_EPILOGUE_USING_MOVE, | |
| 290 X86_TUNE_SHIFT1, | |
| 291 X86_TUNE_USE_FFREEP, | |
| 292 X86_TUNE_INTER_UNIT_MOVES, | |
| 293 X86_TUNE_INTER_UNIT_CONVERSIONS, | |
| 294 X86_TUNE_FOUR_JUMP_LIMIT, | |
| 295 X86_TUNE_SCHEDULE, | |
| 296 X86_TUNE_USE_BT, | |
| 297 X86_TUNE_USE_INCDEC, | |
| 298 X86_TUNE_PAD_RETURNS, | |
| 299 X86_TUNE_EXT_80387_CONSTANTS, | |
| 300 X86_TUNE_SHORTEN_X87_SSE, | |
| 301 X86_TUNE_AVOID_VECTOR_DECODE, | |
| 302 X86_TUNE_PROMOTE_HIMODE_IMUL, | |
| 303 X86_TUNE_SLOW_IMUL_IMM32_MEM, | |
| 304 X86_TUNE_SLOW_IMUL_IMM8, | |
| 305 X86_TUNE_MOVE_M1_VIA_OR, | |
| 306 X86_TUNE_NOT_UNPAIRABLE, | |
| 307 X86_TUNE_NOT_VECTORMODE, | |
| 308 X86_TUNE_USE_VECTOR_FP_CONVERTS, | |
| 309 X86_TUNE_USE_VECTOR_CONVERTS, | |
| 310 X86_TUNE_FUSE_CMP_AND_BRANCH, | |
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311 X86_TUNE_OPT_AGU, |
| 0 | 312 |
| 313 X86_TUNE_LAST | |
| 314 }; | |
| 315 | |
| 316 extern unsigned char ix86_tune_features[X86_TUNE_LAST]; | |
| 317 | |
| 318 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] | |
| 319 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] | |
| 320 #define TARGET_ZERO_EXTEND_WITH_AND \ | |
| 321 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] | |
| 322 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] | |
| 323 #define TARGET_DEEP_BRANCH_PREDICTION \ | |
| 324 ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION] | |
| 325 #define TARGET_BRANCH_PREDICTION_HINTS \ | |
| 326 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] | |
| 327 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] | |
| 328 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] | |
| 329 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] | |
| 330 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] | |
| 331 #define TARGET_PARTIAL_FLAG_REG_STALL \ | |
| 332 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] | |
| 333 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] | |
| 334 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] | |
| 335 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] | |
| 336 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] | |
| 337 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] | |
| 338 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] | |
| 339 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] | |
| 340 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] | |
| 341 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] | |
| 342 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] | |
| 343 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] | |
| 344 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] | |
| 345 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] | |
| 346 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] | |
| 347 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] | |
| 348 #define TARGET_ADD_ESP_4 ix86_tune_features[X86_TUNE_ADD_ESP_4] | |
| 349 #define TARGET_ADD_ESP_8 ix86_tune_features[X86_TUNE_ADD_ESP_8] | |
| 350 #define TARGET_SUB_ESP_4 ix86_tune_features[X86_TUNE_SUB_ESP_4] | |
| 351 #define TARGET_SUB_ESP_8 ix86_tune_features[X86_TUNE_SUB_ESP_8] | |
| 352 #define TARGET_INTEGER_DFMODE_MOVES \ | |
| 353 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] | |
| 354 #define TARGET_PARTIAL_REG_DEPENDENCY \ | |
| 355 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] | |
| 356 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ | |
| 357 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] | |
|
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358 #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ |
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359 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL] |
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360 #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \ |
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361 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL] |
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362 #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \ |
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363 ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL] |
| 0 | 364 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] |
| 365 #define TARGET_SSE_TYPELESS_STORES \ | |
| 366 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] | |
| 367 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] | |
| 368 #define TARGET_MEMORY_MISMATCH_STALL \ | |
| 369 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] | |
| 370 #define TARGET_PROLOGUE_USING_MOVE \ | |
| 371 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] | |
| 372 #define TARGET_EPILOGUE_USING_MOVE \ | |
| 373 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] | |
| 374 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] | |
| 375 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] | |
| 376 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES] | |
| 377 #define TARGET_INTER_UNIT_CONVERSIONS\ | |
| 378 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] | |
| 379 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] | |
| 380 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] | |
| 381 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] | |
| 382 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] | |
| 383 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] | |
| 384 #define TARGET_EXT_80387_CONSTANTS \ | |
| 385 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] | |
| 386 #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE] | |
| 387 #define TARGET_AVOID_VECTOR_DECODE \ | |
| 388 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] | |
| 389 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ | |
| 390 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] | |
| 391 #define TARGET_SLOW_IMUL_IMM32_MEM \ | |
| 392 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] | |
| 393 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] | |
| 394 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] | |
| 395 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] | |
| 396 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] | |
| 397 #define TARGET_USE_VECTOR_FP_CONVERTS \ | |
| 398 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] | |
| 399 #define TARGET_USE_VECTOR_CONVERTS \ | |
| 400 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] | |
| 401 #define TARGET_FUSE_CMP_AND_BRANCH \ | |
| 402 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH] | |
|
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403 #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU] |
| 0 | 404 |
| 405 /* Feature tests against the various architecture variations. */ | |
| 406 enum ix86_arch_indices { | |
| 407 X86_ARCH_CMOVE, /* || TARGET_SSE */ | |
| 408 X86_ARCH_CMPXCHG, | |
| 409 X86_ARCH_CMPXCHG8B, | |
| 410 X86_ARCH_XADD, | |
| 411 X86_ARCH_BSWAP, | |
| 412 | |
| 413 X86_ARCH_LAST | |
| 414 }; | |
| 415 | |
| 416 extern unsigned char ix86_arch_features[X86_ARCH_LAST]; | |
| 417 | |
| 418 #define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE] | |
| 419 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] | |
| 420 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] | |
| 421 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] | |
| 422 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] | |
| 423 | |
| 424 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) | |
| 425 | |
| 426 extern int x86_prefetch_sse; | |
| 427 | |
| 428 #define TARGET_PREFETCH_SSE x86_prefetch_sse | |
| 429 | |
| 430 #define ASSEMBLER_DIALECT (ix86_asm_dialect) | |
| 431 | |
| 432 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) | |
| 433 #define TARGET_MIX_SSE_I387 \ | |
| 434 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) | |
| 435 | |
| 436 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) | |
| 437 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) | |
| 438 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) | |
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439 #define TARGET_SUN_TLS 0 |
| 0 | 440 |
| 441 extern int ix86_isa_flags; | |
| 442 | |
| 443 #ifndef TARGET_64BIT_DEFAULT | |
| 444 #define TARGET_64BIT_DEFAULT 0 | |
| 445 #endif | |
| 446 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT | |
| 447 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 | |
| 448 #endif | |
| 449 | |
| 450 /* Fence to use after loop using storent. */ | |
| 451 | |
| 452 extern tree x86_mfence; | |
| 453 #define FENCE_FOLLOWING_MOVNT x86_mfence | |
| 454 | |
| 455 /* Once GDB has been enhanced to deal with functions without frame | |
| 456 pointers, we can change this to allow for elimination of | |
| 457 the frame pointer in leaf functions. */ | |
| 458 #define TARGET_DEFAULT 0 | |
| 459 | |
| 460 /* Extra bits to force. */ | |
| 461 #define TARGET_SUBTARGET_DEFAULT 0 | |
| 462 #define TARGET_SUBTARGET_ISA_DEFAULT 0 | |
| 463 | |
| 464 /* Extra bits to force on w/ 32-bit mode. */ | |
| 465 #define TARGET_SUBTARGET32_DEFAULT 0 | |
| 466 #define TARGET_SUBTARGET32_ISA_DEFAULT 0 | |
| 467 | |
| 468 /* Extra bits to force on w/ 64-bit mode. */ | |
| 469 #define TARGET_SUBTARGET64_DEFAULT 0 | |
| 470 #define TARGET_SUBTARGET64_ISA_DEFAULT 0 | |
| 471 | |
| 472 /* This is not really a target flag, but is done this way so that | |
| 473 it's analogous to similar code for Mach-O on PowerPC. darwin.h | |
| 474 redefines this to 1. */ | |
| 475 #define TARGET_MACHO 0 | |
| 476 | |
| 477 /* Likewise, for the Windows 64-bit ABI. */ | |
| 478 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) | |
| 479 | |
| 480 /* Available call abi. */ | |
| 481 enum calling_abi | |
| 482 { | |
| 483 SYSV_ABI = 0, | |
| 484 MS_ABI = 1 | |
| 485 }; | |
| 486 | |
|
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487 /* The abi used by target. */ |
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488 extern enum calling_abi ix86_abi; |
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489 |
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490 /* The default abi used by target. */ |
| 0 | 491 #define DEFAULT_ABI SYSV_ABI |
| 492 | |
| 493 /* Subtargets may reset this to 1 in order to enable 96-bit long double | |
| 494 with the rounding mode forced to 53 bits. */ | |
| 495 #define TARGET_96_ROUND_53_LONG_DOUBLE 0 | |
| 496 | |
| 497 /* Sometimes certain combinations of command options do not make | |
| 498 sense on a particular target machine. You can define a macro | |
| 499 `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
| 500 defined, is executed once just after all the command options have | |
| 501 been parsed. | |
| 502 | |
| 503 Don't use this macro to turn on various extra optimizations for | |
| 504 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
| 505 | |
| 506 #define OVERRIDE_OPTIONS override_options (true) | |
| 507 | |
| 508 /* Define this to change the optimizations performed by default. */ | |
| 509 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ | |
| 510 optimization_options ((LEVEL), (SIZE)) | |
| 511 | |
| 512 /* -march=native handling only makes sense with compiler running on | |
| 513 an x86 or x86_64 chip. If changing this condition, also change | |
| 514 the condition in driver-i386.c. */ | |
| 515 #if defined(__i386__) || defined(__x86_64__) | |
| 516 /* In driver-i386.c. */ | |
| 517 extern const char *host_detect_local_cpu (int argc, const char **argv); | |
| 518 #define EXTRA_SPEC_FUNCTIONS \ | |
| 519 { "local_cpu_detect", host_detect_local_cpu }, | |
| 520 #define HAVE_LOCAL_CPU_DETECT | |
| 521 #endif | |
| 522 | |
| 523 #if TARGET_64BIT_DEFAULT | |
| 524 #define OPT_ARCH64 "!m32" | |
| 525 #define OPT_ARCH32 "m32" | |
| 526 #else | |
| 527 #define OPT_ARCH64 "m64" | |
| 528 #define OPT_ARCH32 "!m64" | |
| 529 #endif | |
| 530 | |
| 531 /* Support for configure-time defaults of some command line options. | |
| 532 The order here is important so that -march doesn't squash the | |
| 533 tune or cpu values. */ | |
| 534 #define OPTION_DEFAULT_SPECS \ | |
| 535 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ | |
| 536 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
| 537 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
| 538 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ | |
| 539 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
| 540 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
| 541 {"arch", "%{!march=*:-march=%(VALUE)}"}, \ | |
| 542 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ | |
| 543 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, | |
| 544 | |
| 545 /* Specs for the compiler proper */ | |
| 546 | |
| 547 #ifndef CC1_CPU_SPEC | |
| 548 #define CC1_CPU_SPEC_1 "\ | |
| 549 %{mcpu=*:-mtune=%* \ | |
| 550 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n} \ | |
| 551 %<mcpu=* \ | |
| 552 %{mintel-syntax:-masm=intel \ | |
| 553 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ | |
|
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554 %{msse5:-mavx \ |
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555 %n'-msse5' was removed.\n} \ |
| 0 | 556 %{mno-intel-syntax:-masm=att \ |
| 557 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" | |
| 558 | |
| 559 #ifndef HAVE_LOCAL_CPU_DETECT | |
| 560 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 | |
| 561 #else | |
| 562 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ | |
| 563 "%{march=native:%<march=native %:local_cpu_detect(arch) \ | |
| 564 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \ | |
| 565 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
| 566 #endif | |
| 567 #endif | |
| 568 | |
| 569 /* Target CPU builtins. */ | |
| 570 #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () | |
| 571 | |
| 572 /* Target Pragmas. */ | |
| 573 #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () | |
| 574 | |
| 575 enum target_cpu_default | |
| 576 { | |
| 577 TARGET_CPU_DEFAULT_generic = 0, | |
| 578 | |
| 579 TARGET_CPU_DEFAULT_i386, | |
| 580 TARGET_CPU_DEFAULT_i486, | |
| 581 TARGET_CPU_DEFAULT_pentium, | |
| 582 TARGET_CPU_DEFAULT_pentium_mmx, | |
| 583 TARGET_CPU_DEFAULT_pentiumpro, | |
| 584 TARGET_CPU_DEFAULT_pentium2, | |
| 585 TARGET_CPU_DEFAULT_pentium3, | |
| 586 TARGET_CPU_DEFAULT_pentium4, | |
| 587 TARGET_CPU_DEFAULT_pentium_m, | |
| 588 TARGET_CPU_DEFAULT_prescott, | |
| 589 TARGET_CPU_DEFAULT_nocona, | |
| 590 TARGET_CPU_DEFAULT_core2, | |
|
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591 TARGET_CPU_DEFAULT_atom, |
| 0 | 592 |
| 593 TARGET_CPU_DEFAULT_geode, | |
| 594 TARGET_CPU_DEFAULT_k6, | |
| 595 TARGET_CPU_DEFAULT_k6_2, | |
| 596 TARGET_CPU_DEFAULT_k6_3, | |
| 597 TARGET_CPU_DEFAULT_athlon, | |
| 598 TARGET_CPU_DEFAULT_athlon_sse, | |
| 599 TARGET_CPU_DEFAULT_k8, | |
| 600 TARGET_CPU_DEFAULT_amdfam10, | |
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601 TARGET_CPU_DEFAULT_bdver1, |
| 0 | 602 |
| 603 TARGET_CPU_DEFAULT_max | |
| 604 }; | |
| 605 | |
| 606 #ifndef CC1_SPEC | |
| 607 #define CC1_SPEC "%(cc1_cpu) " | |
| 608 #endif | |
| 609 | |
| 610 /* This macro defines names of additional specifications to put in the | |
| 611 specs that can be used in various specifications like CC1_SPEC. Its | |
| 612 definition is an initializer with a subgrouping for each command option. | |
| 613 | |
| 614 Each subgrouping contains a string constant, that defines the | |
| 615 specification name, and a string constant that used by the GCC driver | |
| 616 program. | |
| 617 | |
| 618 Do not define this macro if it does not need to do anything. */ | |
| 619 | |
| 620 #ifndef SUBTARGET_EXTRA_SPECS | |
| 621 #define SUBTARGET_EXTRA_SPECS | |
| 622 #endif | |
| 623 | |
| 624 #define EXTRA_SPECS \ | |
| 625 { "cc1_cpu", CC1_CPU_SPEC }, \ | |
| 626 SUBTARGET_EXTRA_SPECS | |
| 627 | |
| 628 | |
| 629 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the | |
| 630 FPU, assume that the fpcw is set to extended precision; when using | |
| 631 only SSE, rounding is correct; when using both SSE and the FPU, | |
| 632 the rounding precision is indeterminate, since either may be chosen | |
| 633 apparently at random. */ | |
| 634 #define TARGET_FLT_EVAL_METHOD \ | |
| 635 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) | |
| 636 | |
|
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637 /* Whether to allow x87 floating-point arithmetic on MODE (one of |
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638 SFmode, DFmode and XFmode) in the current excess precision |
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639 configuration. */ |
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640 #define X87_ENABLE_ARITH(MODE) \ |
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641 (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode) |
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642 |
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643 /* Likewise, whether to allow direct conversions from integer mode |
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644 IMODE (HImode, SImode or DImode) to MODE. */ |
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645 #define X87_ENABLE_FLOAT(MODE, IMODE) \ |
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646 (flag_excess_precision == EXCESS_PRECISION_FAST \ |
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647 || (MODE) == XFmode \ |
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648 || ((MODE) == DFmode && (IMODE) == SImode) \ |
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649 || (IMODE) == HImode) |
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650 |
| 0 | 651 /* target machine storage layout */ |
| 652 | |
| 653 #define SHORT_TYPE_SIZE 16 | |
| 654 #define INT_TYPE_SIZE 32 | |
| 655 #define FLOAT_TYPE_SIZE 32 | |
| 656 #define LONG_TYPE_SIZE BITS_PER_WORD | |
| 657 #define DOUBLE_TYPE_SIZE 64 | |
| 658 #define LONG_LONG_TYPE_SIZE 64 | |
| 659 #define LONG_DOUBLE_TYPE_SIZE 80 | |
| 660 | |
| 661 #define WIDEST_HARDWARE_FP_SIZE LONG_DOUBLE_TYPE_SIZE | |
| 662 | |
| 663 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT | |
| 664 #define MAX_BITS_PER_WORD 64 | |
| 665 #else | |
| 666 #define MAX_BITS_PER_WORD 32 | |
| 667 #endif | |
| 668 | |
| 669 /* Define this if most significant byte of a word is the lowest numbered. */ | |
| 670 /* That is true on the 80386. */ | |
| 671 | |
| 672 #define BITS_BIG_ENDIAN 0 | |
| 673 | |
| 674 /* Define this if most significant byte of a word is the lowest numbered. */ | |
| 675 /* That is not true on the 80386. */ | |
| 676 #define BYTES_BIG_ENDIAN 0 | |
| 677 | |
| 678 /* Define this if most significant word of a multiword number is the lowest | |
| 679 numbered. */ | |
| 680 /* Not true for 80386 */ | |
| 681 #define WORDS_BIG_ENDIAN 0 | |
| 682 | |
| 683 /* Width of a word, in units (bytes). */ | |
| 684 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) | |
| 685 #ifdef IN_LIBGCC2 | |
| 686 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) | |
| 687 #else | |
| 688 #define MIN_UNITS_PER_WORD 4 | |
| 689 #endif | |
| 690 | |
| 691 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
| 692 #define PARM_BOUNDARY BITS_PER_WORD | |
| 693 | |
| 694 /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
| 695 #define STACK_BOUNDARY \ | |
|
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696 (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD) |
| 0 | 697 |
| 698 /* Stack boundary of the main function guaranteed by OS. */ | |
| 699 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) | |
| 700 | |
| 701 /* Minimum stack boundary. */ | |
| 702 #define MIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) | |
| 703 | |
| 704 /* Boundary (in *bits*) on which the stack pointer prefers to be | |
| 705 aligned; the compiler cannot rely on having this alignment. */ | |
| 706 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary | |
| 707 | |
| 708 /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for | |
| 709 both 32bit and 64bit, to support codes that need 128 bit stack | |
| 710 alignment for SSE instructions, but can't realign the stack. */ | |
| 711 #define PREFERRED_STACK_BOUNDARY_DEFAULT 128 | |
| 712 | |
| 713 /* 1 if -mstackrealign should be turned on by default. It will | |
| 714 generate an alternate prologue and epilogue that realigns the | |
| 715 runtime stack if nessary. This supports mixing codes that keep a | |
| 716 4-byte aligned stack, as specified by i386 psABI, with codes that | |
|
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717 need a 16-byte aligned stack, as required by SSE instructions. */ |
| 0 | 718 #define STACK_REALIGN_DEFAULT 0 |
| 719 | |
| 720 /* Boundary (in *bits*) on which the incoming stack is aligned. */ | |
| 721 #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary | |
| 722 | |
| 723 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is | |
| 724 mandatory for the 64-bit ABI, and may or may not be true for other | |
| 725 operating systems. */ | |
| 726 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT | |
| 727 | |
| 728 /* Minimum allocation boundary for the code of a function. */ | |
| 729 #define FUNCTION_BOUNDARY 8 | |
| 730 | |
| 731 /* C++ stores the virtual bit in the lowest bit of function pointers. */ | |
| 732 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn | |
| 733 | |
| 734 /* Alignment of field after `int : 0' in a structure. */ | |
| 735 | |
| 736 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD | |
| 737 | |
| 738 /* Minimum size in bits of the largest boundary to which any | |
| 739 and all fundamental data types supported by the hardware | |
| 740 might need to be aligned. No data type wants to be aligned | |
| 741 rounder than this. | |
| 742 | |
| 743 Pentium+ prefers DFmode values to be aligned to 64 bit boundary | |
| 744 and Pentium Pro XFmode values at 128 bit boundaries. */ | |
| 745 | |
| 746 #define BIGGEST_ALIGNMENT (TARGET_AVX ? 256: 128) | |
| 747 | |
| 748 /* Maximum stack alignment. */ | |
| 749 #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT | |
| 750 | |
| 751 /* Alignment value for attribute ((aligned)). It is a constant since | |
| 752 it is the part of the ABI. We shouldn't change it with -mavx. */ | |
| 753 #define ATTRIBUTE_ALIGNED_VALUE 128 | |
| 754 | |
| 755 /* Decide whether a variable of mode MODE should be 128 bit aligned. */ | |
| 756 #define ALIGN_MODE_128(MODE) \ | |
| 757 ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) | |
| 758 | |
| 759 /* The published ABIs say that doubles should be aligned on word | |
| 760 boundaries, so lower the alignment for structure fields unless | |
| 761 -malign-double is set. */ | |
| 762 | |
| 763 /* ??? Blah -- this macro is used directly by libobjc. Since it | |
| 764 supports no vector modes, cut out the complexity and fall back | |
| 765 on BIGGEST_FIELD_ALIGNMENT. */ | |
| 766 #ifdef IN_TARGET_LIBS | |
| 767 #ifdef __x86_64__ | |
| 768 #define BIGGEST_FIELD_ALIGNMENT 128 | |
| 769 #else | |
| 770 #define BIGGEST_FIELD_ALIGNMENT 32 | |
| 771 #endif | |
| 772 #else | |
| 773 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ | |
| 774 x86_field_alignment (FIELD, COMPUTED) | |
| 775 #endif | |
| 776 | |
| 777 /* If defined, a C expression to compute the alignment given to a | |
| 778 constant that is being placed in memory. EXP is the constant | |
| 779 and ALIGN is the alignment that the object would ordinarily have. | |
| 780 The value of this macro is used instead of that alignment to align | |
| 781 the object. | |
| 782 | |
| 783 If this macro is not defined, then ALIGN is used. | |
| 784 | |
| 785 The typical use of this macro is to increase alignment for string | |
| 786 constants to be word aligned so that `strcpy' calls that copy | |
| 787 constants can be done inline. */ | |
| 788 | |
| 789 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) | |
| 790 | |
| 791 /* If defined, a C expression to compute the alignment for a static | |
| 792 variable. TYPE is the data type, and ALIGN is the alignment that | |
| 793 the object would ordinarily have. The value of this macro is used | |
| 794 instead of that alignment to align the object. | |
| 795 | |
| 796 If this macro is not defined, then ALIGN is used. | |
| 797 | |
| 798 One use of this macro is to increase alignment of medium-size | |
| 799 data to make it all fit in fewer cache lines. Another is to | |
| 800 cause character arrays to be word-aligned so that `strcpy' calls | |
| 801 that copy constants to character arrays can be done inline. */ | |
| 802 | |
| 803 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) | |
| 804 | |
| 805 /* If defined, a C expression to compute the alignment for a local | |
| 806 variable. TYPE is the data type, and ALIGN is the alignment that | |
| 807 the object would ordinarily have. The value of this macro is used | |
| 808 instead of that alignment to align the object. | |
| 809 | |
| 810 If this macro is not defined, then ALIGN is used. | |
| 811 | |
| 812 One use of this macro is to increase alignment of medium-size | |
| 813 data to make it all fit in fewer cache lines. */ | |
| 814 | |
| 815 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
| 816 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) | |
| 817 | |
| 818 /* If defined, a C expression to compute the alignment for stack slot. | |
| 819 TYPE is the data type, MODE is the widest mode available, and ALIGN | |
| 820 is the alignment that the slot would ordinarily have. The value of | |
| 821 this macro is used instead of that alignment to align the slot. | |
| 822 | |
| 823 If this macro is not defined, then ALIGN is used when TYPE is NULL, | |
| 824 Otherwise, LOCAL_ALIGNMENT will be used. | |
| 825 | |
| 826 One use of this macro is to set alignment of stack slot to the | |
| 827 maximum alignment of all possible modes which the slot may have. */ | |
| 828 | |
| 829 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ | |
| 830 ix86_local_alignment ((TYPE), (MODE), (ALIGN)) | |
| 831 | |
| 832 /* If defined, a C expression to compute the alignment for a local | |
| 833 variable DECL. | |
| 834 | |
| 835 If this macro is not defined, then | |
| 836 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. | |
| 837 | |
| 838 One use of this macro is to increase alignment of medium-size | |
| 839 data to make it all fit in fewer cache lines. */ | |
| 840 | |
| 841 #define LOCAL_DECL_ALIGNMENT(DECL) \ | |
| 842 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) | |
| 843 | |
|
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844 /* If defined, a C expression to compute the minimum required alignment |
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845 for dynamic stack realignment purposes for EXP (a TYPE or DECL), |
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846 MODE, assuming normal alignment ALIGN. |
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847 |
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848 If this macro is not defined, then (ALIGN) will be used. */ |
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849 |
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850 #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ |
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851 ix86_minimum_alignment (EXP, MODE, ALIGN) |
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852 |
| 0 | 853 |
| 854 /* If defined, a C expression that gives the alignment boundary, in | |
| 855 bits, of an argument with the specified mode and type. If it is | |
| 856 not defined, `PARM_BOUNDARY' is used for all arguments. */ | |
| 857 | |
| 858 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ | |
| 859 ix86_function_arg_boundary ((MODE), (TYPE)) | |
| 860 | |
| 861 /* Set this nonzero if move instructions will actually fail to work | |
| 862 when given unaligned data. */ | |
| 863 #define STRICT_ALIGNMENT 0 | |
| 864 | |
| 865 /* If bit field type is int, don't let it cross an int, | |
| 866 and give entire struct the alignment of an int. */ | |
| 867 /* Required on the 386 since it doesn't have bit-field insns. */ | |
| 868 #define PCC_BITFIELD_TYPE_MATTERS 1 | |
| 869 | |
| 870 /* Standard register usage. */ | |
| 871 | |
| 872 /* This processor has special stack-like registers. See reg-stack.c | |
| 873 for details. */ | |
| 874 | |
| 875 #define STACK_REGS | |
| 876 | |
| 877 #define IS_STACK_MODE(MODE) \ | |
| 878 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \ | |
| 879 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \ | |
| 880 || (MODE) == XFmode) | |
| 881 | |
|
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882 /* Cover class containing the stack registers. */ |
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883 #define STACK_REG_COVER_CLASS FLOAT_REGS |
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884 |
| 0 | 885 /* Number of actual hardware registers. |
| 886 The hardware registers are assigned numbers for the compiler | |
| 887 from 0 to just below FIRST_PSEUDO_REGISTER. | |
| 888 All registers that the compiler knows about must be given numbers, | |
| 889 even those that are not normally considered general registers. | |
| 890 | |
| 891 In the 80386 we give the 8 general purpose registers the numbers 0-7. | |
| 892 We number the floating point registers 8-15. | |
| 893 Note that registers 0-7 can be accessed as a short or int, | |
| 894 while only 0-3 may be used with byte `mov' instructions. | |
| 895 | |
| 896 Reg 16 does not correspond to any hardware register, but instead | |
| 897 appears in the RTL as an argument pointer prior to reload, and is | |
| 898 eliminated during reloading in favor of either the stack or frame | |
| 899 pointer. */ | |
| 900 | |
| 901 #define FIRST_PSEUDO_REGISTER 53 | |
| 902 | |
| 903 /* Number of hardware registers that go into the DWARF-2 unwind info. | |
| 904 If not defined, equals FIRST_PSEUDO_REGISTER. */ | |
| 905 | |
| 906 #define DWARF_FRAME_REGISTERS 17 | |
| 907 | |
| 908 /* 1 for registers that have pervasive standard uses | |
| 909 and are not available for the register allocator. | |
| 910 On the 80386, the stack pointer is such, as is the arg pointer. | |
| 911 | |
| 912 The value is zero if the register is not fixed on either 32 or | |
| 913 64 bit targets, one if the register if fixed on both 32 and 64 | |
| 914 bit targets, two if it is only fixed on 32bit targets and three | |
| 915 if its only fixed on 64bit targets. | |
| 916 Proper values are computed in the CONDITIONAL_REGISTER_USAGE. | |
| 917 */ | |
| 918 #define FIXED_REGISTERS \ | |
| 919 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
| 920 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 921 /*arg,flags,fpsr,fpcr,frame*/ \ | |
| 922 1, 1, 1, 1, 1, \ | |
| 923 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ | |
| 924 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 925 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ | |
| 926 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 927 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
| 928 2, 2, 2, 2, 2, 2, 2, 2, \ | |
| 929 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ | |
| 930 2, 2, 2, 2, 2, 2, 2, 2 } | |
| 931 | |
| 932 | |
| 933 /* 1 for registers not available across function calls. | |
| 934 These must include the FIXED_REGISTERS and also any | |
| 935 registers that can be used without being saved. | |
| 936 The latter must include the registers where values are returned | |
| 937 and the register where structure-value addresses are passed. | |
| 938 Aside from that, you can include as many other registers as you like. | |
| 939 | |
| 940 The value is zero if the register is not call used on either 32 or | |
| 941 64 bit targets, one if the register if call used on both 32 and 64 | |
| 942 bit targets, two if it is only call used on 32bit targets and three | |
| 943 if its only call used on 64bit targets. | |
| 944 Proper values are computed in the CONDITIONAL_REGISTER_USAGE. | |
| 945 */ | |
| 946 #define CALL_USED_REGISTERS \ | |
| 947 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
| 948 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 949 /*arg,flags,fpsr,fpcr,frame*/ \ | |
| 950 1, 1, 1, 1, 1, \ | |
| 951 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ | |
| 952 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 953 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ | |
| 954 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 955 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
| 956 1, 1, 1, 1, 2, 2, 2, 2, \ | |
| 957 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ | |
| 958 1, 1, 1, 1, 1, 1, 1, 1 } | |
| 959 | |
| 960 /* Order in which to allocate registers. Each register must be | |
| 961 listed once, even those in FIXED_REGISTERS. List frame pointer | |
| 962 late and fixed registers last. Note that, in general, we prefer | |
| 963 registers listed in CALL_USED_REGISTERS, keeping the others | |
| 964 available for storage of persistent values. | |
| 965 | |
|
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966 The ADJUST_REG_ALLOC_ORDER actually overwrite the order, |
| 0 | 967 so this is just empty initializer for array. */ |
| 968 | |
| 969 #define REG_ALLOC_ORDER \ | |
| 970 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ | |
| 971 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ | |
| 972 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
| 973 48, 49, 50, 51, 52 } | |
| 974 | |
|
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975 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order |
| 0 | 976 to be rearranged based on a particular function. When using sse math, |
| 977 we want to allocate SSE before x87 registers and vice versa. */ | |
| 978 | |
|
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979 #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () |
| 0 | 980 |
| 981 | |
| 982 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) | |
| 983 | |
| 984 /* Macro to conditionally modify fixed_regs/call_used_regs. */ | |
|
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985 #define CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage () |
| 0 | 986 |
| 987 /* Return number of consecutive hard regs needed starting at reg REGNO | |
| 988 to hold something of mode MODE. | |
| 989 This is ordinarily the length in words of a value of mode MODE | |
| 990 but can be less for certain modes in special long registers. | |
| 991 | |
| 992 Actually there are no two word move instructions for consecutive | |
| 993 registers. And only registers 0-3 may have mov byte instructions | |
| 994 applied to them. | |
| 995 */ | |
| 996 | |
| 997 #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
| 998 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ | |
| 999 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ | |
| 1000 : ((MODE) == XFmode \ | |
| 1001 ? (TARGET_64BIT ? 2 : 3) \ | |
| 1002 : (MODE) == XCmode \ | |
| 1003 ? (TARGET_64BIT ? 4 : 6) \ | |
| 1004 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) | |
| 1005 | |
| 1006 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ | |
| 1007 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \ | |
| 1008 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ | |
| 1009 ? 0 \ | |
| 1010 : ((MODE) == XFmode || (MODE) == XCmode)) \ | |
| 1011 : 0) | |
| 1012 | |
| 1013 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) | |
| 1014 | |
| 1015 #define VALID_AVX256_REG_MODE(MODE) \ | |
| 1016 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ | |
| 1017 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode) | |
| 1018 | |
| 1019 #define VALID_SSE2_REG_MODE(MODE) \ | |
| 1020 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
| 1021 || (MODE) == V2DImode || (MODE) == DFmode) | |
| 1022 | |
| 1023 #define VALID_SSE_REG_MODE(MODE) \ | |
|
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1024 ((MODE) == V1TImode || (MODE) == TImode \ |
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1025 || (MODE) == V4SFmode || (MODE) == V4SImode \ |
| 0 | 1026 || (MODE) == SFmode || (MODE) == TFmode) |
| 1027 | |
| 1028 #define VALID_MMX_REG_MODE_3DNOW(MODE) \ | |
| 1029 ((MODE) == V2SFmode || (MODE) == SFmode) | |
| 1030 | |
| 1031 #define VALID_MMX_REG_MODE(MODE) \ | |
| 1032 ((MODE == V1DImode) || (MODE) == DImode \ | |
| 1033 || (MODE) == V2SImode || (MODE) == SImode \ | |
| 1034 || (MODE) == V4HImode || (MODE) == V8QImode) | |
| 1035 | |
| 1036 /* ??? No autovectorization into MMX or 3DNOW until we can reliably | |
| 1037 place emms and femms instructions. | |
| 1038 FIXME: AVX has 32byte floating point vector operations and 16byte | |
| 1039 integer vector operations. But vectorizer doesn't support | |
| 1040 different sizes for integer and floating point vectors. We limit | |
| 1041 vector size to 16byte. */ | |
| 1042 #define UNITS_PER_SIMD_WORD(MODE) \ | |
| 1043 (TARGET_AVX ? (((MODE) == DFmode || (MODE) == SFmode) ? 16 : 16) \ | |
| 1044 : (TARGET_SSE ? 16 : UNITS_PER_WORD)) | |
| 1045 | |
| 1046 #define VALID_DFP_MODE_P(MODE) \ | |
| 1047 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) | |
| 1048 | |
| 1049 #define VALID_FP_MODE_P(MODE) \ | |
| 1050 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ | |
| 1051 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ | |
| 1052 | |
| 1053 #define VALID_INT_MODE_P(MODE) \ | |
| 1054 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ | |
| 1055 || (MODE) == DImode \ | |
| 1056 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ | |
| 1057 || (MODE) == CDImode \ | |
| 1058 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ | |
| 1059 || (MODE) == TFmode || (MODE) == TCmode))) | |
| 1060 | |
| 1061 /* Return true for modes passed in SSE registers. */ | |
| 1062 #define SSE_REG_MODE_P(MODE) \ | |
|
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1063 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ |
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1064 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ |
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1065 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ |
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1066 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ |
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1067 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode) |
| 0 | 1068 |
| 1069 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ | |
| 1070 | |
| 1071 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
| 1072 ix86_hard_regno_mode_ok ((REGNO), (MODE)) | |
| 1073 | |
| 1074 /* Value is 1 if it is a good idea to tie two pseudo registers | |
| 1075 when one has mode MODE1 and one has mode MODE2. | |
| 1076 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
| 1077 for any hard reg, then this must be 0 for correct output. */ | |
| 1078 | |
| 1079 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) | |
| 1080 | |
| 1081 /* It is possible to write patterns to move flags; but until someone | |
| 1082 does it, */ | |
| 1083 #define AVOID_CCMODE_COPIES | |
| 1084 | |
| 1085 /* Specify the modes required to caller save a given hard regno. | |
| 1086 We do this on i386 to prevent flags from being saved at all. | |
| 1087 | |
| 1088 Kill any attempts to combine saving of modes. */ | |
| 1089 | |
| 1090 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ | |
| 1091 (CC_REGNO_P (REGNO) ? VOIDmode \ | |
| 1092 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ | |
| 1093 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ | |
| 1094 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ | |
| 1095 : (MODE) == QImode && (REGNO) > BX_REG && !TARGET_64BIT ? SImode \ | |
| 1096 : (MODE)) | |
| 1097 | |
| 1098 /* Specify the registers used for certain standard purposes. | |
| 1099 The values of these macros are register numbers. */ | |
| 1100 | |
| 1101 /* on the 386 the pc register is %eip, and is not usable as a general | |
| 1102 register. The ordinary mov instructions won't work */ | |
| 1103 /* #define PC_REGNUM */ | |
| 1104 | |
| 1105 /* Register to use for pushing function arguments. */ | |
| 1106 #define STACK_POINTER_REGNUM 7 | |
| 1107 | |
| 1108 /* Base register for access to local variables of the function. */ | |
| 1109 #define HARD_FRAME_POINTER_REGNUM 6 | |
| 1110 | |
| 1111 /* Base register for access to local variables of the function. */ | |
| 1112 #define FRAME_POINTER_REGNUM 20 | |
| 1113 | |
| 1114 /* First floating point reg */ | |
| 1115 #define FIRST_FLOAT_REG 8 | |
| 1116 | |
| 1117 /* First & last stack-like regs */ | |
| 1118 #define FIRST_STACK_REG FIRST_FLOAT_REG | |
| 1119 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) | |
| 1120 | |
| 1121 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) | |
| 1122 #define LAST_SSE_REG (FIRST_SSE_REG + 7) | |
| 1123 | |
| 1124 #define FIRST_MMX_REG (LAST_SSE_REG + 1) | |
| 1125 #define LAST_MMX_REG (FIRST_MMX_REG + 7) | |
| 1126 | |
| 1127 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1) | |
| 1128 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) | |
| 1129 | |
| 1130 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) | |
| 1131 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) | |
| 1132 | |
| 1133 /* Override this in other tm.h files to cope with various OS lossage | |
| 1134 requiring a frame pointer. */ | |
| 1135 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
| 1136 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
| 1137 #endif | |
| 1138 | |
| 1139 /* Make sure we can access arbitrary call frames. */ | |
| 1140 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () | |
| 1141 | |
| 1142 /* Base register for access to arguments of the function. */ | |
| 1143 #define ARG_POINTER_REGNUM 16 | |
| 1144 | |
| 1145 /* Register to hold the addressing base for position independent | |
| 1146 code access to data items. We don't use PIC pointer for 64bit | |
| 1147 mode. Define the regnum to dummy value to prevent gcc from | |
| 1148 pessimizing code dealing with EBX. | |
| 1149 | |
| 1150 To avoid clobbering a call-saved register unnecessarily, we renumber | |
| 1151 the pic register when possible. The change is visible after the | |
| 1152 prologue has been emitted. */ | |
| 1153 | |
| 1154 #define REAL_PIC_OFFSET_TABLE_REGNUM BX_REG | |
| 1155 | |
| 1156 #define PIC_OFFSET_TABLE_REGNUM \ | |
| 1157 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \ | |
| 1158 || !flag_pic ? INVALID_REGNUM \ | |
| 1159 : reload_completed ? REGNO (pic_offset_table_rtx) \ | |
| 1160 : REAL_PIC_OFFSET_TABLE_REGNUM) | |
| 1161 | |
| 1162 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" | |
| 1163 | |
| 1164 /* This is overridden by <cygwin.h>. */ | |
| 1165 #define MS_AGGREGATE_RETURN 0 | |
| 1166 | |
| 1167 /* This is overridden by <netware.h>. */ | |
| 1168 #define KEEP_AGGREGATE_RETURN_POINTER 0 | |
| 1169 | |
| 1170 /* Define the classes of registers for register constraints in the | |
| 1171 machine description. Also define ranges of constants. | |
| 1172 | |
| 1173 One of the classes must always be named ALL_REGS and include all hard regs. | |
| 1174 If there is more than one class, another class must be named NO_REGS | |
| 1175 and contain no registers. | |
| 1176 | |
| 1177 The name GENERAL_REGS must be the name of a class (or an alias for | |
| 1178 another name such as ALL_REGS). This is the class of registers | |
| 1179 that is allowed by "g" or "r" in a register constraint. | |
| 1180 Also, registers outside this class are allocated only when | |
| 1181 instructions express preferences for them. | |
| 1182 | |
| 1183 The classes must be numbered in nondecreasing order; that is, | |
| 1184 a larger-numbered class must never be contained completely | |
| 1185 in a smaller-numbered class. | |
| 1186 | |
| 1187 For any two classes, it is very desirable that there be another | |
| 1188 class that represents their union. | |
| 1189 | |
| 1190 It might seem that class BREG is unnecessary, since no useful 386 | |
| 1191 opcode needs reg %ebx. But some systems pass args to the OS in ebx, | |
| 1192 and the "b" register constraint is useful in asms for syscalls. | |
| 1193 | |
| 1194 The flags, fpsr and fpcr registers are in no class. */ | |
| 1195 | |
| 1196 enum reg_class | |
| 1197 { | |
| 1198 NO_REGS, | |
| 1199 AREG, DREG, CREG, BREG, SIREG, DIREG, | |
| 1200 AD_REGS, /* %eax/%edx for DImode */ | |
|
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1201 CLOBBERED_REGS, /* call-clobbered integers */ |
| 0 | 1202 Q_REGS, /* %eax %ebx %ecx %edx */ |
| 1203 NON_Q_REGS, /* %esi %edi %ebp %esp */ | |
| 1204 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ | |
| 1205 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ | |
| 1206 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ | |
| 1207 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ | |
| 1208 FLOAT_REGS, | |
| 1209 SSE_FIRST_REG, | |
| 1210 SSE_REGS, | |
| 1211 MMX_REGS, | |
| 1212 FP_TOP_SSE_REGS, | |
| 1213 FP_SECOND_SSE_REGS, | |
| 1214 FLOAT_SSE_REGS, | |
| 1215 FLOAT_INT_REGS, | |
| 1216 INT_SSE_REGS, | |
| 1217 FLOAT_INT_SSE_REGS, | |
| 1218 ALL_REGS, LIM_REG_CLASSES | |
| 1219 }; | |
| 1220 | |
| 1221 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) | |
| 1222 | |
| 1223 #define INTEGER_CLASS_P(CLASS) \ | |
| 1224 reg_class_subset_p ((CLASS), GENERAL_REGS) | |
| 1225 #define FLOAT_CLASS_P(CLASS) \ | |
| 1226 reg_class_subset_p ((CLASS), FLOAT_REGS) | |
| 1227 #define SSE_CLASS_P(CLASS) \ | |
| 1228 reg_class_subset_p ((CLASS), SSE_REGS) | |
| 1229 #define MMX_CLASS_P(CLASS) \ | |
| 1230 ((CLASS) == MMX_REGS) | |
| 1231 #define MAYBE_INTEGER_CLASS_P(CLASS) \ | |
| 1232 reg_classes_intersect_p ((CLASS), GENERAL_REGS) | |
| 1233 #define MAYBE_FLOAT_CLASS_P(CLASS) \ | |
| 1234 reg_classes_intersect_p ((CLASS), FLOAT_REGS) | |
| 1235 #define MAYBE_SSE_CLASS_P(CLASS) \ | |
| 1236 reg_classes_intersect_p (SSE_REGS, (CLASS)) | |
| 1237 #define MAYBE_MMX_CLASS_P(CLASS) \ | |
| 1238 reg_classes_intersect_p (MMX_REGS, (CLASS)) | |
| 1239 | |
| 1240 #define Q_CLASS_P(CLASS) \ | |
| 1241 reg_class_subset_p ((CLASS), Q_REGS) | |
| 1242 | |
| 1243 /* Give names of register classes as strings for dump file. */ | |
| 1244 | |
| 1245 #define REG_CLASS_NAMES \ | |
| 1246 { "NO_REGS", \ | |
| 1247 "AREG", "DREG", "CREG", "BREG", \ | |
| 1248 "SIREG", "DIREG", \ | |
| 1249 "AD_REGS", \ | |
|
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1250 "CLOBBERED_REGS", \ |
| 0 | 1251 "Q_REGS", "NON_Q_REGS", \ |
| 1252 "INDEX_REGS", \ | |
| 1253 "LEGACY_REGS", \ | |
| 1254 "GENERAL_REGS", \ | |
| 1255 "FP_TOP_REG", "FP_SECOND_REG", \ | |
| 1256 "FLOAT_REGS", \ | |
| 1257 "SSE_FIRST_REG", \ | |
| 1258 "SSE_REGS", \ | |
| 1259 "MMX_REGS", \ | |
| 1260 "FP_TOP_SSE_REGS", \ | |
| 1261 "FP_SECOND_SSE_REGS", \ | |
| 1262 "FLOAT_SSE_REGS", \ | |
| 1263 "FLOAT_INT_REGS", \ | |
| 1264 "INT_SSE_REGS", \ | |
| 1265 "FLOAT_INT_SSE_REGS", \ | |
| 1266 "ALL_REGS" } | |
| 1267 | |
|
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1268 /* Define which registers fit in which classes. This is an initializer |
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1269 for a vector of HARD_REG_SET of length N_REG_CLASSES. |
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1270 |
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1271 Note that the default setting of CLOBBERED_REGS is for 32-bit; this |
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1272 is adjusted by CONDITIONAL_REGISTER_USAGE for the 64-bit ABI in effect. */ |
| 0 | 1273 |
| 1274 #define REG_CLASS_CONTENTS \ | |
| 1275 { { 0x00, 0x0 }, \ | |
| 1276 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ | |
| 1277 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ | |
| 1278 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ | |
| 1279 { 0x03, 0x0 }, /* AD_REGS */ \ | |
|
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1280 { 0x07, 0x0 }, /* CLOBBERED_REGS */ \ |
| 0 | 1281 { 0x0f, 0x0 }, /* Q_REGS */ \ |
| 1282 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ | |
| 1283 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ | |
| 1284 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ | |
| 1285 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ | |
| 1286 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ | |
| 1287 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ | |
| 1288 { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \ | |
| 1289 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ | |
| 1290 { 0xe0000000, 0x1f }, /* MMX_REGS */ \ | |
| 1291 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ | |
| 1292 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ | |
| 1293 { 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \ | |
| 1294 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ | |
| 1295 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ | |
| 1296 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ | |
| 1297 { 0xffffffff,0x1fffff } \ | |
| 1298 } | |
| 1299 | |
| 1300 /* The same information, inverted: | |
| 1301 Return the class number of the smallest class containing | |
| 1302 reg number REGNO. This could be a conditional expression | |
| 1303 or could index an array. */ | |
| 1304 | |
| 1305 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) | |
| 1306 | |
|
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1307 /* When this hook returns true for MODE, the compiler allows |
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1308 registers explicitly used in the rtl to be used as spill registers |
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1309 but prevents the compiler from extending the lifetime of these |
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1310 registers. */ |
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1311 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true |
| 0 | 1312 |
| 1313 #define QI_REG_P(X) (REG_P (X) && REGNO (X) <= BX_REG) | |
| 1314 | |
| 1315 #define GENERAL_REGNO_P(N) \ | |
| 1316 ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N)) | |
| 1317 | |
| 1318 #define GENERAL_REG_P(X) \ | |
| 1319 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) | |
| 1320 | |
| 1321 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) | |
| 1322 | |
| 1323 #define REX_INT_REGNO_P(N) \ | |
| 1324 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) | |
| 1325 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) | |
| 1326 | |
| 1327 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) | |
| 1328 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) | |
| 1329 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) | |
| 1330 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) | |
| 1331 | |
| 1332 #define X87_FLOAT_MODE_P(MODE) \ | |
| 1333 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) | |
| 1334 | |
| 1335 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) | |
| 1336 #define SSE_REGNO_P(N) \ | |
| 1337 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ | |
| 1338 || REX_SSE_REGNO_P (N)) | |
| 1339 | |
| 1340 #define REX_SSE_REGNO_P(N) \ | |
| 1341 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) | |
| 1342 | |
| 1343 #define SSE_REGNO(N) \ | |
| 1344 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) | |
| 1345 | |
| 1346 #define SSE_FLOAT_MODE_P(MODE) \ | |
| 1347 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) | |
| 1348 | |
| 1349 #define SSE_VEC_FLOAT_MODE_P(MODE) \ | |
| 1350 ((TARGET_SSE && (MODE) == V4SFmode) || (TARGET_SSE2 && (MODE) == V2DFmode)) | |
| 1351 | |
| 1352 #define AVX_FLOAT_MODE_P(MODE) \ | |
| 1353 (TARGET_AVX && ((MODE) == SFmode || (MODE) == DFmode)) | |
| 1354 | |
| 1355 #define AVX128_VEC_FLOAT_MODE_P(MODE) \ | |
| 1356 (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode)) | |
| 1357 | |
| 1358 #define AVX256_VEC_FLOAT_MODE_P(MODE) \ | |
| 1359 (TARGET_AVX && ((MODE) == V8SFmode || (MODE) == V4DFmode)) | |
| 1360 | |
| 1361 #define AVX_VEC_FLOAT_MODE_P(MODE) \ | |
| 1362 (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode \ | |
| 1363 || (MODE) == V8SFmode || (MODE) == V4DFmode)) | |
| 1364 | |
|
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1365 #define FMA4_VEC_FLOAT_MODE_P(MODE) \ |
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1366 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \ |
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1367 || (MODE) == V8SFmode || (MODE) == V4DFmode)) |
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1368 |
| 0 | 1369 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) |
| 1370 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) | |
| 1371 | |
| 1372 #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP))) | |
| 1373 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) | |
| 1374 | |
| 1375 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) | |
| 1376 | |
| 1377 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) | |
| 1378 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) | |
| 1379 | |
| 1380 /* The class value for index registers, and the one for base regs. */ | |
| 1381 | |
| 1382 #define INDEX_REG_CLASS INDEX_REGS | |
| 1383 #define BASE_REG_CLASS GENERAL_REGS | |
| 1384 | |
| 1385 /* Place additional restrictions on the register class to use when it | |
| 1386 is necessary to be able to hold a value of mode MODE in a reload | |
| 1387 register for which class CLASS would ordinarily be used. */ | |
| 1388 | |
| 1389 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ | |
| 1390 ((MODE) == QImode && !TARGET_64BIT \ | |
| 1391 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ | |
| 1392 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ | |
| 1393 ? Q_REGS : (CLASS)) | |
| 1394 | |
| 1395 /* Given an rtx X being reloaded into a reg required to be | |
| 1396 in class CLASS, return the class of reg to actually use. | |
| 1397 In general this is just CLASS; but on some machines | |
| 1398 in some cases it is preferable to use a more restrictive class. | |
| 1399 On the 80386 series, we prevent floating constants from being | |
| 1400 reloaded into floating registers (since no move-insn can do that) | |
| 1401 and we ensure that QImodes aren't reloaded into the esi or edi reg. */ | |
| 1402 | |
| 1403 /* Put float CONST_DOUBLE in the constant pool instead of fp regs. | |
| 1404 QImode must go into class Q_REGS. | |
| 1405 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and | |
| 1406 movdf to do mem-to-mem moves through integer regs. */ | |
| 1407 | |
| 1408 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
| 1409 ix86_preferred_reload_class ((X), (CLASS)) | |
| 1410 | |
| 1411 /* Discourage putting floating-point values in SSE registers unless | |
| 1412 SSE math is being used, and likewise for the 387 registers. */ | |
| 1413 | |
| 1414 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \ | |
| 1415 ix86_preferred_output_reload_class ((X), (CLASS)) | |
| 1416 | |
| 1417 /* If we are copying between general and FP registers, we need a memory | |
| 1418 location. The same is true for SSE and MMX registers. */ | |
| 1419 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ | |
| 1420 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) | |
| 1421 | |
| 1422 /* Get_secondary_mem widens integral modes to BITS_PER_WORD. | |
| 1423 There is no need to emit full 64 bit move on 64 bit targets | |
| 1424 for integral modes that can be moved using 32 bit move. */ | |
| 1425 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
| 1426 (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \ | |
| 1427 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
| 1428 : MODE) | |
| 1429 | |
| 1430 /* Return the maximum number of consecutive registers | |
| 1431 needed to represent mode MODE in a register of class CLASS. */ | |
| 1432 /* On the 80386, this is the size of MODE in words, | |
| 1433 except in the FP regs, where a single reg is always enough. */ | |
| 1434 #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
| 1435 (!MAYBE_INTEGER_CLASS_P (CLASS) \ | |
| 1436 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ | |
| 1437 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \ | |
| 1438 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
| 1439 | |
| 1440 /* A C expression whose value is nonzero if pseudos that have been | |
| 1441 assigned to registers of class CLASS would likely be spilled | |
| 1442 because registers of CLASS are needed for spill registers. | |
| 1443 | |
| 1444 The default value of this macro returns 1 if CLASS has exactly one | |
| 1445 register and zero otherwise. On most machines, this default | |
| 1446 should be used. Only define this macro to some other expression | |
| 1447 if pseudo allocated by `local-alloc.c' end up in memory because | |
| 1448 their hard registers were needed for spill registers. If this | |
| 1449 macro returns nonzero for those classes, those pseudos will only | |
| 1450 be allocated by `global.c', which knows how to reallocate the | |
| 1451 pseudo to another register. If there would not be another | |
| 1452 register available for reallocation, you should not change the | |
| 1453 definition of this macro since the only effect of such a | |
| 1454 definition would be to slow down register allocation. */ | |
| 1455 | |
| 1456 #define CLASS_LIKELY_SPILLED_P(CLASS) \ | |
| 1457 (((CLASS) == AREG) \ | |
| 1458 || ((CLASS) == DREG) \ | |
| 1459 || ((CLASS) == CREG) \ | |
| 1460 || ((CLASS) == BREG) \ | |
| 1461 || ((CLASS) == AD_REGS) \ | |
| 1462 || ((CLASS) == SIREG) \ | |
| 1463 || ((CLASS) == DIREG) \ | |
|
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1464 || ((CLASS) == SSE_FIRST_REG) \ |
| 0 | 1465 || ((CLASS) == FP_TOP_REG) \ |
| 1466 || ((CLASS) == FP_SECOND_REG)) | |
| 1467 | |
| 1468 /* Return a class of registers that cannot change FROM mode to TO mode. */ | |
| 1469 | |
| 1470 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
| 1471 ix86_cannot_change_mode_class (FROM, TO, CLASS) | |
| 1472 | |
| 1473 /* Stack layout; function entry, exit and calling. */ | |
| 1474 | |
| 1475 /* Define this if pushing a word on the stack | |
| 1476 makes the stack pointer a smaller address. */ | |
| 1477 #define STACK_GROWS_DOWNWARD | |
| 1478 | |
| 1479 /* Define this to nonzero if the nominal address of the stack frame | |
| 1480 is at the high-address end of the local variables; | |
| 1481 that is, each additional local variable allocated | |
| 1482 goes at a more negative offset in the frame. */ | |
| 1483 #define FRAME_GROWS_DOWNWARD 1 | |
| 1484 | |
| 1485 /* Offset within stack frame to start allocating local variables at. | |
| 1486 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
| 1487 first local allocated. Otherwise, it is the offset to the BEGINNING | |
| 1488 of the first local allocated. */ | |
| 1489 #define STARTING_FRAME_OFFSET 0 | |
| 1490 | |
| 1491 /* If we generate an insn to push BYTES bytes, | |
| 1492 this says how many the stack pointer really advances by. | |
| 1493 On 386, we have pushw instruction that decrements by exactly 2 no | |
| 1494 matter what the position was, there is no pushb. | |
| 1495 But as CIE data alignment factor on this arch is -4, we need to make | |
| 1496 sure all stack pointer adjustments are in multiple of 4. | |
| 1497 | |
| 1498 For 64bit ABI we round up to 8 bytes. | |
| 1499 */ | |
| 1500 | |
| 1501 #define PUSH_ROUNDING(BYTES) \ | |
| 1502 (TARGET_64BIT \ | |
| 1503 ? (((BYTES) + 7) & (-8)) \ | |
| 1504 : (((BYTES) + 3) & (-4))) | |
| 1505 | |
| 1506 /* If defined, the maximum amount of space required for outgoing arguments will | |
| 1507 be computed and placed into the variable | |
| 1508 `crtl->outgoing_args_size'. No space will be pushed onto the | |
| 1509 stack for each call; instead, the function prologue should increase the stack | |
| 1510 frame size by this amount. | |
| 1511 | |
| 1512 MS ABI seem to require 16 byte alignment everywhere except for function | |
| 1513 prologue and apilogue. This is not possible without | |
| 1514 ACCUMULATE_OUTGOING_ARGS. */ | |
| 1515 | |
| 1516 #define ACCUMULATE_OUTGOING_ARGS \ | |
| 1517 (TARGET_ACCUMULATE_OUTGOING_ARGS || ix86_cfun_abi () == MS_ABI) | |
| 1518 | |
| 1519 /* If defined, a C expression whose value is nonzero when we want to use PUSH | |
| 1520 instructions to pass outgoing arguments. */ | |
| 1521 | |
| 1522 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) | |
| 1523 | |
| 1524 /* We want the stack and args grow in opposite directions, even if | |
| 1525 PUSH_ARGS is 0. */ | |
| 1526 #define PUSH_ARGS_REVERSED 1 | |
| 1527 | |
| 1528 /* Offset of first parameter from the argument pointer register value. */ | |
| 1529 #define FIRST_PARM_OFFSET(FNDECL) 0 | |
| 1530 | |
| 1531 /* Define this macro if functions should assume that stack space has been | |
| 1532 allocated for arguments even when their values are passed in registers. | |
| 1533 | |
| 1534 The value of this macro is the size, in bytes, of the area reserved for | |
| 1535 arguments passed in registers for the function represented by FNDECL. | |
| 1536 | |
| 1537 This space can be allocated by the caller, or be a part of the | |
| 1538 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says | |
| 1539 which. */ | |
| 1540 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) | |
| 1541 | |
| 1542 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ | |
| 1543 (ix86_function_type_abi (FNTYPE) == MS_ABI) | |
| 1544 | |
| 1545 /* Value is the number of bytes of arguments automatically | |
| 1546 popped when returning from a subroutine call. | |
| 1547 FUNDECL is the declaration node of the function (as a tree), | |
| 1548 FUNTYPE is the data type of the function (as a tree), | |
| 1549 or for a library call it is an identifier node for the subroutine name. | |
| 1550 SIZE is the number of bytes of arguments passed on the stack. | |
| 1551 | |
| 1552 On the 80386, the RTD insn may be used to pop them if the number | |
| 1553 of args is fixed, but if the number is variable then the caller | |
| 1554 must pop them all. RTD can't be used for library calls now | |
| 1555 because the library is compiled with the Unix compiler. | |
| 1556 Use of RTD is a selectable option, since it is incompatible with | |
| 1557 standard Unix calling sequences. If the option is not selected, | |
| 1558 the caller must always pop the args. | |
| 1559 | |
| 1560 The attribute stdcall is equivalent to RTD on a per module basis. */ | |
| 1561 | |
| 1562 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ | |
| 1563 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) | |
| 1564 | |
| 1565 /* Define how to find the value returned by a library function | |
| 1566 assuming the value has mode MODE. */ | |
| 1567 | |
| 1568 #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) | |
| 1569 | |
| 1570 /* Define the size of the result block used for communication between | |
| 1571 untyped_call and untyped_return. The block contains a DImode value | |
| 1572 followed by the block used by fnsave and frstor. */ | |
| 1573 | |
| 1574 #define APPLY_RESULT_SIZE (8+108) | |
| 1575 | |
| 1576 /* 1 if N is a possible register number for function argument passing. */ | |
| 1577 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) | |
| 1578 | |
| 1579 /* Define a data type for recording info about an argument list | |
| 1580 during the scan of that argument list. This data type should | |
| 1581 hold all necessary information about the function itself | |
| 1582 and about the args processed so far, enough to enable macros | |
| 1583 such as FUNCTION_ARG to determine where the next arg should go. */ | |
| 1584 | |
| 1585 typedef struct ix86_args { | |
| 1586 int words; /* # words passed so far */ | |
| 1587 int nregs; /* # registers available for passing */ | |
| 1588 int regno; /* next available register number */ | |
|
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1589 int fastcall; /* fastcall or thiscall calling convention |
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1590 is used */ |
| 0 | 1591 int sse_words; /* # sse words passed so far */ |
| 1592 int sse_nregs; /* # sse registers available for passing */ | |
| 1593 int warn_avx; /* True when we want to warn about AVX ABI. */ | |
| 1594 int warn_sse; /* True when we want to warn about SSE ABI. */ | |
| 1595 int warn_mmx; /* True when we want to warn about MMX ABI. */ | |
| 1596 int sse_regno; /* next available sse register number */ | |
| 1597 int mmx_words; /* # mmx words passed so far */ | |
| 1598 int mmx_nregs; /* # mmx registers available for passing */ | |
| 1599 int mmx_regno; /* next available mmx register number */ | |
| 1600 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ | |
| 1601 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should | |
| 1602 be passed in SSE registers. Otherwise 0. */ | |
|
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1603 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise |
| 0 | 1604 MS_ABI for ms abi. */ |
| 1605 } CUMULATIVE_ARGS; | |
| 1606 | |
| 1607 /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
| 1608 for a call to a function whose data type is FNTYPE. | |
| 1609 For a library call, FNTYPE is 0. */ | |
| 1610 | |
| 1611 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ | |
| 1612 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) | |
| 1613 | |
| 1614 /* Update the data in CUM to advance over an argument | |
| 1615 of mode MODE and data type TYPE. | |
| 1616 (TYPE is null for libcalls where that information may not be available.) */ | |
| 1617 | |
| 1618 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
| 1619 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) | |
| 1620 | |
| 1621 /* Define where to put the arguments to a function. | |
| 1622 Value is zero to push the argument on the stack, | |
| 1623 or a hard register in which to store the argument. | |
| 1624 | |
| 1625 MODE is the argument's machine mode. | |
| 1626 TYPE is the data type of the argument (as a tree). | |
| 1627 This is null for libcalls where that information may | |
| 1628 not be available. | |
| 1629 CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
| 1630 the preceding args and about the function being called. | |
| 1631 NAMED is nonzero if this argument is a named parameter | |
| 1632 (otherwise it is an extra parameter matching an ellipsis). */ | |
| 1633 | |
| 1634 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
| 1635 function_arg (&(CUM), (MODE), (TYPE), (NAMED)) | |
| 1636 | |
| 1637 /* Output assembler code to FILE to increment profiler label # LABELNO | |
| 1638 for profiling a function entry. */ | |
| 1639 | |
| 1640 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) | |
| 1641 | |
| 1642 #define MCOUNT_NAME "_mcount" | |
| 1643 | |
| 1644 #define PROFILE_COUNT_REGISTER "edx" | |
| 1645 | |
| 1646 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
| 1647 the stack pointer does not matter. The value is tested only in | |
| 1648 functions that have frame pointers. | |
| 1649 No definition is equivalent to always zero. */ | |
| 1650 /* Note on the 386 it might be more efficient not to define this since | |
| 1651 we have to restore it ourselves from the frame pointer, in order to | |
| 1652 use pop */ | |
| 1653 | |
| 1654 #define EXIT_IGNORE_STACK 1 | |
| 1655 | |
| 1656 /* Output assembler code for a block containing the constant parts | |
| 1657 of a trampoline, leaving space for the variable parts. */ | |
| 1658 | |
| 1659 /* On the 386, the trampoline contains two instructions: | |
| 1660 mov #STATIC,ecx | |
| 1661 jmp FUNCTION | |
| 1662 The trampoline is generated entirely at runtime. The operand of JMP | |
| 1663 is the address of FUNCTION relative to the instruction following the | |
| 1664 JMP (which is 5 bytes long). */ | |
| 1665 | |
| 1666 /* Length in units of the trampoline for entering a nested function. */ | |
| 1667 | |
|
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1668 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10) |
| 0 | 1669 |
| 1670 /* Definitions for register eliminations. | |
| 1671 | |
| 1672 This is an array of structures. Each structure initializes one pair | |
| 1673 of eliminable registers. The "from" register number is given first, | |
| 1674 followed by "to". Eliminations of the same "from" register are listed | |
| 1675 in order of preference. | |
| 1676 | |
| 1677 There are two registers that can always be eliminated on the i386. | |
| 1678 The frame pointer and the arg pointer can be replaced by either the | |
| 1679 hard frame pointer or to the stack pointer, depending upon the | |
| 1680 circumstances. The hard frame pointer is not used before reload and | |
| 1681 so it is not eligible for elimination. */ | |
| 1682 | |
| 1683 #define ELIMINABLE_REGS \ | |
| 1684 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 1685 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
| 1686 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 1687 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ | |
| 1688 | |
| 1689 /* Define the offset between two registers, one to be eliminated, and the other | |
| 1690 its replacement, at the start of a routine. */ | |
| 1691 | |
| 1692 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
| 1693 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) | |
| 1694 | |
| 1695 /* Addressing modes, and classification of registers for them. */ | |
| 1696 | |
| 1697 /* Macros to check register numbers against specific register classes. */ | |
| 1698 | |
| 1699 /* These assume that REGNO is a hard or pseudo reg number. | |
| 1700 They give nonzero only if REGNO is a hard reg of the suitable class | |
| 1701 or a pseudo reg currently allocated to a suitable hard reg. | |
| 1702 Since they use reg_renumber, they are safe only once reg_renumber | |
| 1703 has been allocated, which happens in local-alloc.c. */ | |
| 1704 | |
| 1705 #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
| 1706 ((REGNO) < STACK_POINTER_REGNUM \ | |
| 1707 || REX_INT_REGNO_P (REGNO) \ | |
| 1708 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ | |
| 1709 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) | |
| 1710 | |
| 1711 #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
| 1712 (GENERAL_REGNO_P (REGNO) \ | |
| 1713 || (REGNO) == ARG_POINTER_REGNUM \ | |
| 1714 || (REGNO) == FRAME_POINTER_REGNUM \ | |
| 1715 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) | |
| 1716 | |
| 1717 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
| 1718 and check its validity for a certain class. | |
| 1719 We have two alternate definitions for each of them. | |
| 1720 The usual definition accepts all pseudo regs; the other rejects | |
| 1721 them unless they have been allocated suitable hard regs. | |
| 1722 The symbol REG_OK_STRICT causes the latter definition to be used. | |
| 1723 | |
| 1724 Most source files want to accept pseudo regs in the hope that | |
| 1725 they will get allocated to the class that the insn wants them to be in. | |
| 1726 Source files for reload pass need to be strict. | |
| 1727 After reload, it makes no difference, since pseudo regs have | |
| 1728 been eliminated by then. */ | |
| 1729 | |
| 1730 | |
| 1731 /* Non strict versions, pseudos are ok. */ | |
| 1732 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ | |
| 1733 (REGNO (X) < STACK_POINTER_REGNUM \ | |
| 1734 || REX_INT_REGNO_P (REGNO (X)) \ | |
| 1735 || REGNO (X) >= FIRST_PSEUDO_REGISTER) | |
| 1736 | |
| 1737 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ | |
| 1738 (GENERAL_REGNO_P (REGNO (X)) \ | |
| 1739 || REGNO (X) == ARG_POINTER_REGNUM \ | |
| 1740 || REGNO (X) == FRAME_POINTER_REGNUM \ | |
| 1741 || REGNO (X) >= FIRST_PSEUDO_REGISTER) | |
| 1742 | |
| 1743 /* Strict versions, hard registers only */ | |
| 1744 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
| 1745 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
| 1746 | |
| 1747 #ifndef REG_OK_STRICT | |
| 1748 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) | |
| 1749 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) | |
| 1750 | |
| 1751 #else | |
| 1752 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) | |
| 1753 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) | |
| 1754 #endif | |
| 1755 | |
|
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1756 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression |
| 0 | 1757 that is a valid memory address for an instruction. |
| 1758 The MODE argument is the machine mode for the MEM expression | |
| 1759 that wants to use this address. | |
| 1760 | |
|
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1761 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P, |
| 0 | 1762 except for CONSTANT_ADDRESS_P which is usually machine-independent. |
| 1763 | |
| 1764 See legitimize_pic_address in i386.c for details as to what | |
| 1765 constitutes a legitimate address when -fpic is used. */ | |
| 1766 | |
| 1767 #define MAX_REGS_PER_ADDRESS 2 | |
| 1768 | |
| 1769 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) | |
| 1770 | |
| 1771 /* Nonzero if the constant value X is a legitimate general operand. | |
| 1772 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
| 1773 | |
| 1774 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) | |
| 1775 | |
| 1776 /* If defined, a C expression to determine the base term of address X. | |
| 1777 This macro is used in only one place: `find_base_term' in alias.c. | |
| 1778 | |
| 1779 It is always safe for this macro to not be defined. It exists so | |
| 1780 that alias analysis can understand machine-dependent addresses. | |
| 1781 | |
| 1782 The typical use of this macro is to handle addresses containing | |
| 1783 a label_ref or symbol_ref within an UNSPEC. */ | |
| 1784 | |
| 1785 #define FIND_BASE_TERM(X) ix86_find_base_term (X) | |
| 1786 | |
| 1787 /* Nonzero if the constant value X is a legitimate general operand | |
| 1788 when generating PIC code. It is given that flag_pic is on and | |
| 1789 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
| 1790 | |
| 1791 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) | |
| 1792 | |
| 1793 #define SYMBOLIC_CONST(X) \ | |
| 1794 (GET_CODE (X) == SYMBOL_REF \ | |
| 1795 || GET_CODE (X) == LABEL_REF \ | |
| 1796 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
| 1797 | |
| 1798 /* Max number of args passed in registers. If this is more than 3, we will | |
| 1799 have problems with ebx (register #4), since it is a caller save register and | |
| 1800 is also used as the pic register in ELF. So for now, don't allow more than | |
| 1801 3 registers to be passed in registers. */ | |
| 1802 | |
| 1803 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ | |
| 1804 #define X86_64_REGPARM_MAX 6 | |
|
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1805 #define X86_64_MS_REGPARM_MAX 4 |
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1806 |
| 0 | 1807 #define X86_32_REGPARM_MAX 3 |
| 1808 | |
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1809 #define REGPARM_MAX \ |
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1810 (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X86_64_MS_REGPARM_MAX \ |
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1811 : X86_64_REGPARM_MAX) \ |
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1812 : X86_32_REGPARM_MAX) |
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1813 |
| 0 | 1814 #define X86_64_SSE_REGPARM_MAX 8 |
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1815 #define X86_64_MS_SSE_REGPARM_MAX 4 |
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1816 |
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1817 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0) |
| 0 | 1818 |
| 1819 #define SSE_REGPARM_MAX \ | |
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1820 (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X86_64_MS_SSE_REGPARM_MAX \ |
| 0 | 1821 : X86_64_SSE_REGPARM_MAX) \ |
| 1822 : X86_32_SSE_REGPARM_MAX) | |
| 1823 | |
| 1824 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) | |
| 1825 | |
| 1826 | |
| 1827 /* Specify the machine mode that this machine uses | |
| 1828 for the index in the tablejump instruction. */ | |
| 1829 #define CASE_VECTOR_MODE \ | |
| 1830 (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) | |
| 1831 | |
| 1832 /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
| 1833 #define DEFAULT_SIGNED_CHAR 1 | |
| 1834 | |
| 1835 /* Max number of bytes we can move from memory to memory | |
| 1836 in one reasonably fast instruction. */ | |
| 1837 #define MOVE_MAX 16 | |
| 1838 | |
| 1839 /* MOVE_MAX_PIECES is the number of bytes at a time which we can | |
| 1840 move efficiently, as opposed to MOVE_MAX which is the maximum | |
| 1841 number of bytes we can move with a single instruction. */ | |
| 1842 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) | |
| 1843 | |
| 1844 /* If a memory-to-memory move would take MOVE_RATIO or more simple | |
| 1845 move-instruction pairs, we will do a movmem or libcall instead. | |
| 1846 Increasing the value will always make code faster, but eventually | |
| 1847 incurs high cost in increased code size. | |
| 1848 | |
| 1849 If you don't define this, a reasonable default is used. */ | |
| 1850 | |
| 1851 #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) | |
| 1852 | |
| 1853 /* If a clear memory operation would take CLEAR_RATIO or more simple | |
| 1854 move-instruction sequences, we will do a clrmem or libcall instead. */ | |
| 1855 | |
| 1856 #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2) | |
| 1857 | |
| 1858 /* Define if shifts truncate the shift count | |
| 1859 which implies one can omit a sign-extension or zero-extension | |
| 1860 of a shift count. */ | |
| 1861 /* On i386, shifts do truncate the count. But bit opcodes don't. */ | |
| 1862 | |
| 1863 /* #define SHIFT_COUNT_TRUNCATED */ | |
| 1864 | |
| 1865 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
| 1866 is done just by pretending it is already truncated. */ | |
| 1867 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
| 1868 | |
| 1869 /* A macro to update M and UNSIGNEDP when an object whose type is | |
| 1870 TYPE and which has the specified mode and signedness is to be | |
| 1871 stored in a register. This macro is only called when TYPE is a | |
| 1872 scalar type. | |
| 1873 | |
| 1874 On i386 it is sometimes useful to promote HImode and QImode | |
| 1875 quantities to SImode. The choice depends on target type. */ | |
| 1876 | |
| 1877 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
| 1878 do { \ | |
| 1879 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ | |
| 1880 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ | |
| 1881 (MODE) = SImode; \ | |
| 1882 } while (0) | |
| 1883 | |
| 1884 /* Specify the machine mode that pointers have. | |
| 1885 After generation of rtl, the compiler makes no further distinction | |
| 1886 between pointers and any other objects of this machine mode. */ | |
| 1887 #define Pmode (TARGET_64BIT ? DImode : SImode) | |
| 1888 | |
| 1889 /* A function address in a call instruction | |
| 1890 is a byte address (for indexing purposes) | |
| 1891 so give the MEM rtx a byte's mode. */ | |
| 1892 #define FUNCTION_MODE QImode | |
| 1893 | |
| 1894 /* A C expression for the cost of moving data from a register in class FROM to | |
| 1895 one in class TO. The classes are expressed using the enumeration values | |
| 1896 such as `GENERAL_REGS'. A value of 2 is the default; other values are | |
| 1897 interpreted relative to that. | |
| 1898 | |
| 1899 It is not required that the cost always equal 2 when FROM is the same as TO; | |
| 1900 on some machines it is expensive to move between registers if they are not | |
| 1901 general registers. */ | |
| 1902 | |
| 1903 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ | |
| 1904 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) | |
| 1905 | |
| 1906 /* A C expression for the cost of moving data of mode M between a | |
| 1907 register and memory. A value of 2 is the default; this cost is | |
| 1908 relative to those in `REGISTER_MOVE_COST'. | |
| 1909 | |
| 1910 If moving between registers and memory is more expensive than | |
| 1911 between two registers, you should define this macro to express the | |
| 1912 relative cost. */ | |
| 1913 | |
| 1914 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \ | |
| 1915 ix86_memory_move_cost ((MODE), (CLASS), (IN)) | |
| 1916 | |
| 1917 /* A C expression for the cost of a branch instruction. A value of 1 | |
| 1918 is the default; other values are interpreted relative to that. */ | |
| 1919 | |
| 1920 #define BRANCH_COST(speed_p, predictable_p) \ | |
| 1921 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) | |
| 1922 | |
| 1923 /* Define this macro as a C expression which is nonzero if accessing | |
| 1924 less than a word of memory (i.e. a `char' or a `short') is no | |
| 1925 faster than accessing a word of memory, i.e., if such access | |
| 1926 require more than one instruction or if there is no difference in | |
| 1927 cost between byte and (aligned) word loads. | |
| 1928 | |
| 1929 When this macro is not defined, the compiler will access a field by | |
| 1930 finding the smallest containing object; when it is defined, a | |
| 1931 fullword load will be used if alignment permits. Unless bytes | |
| 1932 accesses are faster than word accesses, using word accesses is | |
| 1933 preferable since it may eliminate subsequent memory access if | |
| 1934 subsequent accesses occur to other fields in the same word of the | |
| 1935 structure, but to different bytes. */ | |
| 1936 | |
| 1937 #define SLOW_BYTE_ACCESS 0 | |
| 1938 | |
| 1939 /* Nonzero if access to memory by shorts is slow and undesirable. */ | |
| 1940 #define SLOW_SHORT_ACCESS 0 | |
| 1941 | |
| 1942 /* Define this macro to be the value 1 if unaligned accesses have a | |
| 1943 cost many times greater than aligned accesses, for example if they | |
| 1944 are emulated in a trap handler. | |
| 1945 | |
| 1946 When this macro is nonzero, the compiler will act as if | |
| 1947 `STRICT_ALIGNMENT' were nonzero when generating code for block | |
| 1948 moves. This can cause significantly more instructions to be | |
| 1949 produced. Therefore, do not set this macro nonzero if unaligned | |
| 1950 accesses only add a cycle or two to the time for a memory access. | |
| 1951 | |
| 1952 If the value of this macro is always zero, it need not be defined. */ | |
| 1953 | |
| 1954 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ | |
| 1955 | |
| 1956 /* Define this macro if it is as good or better to call a constant | |
| 1957 function address than to call an address kept in a register. | |
| 1958 | |
| 1959 Desirable on the 386 because a CALL with a constant address is | |
| 1960 faster than one with a register address. */ | |
| 1961 | |
| 1962 #define NO_FUNCTION_CSE | |
| 1963 | |
| 1964 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
| 1965 return the mode to be used for the comparison. | |
| 1966 | |
| 1967 For floating-point equality comparisons, CCFPEQmode should be used. | |
| 1968 VOIDmode should be used in all other cases. | |
| 1969 | |
| 1970 For integer comparisons against zero, reduce to CCNOmode or CCZmode if | |
| 1971 possible, to allow for more combinations. */ | |
| 1972 | |
| 1973 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) | |
| 1974 | |
| 1975 /* Return nonzero if MODE implies a floating point inequality can be | |
| 1976 reversed. */ | |
| 1977 | |
| 1978 #define REVERSIBLE_CC_MODE(MODE) 1 | |
| 1979 | |
| 1980 /* A C expression whose value is reversed condition code of the CODE for | |
| 1981 comparison done in CC_MODE mode. */ | |
| 1982 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) | |
| 1983 | |
| 1984 | |
| 1985 /* Control the assembler format that we output, to the extent | |
| 1986 this does not vary between assemblers. */ | |
| 1987 | |
| 1988 /* How to refer to registers in assembler output. | |
| 1989 This sequence is indexed by compiler's hard-register-number (see above). */ | |
| 1990 | |
| 1991 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". | |
| 1992 For non floating point regs, the following are the HImode names. | |
| 1993 | |
| 1994 For float regs, the stack top is sometimes referred to as "%st(0)" | |
| 1995 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */ | |
| 1996 | |
| 1997 #define HI_REGISTER_NAMES \ | |
| 1998 {"ax","dx","cx","bx","si","di","bp","sp", \ | |
| 1999 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ | |
| 2000 "argp", "flags", "fpsr", "fpcr", "frame", \ | |
| 2001 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ | |
| 2002 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ | |
| 2003 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
| 2004 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} | |
| 2005 | |
| 2006 #define REGISTER_NAMES HI_REGISTER_NAMES | |
| 2007 | |
| 2008 /* Table of additional register names to use in user input. */ | |
| 2009 | |
| 2010 #define ADDITIONAL_REGISTER_NAMES \ | |
| 2011 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ | |
| 2012 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ | |
| 2013 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ | |
| 2014 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ | |
| 2015 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ | |
| 2016 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } } | |
| 2017 | |
| 2018 /* Note we are omitting these since currently I don't know how | |
| 2019 to get gcc to use these, since they want the same but different | |
| 2020 number as al, and ax. | |
| 2021 */ | |
| 2022 | |
| 2023 #define QI_REGISTER_NAMES \ | |
| 2024 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} | |
| 2025 | |
| 2026 /* These parallel the array above, and can be used to access bits 8:15 | |
| 2027 of regs 0 through 3. */ | |
| 2028 | |
| 2029 #define QI_HIGH_REGISTER_NAMES \ | |
| 2030 {"ah", "dh", "ch", "bh", } | |
| 2031 | |
| 2032 /* How to renumber registers for dbx and gdb. */ | |
| 2033 | |
| 2034 #define DBX_REGISTER_NUMBER(N) \ | |
| 2035 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) | |
| 2036 | |
| 2037 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
| 2038 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; | |
| 2039 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
| 2040 | |
| 2041 /* Before the prologue, RA is at 0(%esp). */ | |
| 2042 #define INCOMING_RETURN_ADDR_RTX \ | |
| 2043 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) | |
| 2044 | |
| 2045 /* After the prologue, RA is at -4(AP) in the current frame. */ | |
| 2046 #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
| 2047 ((COUNT) == 0 \ | |
| 2048 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ | |
| 2049 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) | |
| 2050 | |
| 2051 /* PC is dbx register 8; let's use that column for RA. */ | |
| 2052 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) | |
| 2053 | |
| 2054 /* Before the prologue, the top of the frame is at 4(%esp). */ | |
| 2055 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD | |
| 2056 | |
| 2057 /* Describe how we implement __builtin_eh_return. */ | |
| 2058 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) | |
| 2059 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) | |
| 2060 | |
| 2061 | |
| 2062 /* Select a format to encode pointers in exception handling data. CODE | |
| 2063 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
| 2064 true if the symbol may be affected by dynamic relocations. | |
| 2065 | |
| 2066 ??? All x86 object file formats are capable of representing this. | |
| 2067 After all, the relocation needed is the same as for the call insn. | |
| 2068 Whether or not a particular assembler allows us to enter such, I | |
| 2069 guess we'll have to see. */ | |
| 2070 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
| 2071 asm_preferred_eh_data_format ((CODE), (GLOBAL)) | |
| 2072 | |
| 2073 /* This is how to output an insn to push a register on the stack. | |
| 2074 It need not be very fast code. */ | |
| 2075 | |
| 2076 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ | |
| 2077 do { \ | |
| 2078 if (TARGET_64BIT) \ | |
| 2079 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ | |
| 2080 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
| 2081 else \ | |
| 2082 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
| 2083 } while (0) | |
| 2084 | |
| 2085 /* This is how to output an insn to pop a register from the stack. | |
| 2086 It need not be very fast code. */ | |
| 2087 | |
| 2088 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ | |
| 2089 do { \ | |
| 2090 if (TARGET_64BIT) \ | |
| 2091 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ | |
| 2092 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
| 2093 else \ | |
| 2094 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
| 2095 } while (0) | |
| 2096 | |
| 2097 /* This is how to output an element of a case-vector that is absolute. */ | |
| 2098 | |
| 2099 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
| 2100 ix86_output_addr_vec_elt ((FILE), (VALUE)) | |
| 2101 | |
| 2102 /* This is how to output an element of a case-vector that is relative. */ | |
| 2103 | |
| 2104 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
| 2105 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) | |
| 2106 | |
| 2107 /* When we see %v, we will print the 'v' prefix if TARGET_AVX is | |
| 2108 true. */ | |
| 2109 | |
| 2110 #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ | |
| 2111 { \ | |
| 2112 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ | |
| 2113 { \ | |
| 2114 if (TARGET_AVX) \ | |
| 2115 (PTR) += 1; \ | |
| 2116 else \ | |
| 2117 (PTR) += 2; \ | |
| 2118 } \ | |
| 2119 } | |
| 2120 | |
| 2121 /* A C statement or statements which output an assembler instruction | |
| 2122 opcode to the stdio stream STREAM. The macro-operand PTR is a | |
| 2123 variable of type `char *' which points to the opcode name in | |
| 2124 its "internal" form--the form that is written in the machine | |
| 2125 description. */ | |
| 2126 | |
| 2127 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ | |
| 2128 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) | |
| 2129 | |
|
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2130 /* A C statement to output to the stdio stream FILE an assembler |
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2131 command to pad the location counter to a multiple of 1<<LOG |
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2132 bytes if it is within MAX_SKIP bytes. */ |
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2133 |
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2134 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN |
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2135 #undef ASM_OUTPUT_MAX_SKIP_PAD |
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2136 #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \ |
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2137 if ((LOG) != 0) \ |
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2138 { \ |
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2139 if ((MAX_SKIP) == 0) \ |
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2140 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ |
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2141 else \ |
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2142 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ |
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2143 } |
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2144 #endif |
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2145 |
| 0 | 2146 /* Under some conditions we need jump tables in the text section, |
| 2147 because the assembler cannot handle label differences between | |
| 2148 sections. This is the case for x86_64 on Mach-O for example. */ | |
| 2149 | |
| 2150 #define JUMP_TABLES_IN_TEXT_SECTION \ | |
| 2151 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ | |
| 2152 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) | |
| 2153 | |
| 2154 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, | |
| 2155 and switch back. For x86 we do this only to save a few bytes that | |
| 2156 would otherwise be unused in the text section. */ | |
|
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2157 #define CRT_MKSTR2(VAL) #VAL |
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2158 #define CRT_MKSTR(x) CRT_MKSTR2(x) |
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2159 |
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2160 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ |
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2161 asm (SECTION_OP "\n\t" \ |
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2162 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \ |
| 0 | 2163 TEXT_SECTION_ASM_OP); |
| 2164 | |
| 2165 /* Print operand X (an rtx) in assembler syntax to file FILE. | |
| 2166 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
| 2167 Effect of various CODE letters is described in i386.c near | |
| 2168 print_operand function. */ | |
| 2169 | |
| 2170 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ | |
| 2171 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&' || (CODE) == ';') | |
| 2172 | |
| 2173 #define PRINT_OPERAND(FILE, X, CODE) \ | |
| 2174 print_operand ((FILE), (X), (CODE)) | |
| 2175 | |
| 2176 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
| 2177 print_operand_address ((FILE), (ADDR)) | |
| 2178 | |
| 2179 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ | |
| 2180 do { \ | |
| 2181 if (! output_addr_const_extra (FILE, (X))) \ | |
| 2182 goto FAIL; \ | |
| 2183 } while (0); | |
| 2184 | |
| 2185 /* Which processor to schedule for. The cpu attribute defines a list that | |
| 2186 mirrors this list, so changes to i386.md must be made at the same time. */ | |
| 2187 | |
| 2188 enum processor_type | |
| 2189 { | |
| 2190 PROCESSOR_I386 = 0, /* 80386 */ | |
| 2191 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ | |
| 2192 PROCESSOR_PENTIUM, | |
| 2193 PROCESSOR_PENTIUMPRO, | |
| 2194 PROCESSOR_GEODE, | |
| 2195 PROCESSOR_K6, | |
| 2196 PROCESSOR_ATHLON, | |
| 2197 PROCESSOR_PENTIUM4, | |
| 2198 PROCESSOR_K8, | |
| 2199 PROCESSOR_NOCONA, | |
| 2200 PROCESSOR_CORE2, | |
| 2201 PROCESSOR_GENERIC32, | |
| 2202 PROCESSOR_GENERIC64, | |
| 2203 PROCESSOR_AMDFAM10, | |
|
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2204 PROCESSOR_BDVER1, |
|
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2205 PROCESSOR_ATOM, |
| 0 | 2206 PROCESSOR_max |
| 2207 }; | |
| 2208 | |
| 2209 extern enum processor_type ix86_tune; | |
| 2210 extern enum processor_type ix86_arch; | |
| 2211 | |
| 2212 enum fpmath_unit | |
| 2213 { | |
| 2214 FPMATH_387 = 1, | |
| 2215 FPMATH_SSE = 2 | |
| 2216 }; | |
| 2217 | |
| 2218 extern enum fpmath_unit ix86_fpmath; | |
| 2219 | |
| 2220 enum tls_dialect | |
| 2221 { | |
| 2222 TLS_DIALECT_GNU, | |
| 2223 TLS_DIALECT_GNU2, | |
| 2224 TLS_DIALECT_SUN | |
| 2225 }; | |
| 2226 | |
| 2227 extern enum tls_dialect ix86_tls_dialect; | |
| 2228 | |
| 2229 enum cmodel { | |
| 2230 CM_32, /* The traditional 32-bit ABI. */ | |
| 2231 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ | |
| 2232 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ | |
| 2233 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ | |
| 2234 CM_LARGE, /* No assumptions. */ | |
| 2235 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */ | |
| 2236 CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */ | |
| 2237 CM_LARGE_PIC /* No assumptions. */ | |
| 2238 }; | |
| 2239 | |
| 2240 extern enum cmodel ix86_cmodel; | |
| 2241 | |
| 2242 /* Size of the RED_ZONE area. */ | |
| 2243 #define RED_ZONE_SIZE 128 | |
| 2244 /* Reserved area of the red zone for temporaries. */ | |
| 2245 #define RED_ZONE_RESERVE 8 | |
| 2246 | |
| 2247 enum asm_dialect { | |
| 2248 ASM_ATT, | |
| 2249 ASM_INTEL | |
| 2250 }; | |
| 2251 | |
| 2252 extern enum asm_dialect ix86_asm_dialect; | |
| 2253 extern unsigned int ix86_preferred_stack_boundary; | |
| 2254 extern unsigned int ix86_incoming_stack_boundary; | |
| 2255 extern int ix86_branch_cost, ix86_section_threshold; | |
| 2256 | |
| 2257 /* Smallest class containing REGNO. */ | |
| 2258 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; | |
| 2259 | |
| 2260 extern rtx ix86_compare_op0; /* operand 0 for comparisons */ | |
| 2261 extern rtx ix86_compare_op1; /* operand 1 for comparisons */ | |
|
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2262 |
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2263 enum ix86_fpcmp_strategy { |
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2264 IX86_FPCMP_SAHF, |
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2265 IX86_FPCMP_COMI, |
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2266 IX86_FPCMP_ARITH |
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2267 }; |
| 0 | 2268 |
| 2269 /* To properly truncate FP values into integers, we need to set i387 control | |
| 2270 word. We can't emit proper mode switching code before reload, as spills | |
| 2271 generated by reload may truncate values incorrectly, but we still can avoid | |
| 2272 redundant computation of new control word by the mode switching pass. | |
| 2273 The fldcw instructions are still emitted redundantly, but this is probably | |
| 2274 not going to be noticeable problem, as most CPUs do have fast path for | |
| 2275 the sequence. | |
| 2276 | |
| 2277 The machinery is to emit simple truncation instructions and split them | |
| 2278 before reload to instructions having USEs of two memory locations that | |
| 2279 are filled by this code to old and new control word. | |
| 2280 | |
| 2281 Post-reload pass may be later used to eliminate the redundant fildcw if | |
| 2282 needed. */ | |
| 2283 | |
| 2284 enum ix86_entity | |
| 2285 { | |
| 2286 I387_TRUNC = 0, | |
| 2287 I387_FLOOR, | |
| 2288 I387_CEIL, | |
| 2289 I387_MASK_PM, | |
| 2290 MAX_386_ENTITIES | |
| 2291 }; | |
| 2292 | |
| 2293 enum ix86_stack_slot | |
| 2294 { | |
| 2295 SLOT_VIRTUAL = 0, | |
| 2296 SLOT_TEMP, | |
| 2297 SLOT_CW_STORED, | |
| 2298 SLOT_CW_TRUNC, | |
| 2299 SLOT_CW_FLOOR, | |
| 2300 SLOT_CW_CEIL, | |
| 2301 SLOT_CW_MASK_PM, | |
| 2302 MAX_386_STACK_LOCALS | |
| 2303 }; | |
| 2304 | |
| 2305 /* Define this macro if the port needs extra instructions inserted | |
| 2306 for mode switching in an optimizing compilation. */ | |
| 2307 | |
| 2308 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ | |
| 2309 ix86_optimize_mode_switching[(ENTITY)] | |
| 2310 | |
| 2311 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as | |
| 2312 initializer for an array of integers. Each initializer element N | |
| 2313 refers to an entity that needs mode switching, and specifies the | |
| 2314 number of different modes that might need to be set for this | |
| 2315 entity. The position of the initializer in the initializer - | |
| 2316 starting counting at zero - determines the integer that is used to | |
| 2317 refer to the mode-switched entity in question. */ | |
| 2318 | |
| 2319 #define NUM_MODES_FOR_MODE_SWITCHING \ | |
| 2320 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } | |
| 2321 | |
| 2322 /* ENTITY is an integer specifying a mode-switched entity. If | |
| 2323 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to | |
| 2324 return an integer value not larger than the corresponding element | |
| 2325 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY | |
| 2326 must be switched into prior to the execution of INSN. */ | |
| 2327 | |
| 2328 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I)) | |
| 2329 | |
| 2330 /* This macro specifies the order in which modes for ENTITY are | |
| 2331 processed. 0 is the highest priority. */ | |
| 2332 | |
| 2333 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) | |
| 2334 | |
| 2335 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE | |
| 2336 is the set of hard registers live at the point where the insn(s) | |
| 2337 are to be inserted. */ | |
| 2338 | |
| 2339 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ | |
| 2340 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \ | |
| 2341 ? emit_i387_cw_initialization (MODE), 0 \ | |
| 2342 : 0) | |
| 2343 | |
| 2344 | |
| 2345 /* Avoid renaming of stack registers, as doing so in combination with | |
| 2346 scheduling just increases amount of live registers at time and in | |
| 2347 the turn amount of fxch instructions needed. | |
| 2348 | |
| 2349 ??? Maybe Pentium chips benefits from renaming, someone can try.... */ | |
| 2350 | |
| 2351 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ | |
| 2352 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG)) | |
| 2353 | |
| 2354 | |
| 2355 #define FASTCALL_PREFIX '@' | |
| 2356 | |
|
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2357 /* Machine specific CFA tracking during prologue/epilogue generation. */ |
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2358 |
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2359 #ifndef USED_FOR_TARGET |
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2360 struct GTY(()) machine_cfa_state |
| 0 | 2361 { |
|
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2362 rtx reg; |
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2363 HOST_WIDE_INT offset; |
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2364 }; |
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2365 |
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2366 struct GTY(()) machine_function { |
| 0 | 2367 struct stack_local_entry *stack_locals; |
| 2368 const char *some_ld_name; | |
| 2369 int varargs_gpr_size; | |
| 2370 int varargs_fpr_size; | |
| 2371 int optimize_mode_switching[MAX_386_ENTITIES]; | |
|
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2372 |
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2373 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE |
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2374 has been computed for. */ |
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2375 int use_fast_prologue_epilogue_nregs; |
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2376 |
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2377 /* The CFA state at the end of the prologue. */ |
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2378 struct machine_cfa_state cfa; |
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2379 |
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2380 /* This value is used for amd64 targets and specifies the current abi |
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2381 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ |
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2382 enum calling_abi call_abi; |
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2383 |
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2384 /* Nonzero if the function accesses a previous frame. */ |
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2385 BOOL_BITFIELD accesses_prev_frame : 1; |
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2386 |
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2387 /* Nonzero if the function requires a CLD in the prologue. */ |
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2388 BOOL_BITFIELD needs_cld : 1; |
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2389 |
| 0 | 2390 /* Set by ix86_compute_frame_layout and used by prologue/epilogue |
| 2391 expander to determine the style used. */ | |
|
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2392 BOOL_BITFIELD use_fast_prologue_epilogue : 1; |
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2393 |
| 0 | 2394 /* If true, the current function needs the default PIC register, not |
| 2395 an alternate register (on x86) and must not use the red zone (on | |
| 2396 x86_64), even if it's a leaf function. We don't want the | |
| 2397 function to be regarded as non-leaf because TLS calls need not | |
| 2398 affect register allocation. This flag is set when a TLS call | |
| 2399 instruction is expanded within a function, and never reset, even | |
| 2400 if all such instructions are optimized away. Use the | |
| 2401 ix86_current_function_calls_tls_descriptor macro for a better | |
| 2402 approximation. */ | |
|
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2403 BOOL_BITFIELD tls_descriptor_call_expanded_p : 1; |
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2404 |
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2405 /* If true, the current function has a STATIC_CHAIN is placed on the |
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2406 stack below the return address. */ |
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2407 BOOL_BITFIELD static_chain_on_stack : 1; |
| 0 | 2408 }; |
|
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2409 #endif |
| 0 | 2410 |
| 2411 #define ix86_stack_locals (cfun->machine->stack_locals) | |
| 2412 #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) | |
| 2413 #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) | |
| 2414 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) | |
| 2415 #define ix86_current_function_needs_cld (cfun->machine->needs_cld) | |
| 2416 #define ix86_tls_descriptor_calls_expanded_in_cfun \ | |
| 2417 (cfun->machine->tls_descriptor_call_expanded_p) | |
| 2418 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS | |
| 2419 calls are optimized away, we try to detect cases in which it was | |
| 2420 optimized away. Since such instructions (use (reg REG_SP)), we can | |
| 2421 verify whether there's any such instruction live by testing that | |
| 2422 REG_SP is live. */ | |
| 2423 #define ix86_current_function_calls_tls_descriptor \ | |
| 2424 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) | |
|
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2425 #define ix86_cfa_state (&cfun->machine->cfa) |
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2426 #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack) |
| 0 | 2427 |
| 2428 /* Control behavior of x86_file_start. */ | |
| 2429 #define X86_FILE_START_VERSION_DIRECTIVE false | |
| 2430 #define X86_FILE_START_FLTUSED false | |
| 2431 | |
| 2432 /* Flag to mark data that is in the large address area. */ | |
| 2433 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) | |
| 2434 #define SYMBOL_REF_FAR_ADDR_P(X) \ | |
| 2435 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) | |
| 2436 | |
| 2437 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to | |
| 2438 have defined always, to avoid ifdefing. */ | |
| 2439 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) | |
| 2440 #define SYMBOL_REF_DLLIMPORT_P(X) \ | |
| 2441 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) | |
| 2442 | |
| 2443 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) | |
| 2444 #define SYMBOL_REF_DLLEXPORT_P(X) \ | |
| 2445 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) | |
| 2446 | |
| 2447 /* Model costs for vectorizer. */ | |
| 2448 | |
| 2449 /* Cost of conditional branch. */ | |
| 2450 #undef TARG_COND_BRANCH_COST | |
| 2451 #define TARG_COND_BRANCH_COST ix86_cost->branch_cost | |
| 2452 | |
| 2453 /* Enum through the target specific extra va_list types. | |
| 2454 Please, do not iterate the base va_list type name. */ | |
| 2455 #define TARGET_ENUM_VA_LIST(IDX, PNAME, PTYPE) \ | |
| 2456 (TARGET_64BIT ? ix86_enum_va_list (IDX, PNAME, PTYPE) : 0) | |
| 2457 | |
| 2458 /* Cost of any scalar operation, excluding load and store. */ | |
| 2459 #undef TARG_SCALAR_STMT_COST | |
| 2460 #define TARG_SCALAR_STMT_COST ix86_cost->scalar_stmt_cost | |
| 2461 | |
| 2462 /* Cost of scalar load. */ | |
| 2463 #undef TARG_SCALAR_LOAD_COST | |
| 2464 #define TARG_SCALAR_LOAD_COST ix86_cost->scalar_load_cost | |
| 2465 | |
| 2466 /* Cost of scalar store. */ | |
| 2467 #undef TARG_SCALAR_STORE_COST | |
| 2468 #define TARG_SCALAR_STORE_COST ix86_cost->scalar_store_cost | |
| 2469 | |
| 2470 /* Cost of any vector operation, excluding load, store or vector to scalar | |
| 2471 operation. */ | |
| 2472 #undef TARG_VEC_STMT_COST | |
| 2473 #define TARG_VEC_STMT_COST ix86_cost->vec_stmt_cost | |
| 2474 | |
| 2475 /* Cost of vector to scalar operation. */ | |
| 2476 #undef TARG_VEC_TO_SCALAR_COST | |
| 2477 #define TARG_VEC_TO_SCALAR_COST ix86_cost->vec_to_scalar_cost | |
| 2478 | |
| 2479 /* Cost of scalar to vector operation. */ | |
| 2480 #undef TARG_SCALAR_TO_VEC_COST | |
| 2481 #define TARG_SCALAR_TO_VEC_COST ix86_cost->scalar_to_vec_cost | |
| 2482 | |
| 2483 /* Cost of aligned vector load. */ | |
| 2484 #undef TARG_VEC_LOAD_COST | |
| 2485 #define TARG_VEC_LOAD_COST ix86_cost->vec_align_load_cost | |
| 2486 | |
| 2487 /* Cost of misaligned vector load. */ | |
| 2488 #undef TARG_VEC_UNALIGNED_LOAD_COST | |
| 2489 #define TARG_VEC_UNALIGNED_LOAD_COST ix86_cost->vec_unalign_load_cost | |
| 2490 | |
| 2491 /* Cost of vector store. */ | |
| 2492 #undef TARG_VEC_STORE_COST | |
| 2493 #define TARG_VEC_STORE_COST ix86_cost->vec_store_cost | |
| 2494 | |
| 2495 /* Cost of conditional taken branch for vectorizer cost model. */ | |
| 2496 #undef TARG_COND_TAKEN_BRANCH_COST | |
| 2497 #define TARG_COND_TAKEN_BRANCH_COST ix86_cost->cond_taken_branch_cost | |
| 2498 | |
| 2499 /* Cost of conditional not taken branch for vectorizer cost model. */ | |
| 2500 #undef TARG_COND_NOT_TAKEN_BRANCH_COST | |
| 2501 #define TARG_COND_NOT_TAKEN_BRANCH_COST ix86_cost->cond_not_taken_branch_cost | |
| 2502 | |
| 2503 /* | |
| 2504 Local variables: | |
| 2505 version-control: t | |
| 2506 End: | |
| 2507 */ |