Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/sh/sh.opt @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
| author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 22 Mar 2011 17:18:12 +0900 |
| parents | b7f97abdc517 |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
| 0 | 1 ; Options for the SH port of the compiler. |
| 2 | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
|
3 ; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010 |
|
f6334be47118
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parents:
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4 ; Free Software Foundation, Inc. |
| 0 | 5 ; |
| 6 ; This file is part of GCC. | |
| 7 ; | |
| 8 ; GCC is free software; you can redistribute it and/or modify it under | |
| 9 ; the terms of the GNU General Public License as published by the Free | |
| 10 ; Software Foundation; either version 3, or (at your option) any later | |
| 11 ; version. | |
| 12 ; | |
| 13 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
| 14 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 15 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 16 ; for more details. | |
| 17 ; | |
| 18 ; You should have received a copy of the GNU General Public License | |
| 19 ; along with GCC; see the file COPYING3. If not see | |
| 20 ; <http://www.gnu.org/licenses/>. | |
| 21 | |
| 22 ;; Used for various architecture options. | |
| 23 Mask(SH_E) | |
| 24 | |
| 25 ;; Set if the default precision of th FPU is single. | |
| 26 Mask(FPU_SINGLE) | |
| 27 | |
| 28 ;; Set if we should generate code using type 2A insns. | |
| 29 Mask(HARD_SH2A) | |
| 30 | |
| 31 ;; Set if we should generate code using type 2A DF insns. | |
| 32 Mask(HARD_SH2A_DOUBLE) | |
| 33 | |
| 34 ;; Set if compiling for SH4 hardware (to be used for insn costs etc.) | |
| 35 Mask(HARD_SH4) | |
| 36 | |
| 37 ;; Set if we should generate code for a SH5 CPU (either ISA). | |
| 38 Mask(SH5) | |
| 39 | |
| 40 ;; Set if we should save all target registers. | |
| 41 Mask(SAVE_ALL_TARGET_REGS) | |
| 42 | |
| 43 m1 | |
| 44 Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1) | |
| 45 Generate SH1 code | |
| 46 | |
| 47 m2 | |
| 48 Target RejectNegative Mask(SH2) Condition(SUPPORT_SH2) | |
| 49 Generate SH2 code | |
| 50 | |
| 51 m2a | |
| 52 Target RejectNegative Condition(SUPPORT_SH2A) | |
|
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53 Generate default double-precision SH2a-FPU code |
| 0 | 54 |
| 55 m2a-nofpu | |
| 56 Target RejectNegative Condition(SUPPORT_SH2A_NOFPU) | |
| 57 Generate SH2a FPU-less code | |
| 58 | |
| 59 m2a-single | |
| 60 Target RejectNegative Condition(SUPPORT_SH2A_SINGLE) | |
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61 Generate default single-precision SH2a-FPU code |
| 0 | 62 |
| 63 m2a-single-only | |
| 64 Target RejectNegative Condition(SUPPORT_SH2A_SINGLE_ONLY) | |
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65 Generate only single-precision SH2a-FPU code |
| 0 | 66 |
| 67 m2e | |
| 68 Target RejectNegative Condition(SUPPORT_SH2E) | |
| 69 Generate SH2e code | |
| 70 | |
| 71 m3 | |
| 72 Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) | |
| 73 Generate SH3 code | |
| 74 | |
| 75 m3e | |
| 76 Target RejectNegative Condition(SUPPORT_SH3E) | |
| 77 Generate SH3e code | |
| 78 | |
| 79 m4 | |
| 80 Target RejectNegative Mask(SH4) Condition(SUPPORT_SH4) | |
| 81 Generate SH4 code | |
| 82 | |
| 83 m4-100 | |
| 84 Target RejectNegative Condition(SUPPORT_SH4) | |
| 85 Generate SH4-100 code | |
| 86 | |
| 87 m4-200 | |
| 88 Target RejectNegative Condition(SUPPORT_SH4) | |
| 89 Generate SH4-200 code | |
| 90 | |
| 91 ;; TARGET_SH4_300 indicates if we have the ST40-300 instruction set and | |
| 92 ;; pipeline - irrespective of ABI. | |
| 93 m4-300 | |
| 94 Target RejectNegative Condition(SUPPORT_SH4) Var(TARGET_SH4_300) | |
| 95 Generate SH4-300 code | |
| 96 | |
| 97 m4-nofpu | |
| 98 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) | |
| 99 Generate SH4 FPU-less code | |
| 100 | |
| 101 m4-100-nofpu | |
| 102 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) | |
| 103 Generate SH4-100 FPU-less code | |
| 104 | |
| 105 m4-200-nofpu | |
| 106 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) | |
| 107 Generate SH4-200 FPU-less code | |
| 108 | |
| 109 m4-300-nofpu | |
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67
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
110 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) |
| 0 | 111 Generate SH4-300 FPU-less code |
| 112 | |
| 113 m4-340 | |
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67
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
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114 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) |
| 0 | 115 Generate code for SH4 340 series (MMU/FPU-less) |
| 116 ;; passes -isa=sh4-nommu-nofpu to the assembler. | |
| 117 | |
| 118 m4-400 | |
| 119 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) | |
| 120 Generate code for SH4 400 series (MMU/FPU-less) | |
| 121 ;; passes -isa=sh4-nommu-nofpu to the assembler. | |
| 122 | |
| 123 m4-500 | |
| 124 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) | |
| 125 Generate code for SH4 500 series (FPU-less). | |
| 126 ;; passes -isa=sh4-nofpu to the assembler. | |
| 127 | |
| 128 m4-single | |
| 129 Target RejectNegative Condition(SUPPORT_SH4_SINGLE) | |
| 130 Generate default single-precision SH4 code | |
| 131 | |
| 132 m4-100-single | |
| 133 Target RejectNegative Condition(SUPPORT_SH4_SINGLE) | |
| 134 Generate default single-precision SH4-100 code | |
| 135 | |
| 136 m4-200-single | |
| 137 Target RejectNegative Condition(SUPPORT_SH4_SINGLE) | |
| 138 Generate default single-precision SH4-200 code | |
| 139 | |
| 140 m4-300-single | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
141 Target RejectNegative Condition(SUPPORT_SH4_SINGLE) Var(TARGET_SH4_300) |
| 0 | 142 Generate default single-precision SH4-300 code |
| 143 | |
| 144 m4-single-only | |
| 145 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) | |
| 146 Generate only single-precision SH4 code | |
| 147 | |
| 148 m4-100-single-only | |
| 149 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) | |
| 150 Generate only single-precision SH4-100 code | |
| 151 | |
| 152 m4-200-single-only | |
| 153 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) | |
| 154 Generate only single-precision SH4-200 code | |
| 155 | |
| 156 m4-300-single-only | |
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67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
157 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Var(TARGET_SH4_300) |
| 0 | 158 Generate only single-precision SH4-300 code |
| 159 | |
| 160 m4a | |
| 161 Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A) | |
| 162 Generate SH4a code | |
| 163 | |
| 164 m4a-nofpu | |
| 165 Target RejectNegative Condition(SUPPORT_SH4A_NOFPU) | |
| 166 Generate SH4a FPU-less code | |
| 167 | |
| 168 m4a-single | |
| 169 Target RejectNegative Condition(SUPPORT_SH4A_SINGLE) | |
| 170 Generate default single-precision SH4a code | |
| 171 | |
| 172 m4a-single-only | |
| 173 Target RejectNegative Condition(SUPPORT_SH4A_SINGLE_ONLY) | |
| 174 Generate only single-precision SH4a code | |
| 175 | |
| 176 m4al | |
| 177 Target RejectNegative Condition(SUPPORT_SH4AL) | |
| 178 Generate SH4al-dsp code | |
| 179 | |
| 180 m5-32media | |
| 181 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA) | |
| 182 Generate 32-bit SHmedia code | |
| 183 | |
| 184 m5-32media-nofpu | |
| 185 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU) | |
| 186 Generate 32-bit FPU-less SHmedia code | |
| 187 | |
| 188 m5-64media | |
| 189 Target RejectNegative Condition(SUPPORT_SH5_64MEDIA) | |
| 190 Generate 64-bit SHmedia code | |
| 191 | |
| 192 m5-64media-nofpu | |
| 193 Target RejectNegative Condition(SUPPORT_SH5_64MEDIA_NOFPU) | |
| 194 Generate 64-bit FPU-less SHmedia code | |
| 195 | |
| 196 m5-compact | |
| 197 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA) | |
| 198 Generate SHcompact code | |
| 199 | |
| 200 m5-compact-nofpu | |
| 201 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU) | |
| 202 Generate FPU-less SHcompact code | |
| 203 | |
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
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204 maccumulate-outgoing-args |
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205 Target Report Mask(ACCUMULATE_OUTGOING_ARGS) |
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parents:
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206 Reserve space for outgoing arguments in the function prologue |
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parents:
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207 |
| 0 | 208 madjust-unroll |
| 209 Target Report Mask(ADJUST_UNROLL) Condition(SUPPORT_ANY_SH5) | |
| 210 Throttle unrolling to avoid thrashing target registers unless the unroll benefit outweighs this | |
| 211 | |
| 212 mb | |
| 213 Target Report RejectNegative InverseMask(LITTLE_ENDIAN) | |
| 214 Generate code in big endian mode | |
| 215 | |
| 216 mbigtable | |
| 217 Target Report RejectNegative Mask(BIGTABLE) | |
| 218 Generate 32-bit offsets in switch tables | |
| 219 | |
| 220 mbitops | |
| 221 Target Report RejectNegative Mask(BITOPS) | |
| 222 Generate bit instructions | |
| 223 | |
| 224 mbranch-cost= | |
| 225 Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1) | |
| 226 Cost to assume for a branch insn | |
| 227 | |
| 228 mcbranchdi | |
| 229 Target Var(TARGET_CBRANCHDI4) | |
| 230 Enable cbranchdi4 pattern | |
| 231 | |
| 232 mcmpeqdi | |
| 233 Target Var(TARGET_CMPEQDI_T) | |
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parents:
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234 Emit cmpeqdi_t pattern even when -mcbranchdi is in effect. |
| 0 | 235 |
| 236 mcut2-workaround | |
| 237 Target RejectNegative Var(TARGET_SH5_CUT2_WORKAROUND) | |
| 238 Enable SH5 cut2 workaround | |
| 239 | |
| 240 mdalign | |
| 241 Target Report RejectNegative Mask(ALIGN_DOUBLE) | |
| 242 Align doubles at 64-bit boundaries | |
| 243 | |
| 244 mdiv= | |
| 245 Target RejectNegative Joined Var(sh_div_str) Init("") | |
| 246 Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table | |
| 247 | |
| 248 mdivsi3_libfunc= | |
| 249 Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("") | |
| 250 Specify name for 32 bit signed division function | |
| 251 | |
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252 mfmovd |
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253 Target RejectNegative Mask(FMOVD) |
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254 Enable the use of 64-bit floating point registers in fmov instructions. See -mdalign if 64-bit alignment is required. |
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255 |
| 0 | 256 mfixed-range= |
| 257 Target RejectNegative Joined Var(sh_fixed_range_str) | |
| 258 Specify range of registers to make fixed | |
| 259 | |
| 260 mfused-madd | |
| 261 Target Var(TARGET_FMAC) | |
| 262 Enable the use of the fused floating point multiply-accumulate operation | |
| 263 | |
| 264 mgettrcost= | |
| 265 Target RejectNegative Joined UInteger Var(sh_gettrcost) Init(-1) | |
| 266 Cost to assume for gettr insn | |
| 267 | |
| 268 mhitachi | |
| 269 Target Report RejectNegative Mask(HITACHI) | |
| 270 Follow Renesas (formerly Hitachi) / SuperH calling conventions | |
| 271 | |
| 272 mieee | |
| 273 Target Report Mask(IEEE) | |
| 274 Increase the IEEE compliance for floating-point code | |
| 275 | |
| 276 mindexed-addressing | |
| 277 Target Report Mask(ALLOW_INDEXED_ADDRESS) Condition(SUPPORT_ANY_SH5_32MEDIA) | |
| 278 Enable the use of the indexed addressing mode for SHmedia32/SHcompact | |
| 279 | |
| 280 minline-ic_invalidate | |
| 281 Target Report Var(TARGET_INLINE_IC_INVALIDATE) | |
| 282 inline code to invalidate instruction cache entries after setting up nested function trampolines | |
| 283 | |
| 284 minvalid-symbols | |
| 285 Target Report Mask(INVALID_SYMBOLS) Condition(SUPPORT_ANY_SH5) | |
| 286 Assume symbols might be invalid | |
| 287 | |
| 288 misize | |
| 289 Target Report RejectNegative Mask(DUMPISIZE) | |
| 290 Annotate assembler instructions with estimated addresses | |
| 291 | |
| 292 ml | |
| 293 Target Report RejectNegative Mask(LITTLE_ENDIAN) | |
| 294 Generate code in little endian mode | |
| 295 | |
| 296 mnomacsave | |
| 297 Target Report RejectNegative Mask(NOMACSAVE) | |
| 298 Mark MAC register as call-clobbered | |
| 299 | |
| 300 ;; ??? This option is not useful, but is retained in case there are people | |
| 301 ;; who are still relying on it. It may be deleted in the future. | |
| 302 mpadstruct | |
| 303 Target Report RejectNegative Mask(PADSTRUCT) | |
| 304 Make structs a multiple of 4 bytes (warning: ABI altered) | |
| 305 | |
| 306 mprefergot | |
| 307 Target Report RejectNegative Mask(PREFERGOT) | |
| 308 Emit function-calls using global offset table when generating PIC | |
| 309 | |
| 310 mpt-fixed | |
| 311 Target Report Mask(PT_FIXED) Condition(SUPPORT_ANY_SH5) | |
| 312 Assume pt* instructions won't trap | |
| 313 | |
| 314 mrelax | |
| 315 Target Report RejectNegative Mask(RELAX) | |
| 316 Shorten address references during linking | |
| 317 | |
| 318 mrenesas | |
| 319 Target Mask(HITACHI) MaskExists | |
| 320 Follow Renesas (formerly Hitachi) / SuperH calling conventions | |
| 321 | |
| 322 mspace | |
|
67
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
323 Target RejectNegative Alias(Os) |
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parents:
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324 Deprecated. Use -Os instead |
| 0 | 325 |
| 326 multcost= | |
| 327 Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1) | |
| 328 Cost to assume for a multiply insn | |
| 329 | |
| 330 musermode | |
| 331 Target Report RejectNegative Mask(USERMODE) | |
| 332 Don't generate privileged-mode only code; implies -mno-inline-ic_invalidate if the inline code would not work in user mode. | |
| 333 | |
| 334 ;; We might want to enable this by default for TARGET_HARD_SH4, because | |
| 335 ;; zero-offset branches have zero latency. Needs some benchmarking. | |
| 336 mpretend-cmove | |
| 337 Target Var(TARGET_PRETEND_CMOVE) | |
| 338 Pretend a branch-around-a-move is a conditional move. |