Mercurial > hg > CbC > CbC_gcc
annotate gcc/ira.h @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
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date | Tue, 22 Mar 2011 17:18:12 +0900 |
parents | 77e2b8dfacca |
children | 04ced10e8804 |
rev | line source |
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0 | 1 /* Communication between the Integrated Register Allocator (IRA) and |
2 the rest of the compiler. | |
67
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3 Copyright (C) 2006, 2007, 2008, 2009, 2010 |
0 | 4 Free Software Foundation, Inc. |
5 Contributed by Vladimir Makarov <vmakarov@redhat.com>. | |
6 | |
7 This file is part of GCC. | |
8 | |
9 GCC is free software; you can redistribute it and/or modify it under | |
10 the terms of the GNU General Public License as published by the Free | |
11 Software Foundation; either version 3, or (at your option) any later | |
12 version. | |
13 | |
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 for more details. | |
18 | |
19 You should have received a copy of the GNU General Public License | |
20 along with GCC; see the file COPYING3. If not see | |
21 <http://www.gnu.org/licenses/>. */ | |
22 | |
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23 /* Function specific hard registers can not be used for the register |
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24 allocation. */ |
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25 extern HARD_REG_SET ira_no_alloc_regs; |
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26 |
0 | 27 /* True if we have allocno conflicts. It is false for non-optimized |
28 mode or when the conflict table is too big. */ | |
29 extern bool ira_conflicts_p; | |
30 | |
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31 struct target_ira { |
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32 /* Number of given class hard registers available for the register |
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33 allocation for given classes. */ |
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34 int x_ira_available_class_regs[N_REG_CLASSES]; |
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35 |
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36 /* Map: hard register number -> cover class it belongs to. If the |
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37 corresponding class is NO_REGS, the hard register is not available |
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38 for allocation. */ |
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39 enum reg_class x_ira_hard_regno_cover_class[FIRST_PSEUDO_REGISTER]; |
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40 |
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41 /* Number of cover classes. Cover classes is non-intersected register |
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42 classes containing all hard-registers available for the |
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43 allocation. */ |
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44 int x_ira_reg_class_cover_size; |
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45 |
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46 /* The array containing cover classes (see also comments for macro |
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47 IRA_COVER_CLASSES;. Only first IRA_REG_CLASS_COVER_SIZE elements are |
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48 used for this. */ |
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49 enum reg_class x_ira_reg_class_cover[N_REG_CLASSES]; |
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50 |
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51 /* Map of all register classes to corresponding cover class containing |
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52 the given class. If given class is not a subset of a cover class, |
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53 we translate it into the cheapest cover class. */ |
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54 enum reg_class x_ira_class_translate[N_REG_CLASSES]; |
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55 |
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56 /* Map: register class x machine mode -> number of hard registers of |
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57 given class needed to store value of given mode. If the number for |
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58 some hard-registers of the register class is different, the size |
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59 will be negative. */ |
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60 int x_ira_reg_class_nregs[N_REG_CLASSES][MAX_MACHINE_MODE]; |
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61 |
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62 /* Array analogous to target hook TARGET_MEMORY_MOVE_COST. */ |
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63 short x_ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2]; |
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64 |
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65 /* Array of number of hard registers of given class which are |
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66 available for the allocation. The order is defined by the |
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67 allocation order. */ |
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68 short x_ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]; |
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69 |
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70 /* The number of elements of the above array for given register |
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71 class. */ |
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72 int x_ira_class_hard_regs_num[N_REG_CLASSES]; |
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73 }; |
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74 |
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75 extern struct target_ira default_target_ira; |
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76 #if SWITCHABLE_TARGET |
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77 extern struct target_ira *this_target_ira; |
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78 #else |
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79 #define this_target_ira (&default_target_ira) |
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80 #endif |
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81 |
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82 #define ira_available_class_regs \ |
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83 (this_target_ira->x_ira_available_class_regs) |
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84 #define ira_hard_regno_cover_class \ |
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85 (this_target_ira->x_ira_hard_regno_cover_class) |
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86 #define ira_reg_class_cover_size \ |
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87 (this_target_ira->x_ira_reg_class_cover_size) |
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88 #define ira_reg_class_cover \ |
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89 (this_target_ira->x_ira_reg_class_cover) |
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90 #define ira_class_translate \ |
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91 (this_target_ira->x_ira_class_translate) |
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92 #define ira_reg_class_nregs \ |
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93 (this_target_ira->x_ira_reg_class_nregs) |
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94 #define ira_memory_move_cost \ |
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95 (this_target_ira->x_ira_memory_move_cost) |
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96 #define ira_class_hard_regs \ |
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97 (this_target_ira->x_ira_class_hard_regs) |
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98 #define ira_class_hard_regs_num \ |
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99 (this_target_ira->x_ira_class_hard_regs_num) |
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100 |
0 | 101 extern void ira_init_once (void); |
102 extern void ira_init (void); | |
103 extern void ira_finish_once (void); | |
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104 extern void ira_setup_eliminable_regset (void); |
0 | 105 extern rtx ira_eliminate_regs (rtx, enum machine_mode); |
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106 extern void ira_set_pseudo_classes (FILE *); |
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107 extern void ira_implicitly_set_insn_hard_regs (HARD_REG_SET *); |
0 | 108 |
109 extern void ira_sort_regnos_for_alter_reg (int *, int, unsigned int *); | |
110 extern void ira_mark_allocation_change (int); | |
111 extern void ira_mark_memory_move_deletion (int, int); | |
112 extern bool ira_reassign_pseudos (int *, int, HARD_REG_SET, HARD_REG_SET *, | |
113 HARD_REG_SET *, bitmap); | |
114 extern rtx ira_reuse_stack_slot (int, unsigned int, unsigned int); | |
115 extern void ira_mark_new_stack_slot (rtx, int, unsigned int); | |
116 extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx); | |
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117 extern bool ira_bad_reload_regno (int, rtx, rtx); |
0 | 118 |
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119 extern void ira_adjust_equiv_reg_cost (unsigned, int); |