Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/i386/i386.h @ 158:494b0b89df80 default tip
...
| author | Shinji KONO <kono@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Mon, 25 May 2020 18:13:55 +0900 |
| parents | 1830386684a0 |
| children |
| rev | line source |
|---|---|
| 0 | 1 /* Definitions of target machine for GCC for IA-32. |
| 145 | 2 Copyright (C) 1988-2020 Free Software Foundation, Inc. |
| 0 | 3 |
| 4 This file is part of GCC. | |
| 5 | |
| 6 GCC is free software; you can redistribute it and/or modify | |
| 7 it under the terms of the GNU General Public License as published by | |
| 8 the Free Software Foundation; either version 3, or (at your option) | |
| 9 any later version. | |
| 10 | |
| 11 GCC is distributed in the hope that it will be useful, | |
| 12 but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 GNU General Public License for more details. | |
| 15 | |
| 16 Under Section 7 of GPL version 3, you are granted additional | |
| 17 permissions described in the GCC Runtime Library Exception, version | |
| 18 3.1, as published by the Free Software Foundation. | |
| 19 | |
| 20 You should have received a copy of the GNU General Public License and | |
| 21 a copy of the GCC Runtime Library Exception along with this program; | |
| 22 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
| 23 <http://www.gnu.org/licenses/>. */ | |
| 24 | |
| 25 /* The purpose of this file is to define the characteristics of the i386, | |
| 26 independent of assembler syntax or operating system. | |
| 27 | |
| 28 Three other files build on this one to describe a specific assembler syntax: | |
| 29 bsd386.h, att386.h, and sun386.h. | |
| 30 | |
| 31 The actual tm.h file for a particular system should include | |
| 32 this file, and then the file for the appropriate assembler syntax. | |
| 33 | |
| 34 Many macros that specify assembler syntax are omitted entirely from | |
| 35 this file because they really belong in the files for particular | |
| 36 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, | |
| 37 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many | |
| 38 that start with ASM_ or end in ASM_OP. */ | |
| 39 | |
| 40 /* Redefines for option macros. */ | |
| 41 | |
| 111 | 42 #define TARGET_64BIT TARGET_ISA_64BIT |
| 43 #define TARGET_64BIT_P(x) TARGET_ISA_64BIT_P(x) | |
| 44 #define TARGET_MMX TARGET_ISA_MMX | |
| 45 #define TARGET_MMX_P(x) TARGET_ISA_MMX_P(x) | |
| 46 #define TARGET_3DNOW TARGET_ISA_3DNOW | |
| 47 #define TARGET_3DNOW_P(x) TARGET_ISA_3DNOW_P(x) | |
| 48 #define TARGET_3DNOW_A TARGET_ISA_3DNOW_A | |
| 49 #define TARGET_3DNOW_A_P(x) TARGET_ISA_3DNOW_A_P(x) | |
| 50 #define TARGET_SSE TARGET_ISA_SSE | |
| 51 #define TARGET_SSE_P(x) TARGET_ISA_SSE_P(x) | |
| 52 #define TARGET_SSE2 TARGET_ISA_SSE2 | |
| 53 #define TARGET_SSE2_P(x) TARGET_ISA_SSE2_P(x) | |
| 54 #define TARGET_SSE3 TARGET_ISA_SSE3 | |
| 55 #define TARGET_SSE3_P(x) TARGET_ISA_SSE3_P(x) | |
| 56 #define TARGET_SSSE3 TARGET_ISA_SSSE3 | |
| 57 #define TARGET_SSSE3_P(x) TARGET_ISA_SSSE3_P(x) | |
| 58 #define TARGET_SSE4_1 TARGET_ISA_SSE4_1 | |
| 59 #define TARGET_SSE4_1_P(x) TARGET_ISA_SSE4_1_P(x) | |
| 60 #define TARGET_SSE4_2 TARGET_ISA_SSE4_2 | |
| 61 #define TARGET_SSE4_2_P(x) TARGET_ISA_SSE4_2_P(x) | |
| 62 #define TARGET_AVX TARGET_ISA_AVX | |
| 63 #define TARGET_AVX_P(x) TARGET_ISA_AVX_P(x) | |
| 64 #define TARGET_AVX2 TARGET_ISA_AVX2 | |
| 65 #define TARGET_AVX2_P(x) TARGET_ISA_AVX2_P(x) | |
| 66 #define TARGET_AVX512F TARGET_ISA_AVX512F | |
| 67 #define TARGET_AVX512F_P(x) TARGET_ISA_AVX512F_P(x) | |
| 68 #define TARGET_AVX512PF TARGET_ISA_AVX512PF | |
| 69 #define TARGET_AVX512PF_P(x) TARGET_ISA_AVX512PF_P(x) | |
| 70 #define TARGET_AVX512ER TARGET_ISA_AVX512ER | |
| 71 #define TARGET_AVX512ER_P(x) TARGET_ISA_AVX512ER_P(x) | |
| 72 #define TARGET_AVX512CD TARGET_ISA_AVX512CD | |
| 73 #define TARGET_AVX512CD_P(x) TARGET_ISA_AVX512CD_P(x) | |
| 74 #define TARGET_AVX512DQ TARGET_ISA_AVX512DQ | |
| 75 #define TARGET_AVX512DQ_P(x) TARGET_ISA_AVX512DQ_P(x) | |
| 76 #define TARGET_AVX512BW TARGET_ISA_AVX512BW | |
| 77 #define TARGET_AVX512BW_P(x) TARGET_ISA_AVX512BW_P(x) | |
| 78 #define TARGET_AVX512VL TARGET_ISA_AVX512VL | |
| 79 #define TARGET_AVX512VL_P(x) TARGET_ISA_AVX512VL_P(x) | |
| 80 #define TARGET_AVX512VBMI TARGET_ISA_AVX512VBMI | |
| 81 #define TARGET_AVX512VBMI_P(x) TARGET_ISA_AVX512VBMI_P(x) | |
| 82 #define TARGET_AVX512IFMA TARGET_ISA_AVX512IFMA | |
| 83 #define TARGET_AVX512IFMA_P(x) TARGET_ISA_AVX512IFMA_P(x) | |
| 145 | 84 #define TARGET_AVX5124FMAPS TARGET_ISA2_AVX5124FMAPS |
| 85 #define TARGET_AVX5124FMAPS_P(x) TARGET_ISA2_AVX5124FMAPS_P(x) | |
| 86 #define TARGET_AVX5124VNNIW TARGET_ISA2_AVX5124VNNIW | |
| 87 #define TARGET_AVX5124VNNIW_P(x) TARGET_ISA2_AVX5124VNNIW_P(x) | |
| 131 | 88 #define TARGET_AVX512VBMI2 TARGET_ISA_AVX512VBMI2 |
| 89 #define TARGET_AVX512VBMI2_P(x) TARGET_ISA_AVX512VBMI2_P(x) | |
| 111 | 90 #define TARGET_AVX512VPOPCNTDQ TARGET_ISA_AVX512VPOPCNTDQ |
| 91 #define TARGET_AVX512VPOPCNTDQ_P(x) TARGET_ISA_AVX512VPOPCNTDQ_P(x) | |
| 131 | 92 #define TARGET_AVX512VNNI TARGET_ISA_AVX512VNNI |
| 93 #define TARGET_AVX512VNNI_P(x) TARGET_ISA_AVX512VNNI_P(x) | |
| 94 #define TARGET_AVX512BITALG TARGET_ISA_AVX512BITALG | |
| 95 #define TARGET_AVX512BITALG_P(x) TARGET_ISA_AVX512BITALG_P(x) | |
| 145 | 96 #define TARGET_AVX512VP2INTERSECT TARGET_ISA2_AVX512VP2INTERSECT |
| 97 #define TARGET_AVX512VP2INTERSECT_P(x) TARGET_ISA2_AVX512VP2INTERSECT_P(x) | |
| 111 | 98 #define TARGET_FMA TARGET_ISA_FMA |
| 99 #define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x) | |
| 100 #define TARGET_SSE4A TARGET_ISA_SSE4A | |
| 101 #define TARGET_SSE4A_P(x) TARGET_ISA_SSE4A_P(x) | |
| 102 #define TARGET_FMA4 TARGET_ISA_FMA4 | |
| 103 #define TARGET_FMA4_P(x) TARGET_ISA_FMA4_P(x) | |
| 104 #define TARGET_XOP TARGET_ISA_XOP | |
| 105 #define TARGET_XOP_P(x) TARGET_ISA_XOP_P(x) | |
| 106 #define TARGET_LWP TARGET_ISA_LWP | |
| 107 #define TARGET_LWP_P(x) TARGET_ISA_LWP_P(x) | |
| 108 #define TARGET_ABM TARGET_ISA_ABM | |
| 109 #define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x) | |
| 145 | 110 #define TARGET_PCONFIG TARGET_ISA2_PCONFIG |
| 111 #define TARGET_PCONFIG_P(x) TARGET_ISA2_PCONFIG_P(x) | |
| 112 #define TARGET_WBNOINVD TARGET_ISA2_WBNOINVD | |
| 113 #define TARGET_WBNOINVD_P(x) TARGET_ISA2_WBNOINVD_P(x) | |
| 114 #define TARGET_SGX TARGET_ISA2_SGX | |
| 115 #define TARGET_SGX_P(x) TARGET_ISA2_SGX_P(x) | |
| 116 #define TARGET_RDPID TARGET_ISA2_RDPID | |
| 117 #define TARGET_RDPID_P(x) TARGET_ISA2_RDPID_P(x) | |
| 111 | 118 #define TARGET_GFNI TARGET_ISA_GFNI |
| 119 #define TARGET_GFNI_P(x) TARGET_ISA_GFNI_P(x) | |
| 145 | 120 #define TARGET_VAES TARGET_ISA2_VAES |
| 121 #define TARGET_VAES_P(x) TARGET_ISA2_VAES_P(x) | |
| 131 | 122 #define TARGET_VPCLMULQDQ TARGET_ISA_VPCLMULQDQ |
| 123 #define TARGET_VPCLMULQDQ_P(x) TARGET_ISA_VPCLMULQDQ_P(x) | |
| 111 | 124 #define TARGET_BMI TARGET_ISA_BMI |
| 125 #define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x) | |
| 126 #define TARGET_BMI2 TARGET_ISA_BMI2 | |
| 127 #define TARGET_BMI2_P(x) TARGET_ISA_BMI2_P(x) | |
| 128 #define TARGET_LZCNT TARGET_ISA_LZCNT | |
| 129 #define TARGET_LZCNT_P(x) TARGET_ISA_LZCNT_P(x) | |
| 130 #define TARGET_TBM TARGET_ISA_TBM | |
| 131 #define TARGET_TBM_P(x) TARGET_ISA_TBM_P(x) | |
| 132 #define TARGET_POPCNT TARGET_ISA_POPCNT | |
| 133 #define TARGET_POPCNT_P(x) TARGET_ISA_POPCNT_P(x) | |
| 134 #define TARGET_SAHF TARGET_ISA_SAHF | |
| 135 #define TARGET_SAHF_P(x) TARGET_ISA_SAHF_P(x) | |
| 145 | 136 #define TARGET_MOVBE TARGET_ISA2_MOVBE |
| 137 #define TARGET_MOVBE_P(x) TARGET_ISA2_MOVBE_P(x) | |
| 111 | 138 #define TARGET_CRC32 TARGET_ISA_CRC32 |
| 139 #define TARGET_CRC32_P(x) TARGET_ISA_CRC32_P(x) | |
| 140 #define TARGET_AES TARGET_ISA_AES | |
| 141 #define TARGET_AES_P(x) TARGET_ISA_AES_P(x) | |
| 142 #define TARGET_SHA TARGET_ISA_SHA | |
| 143 #define TARGET_SHA_P(x) TARGET_ISA_SHA_P(x) | |
| 144 #define TARGET_CLFLUSHOPT TARGET_ISA_CLFLUSHOPT | |
| 145 #define TARGET_CLFLUSHOPT_P(x) TARGET_ISA_CLFLUSHOPT_P(x) | |
| 145 | 146 #define TARGET_CLZERO TARGET_ISA2_CLZERO |
| 147 #define TARGET_CLZERO_P(x) TARGET_ISA2_CLZERO_P(x) | |
| 111 | 148 #define TARGET_XSAVEC TARGET_ISA_XSAVEC |
| 149 #define TARGET_XSAVEC_P(x) TARGET_ISA_XSAVEC_P(x) | |
| 150 #define TARGET_XSAVES TARGET_ISA_XSAVES | |
| 151 #define TARGET_XSAVES_P(x) TARGET_ISA_XSAVES_P(x) | |
| 152 #define TARGET_PCLMUL TARGET_ISA_PCLMUL | |
| 153 #define TARGET_PCLMUL_P(x) TARGET_ISA_PCLMUL_P(x) | |
| 145 | 154 #define TARGET_CMPXCHG16B TARGET_ISA2_CX16 |
| 155 #define TARGET_CMPXCHG16B_P(x) TARGET_ISA2_CX16_P(x) | |
| 111 | 156 #define TARGET_FSGSBASE TARGET_ISA_FSGSBASE |
| 157 #define TARGET_FSGSBASE_P(x) TARGET_ISA_FSGSBASE_P(x) | |
| 158 #define TARGET_RDRND TARGET_ISA_RDRND | |
| 159 #define TARGET_RDRND_P(x) TARGET_ISA_RDRND_P(x) | |
| 160 #define TARGET_F16C TARGET_ISA_F16C | |
| 161 #define TARGET_F16C_P(x) TARGET_ISA_F16C_P(x) | |
| 162 #define TARGET_RTM TARGET_ISA_RTM | |
| 163 #define TARGET_RTM_P(x) TARGET_ISA_RTM_P(x) | |
| 145 | 164 #define TARGET_HLE TARGET_ISA2_HLE |
| 165 #define TARGET_HLE_P(x) TARGET_ISA2_HLE_P(x) | |
| 111 | 166 #define TARGET_RDSEED TARGET_ISA_RDSEED |
| 167 #define TARGET_RDSEED_P(x) TARGET_ISA_RDSEED_P(x) | |
| 168 #define TARGET_PRFCHW TARGET_ISA_PRFCHW | |
| 169 #define TARGET_PRFCHW_P(x) TARGET_ISA_PRFCHW_P(x) | |
| 170 #define TARGET_ADX TARGET_ISA_ADX | |
| 171 #define TARGET_ADX_P(x) TARGET_ISA_ADX_P(x) | |
| 172 #define TARGET_FXSR TARGET_ISA_FXSR | |
| 173 #define TARGET_FXSR_P(x) TARGET_ISA_FXSR_P(x) | |
| 174 #define TARGET_XSAVE TARGET_ISA_XSAVE | |
| 175 #define TARGET_XSAVE_P(x) TARGET_ISA_XSAVE_P(x) | |
| 176 #define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT | |
| 177 #define TARGET_XSAVEOPT_P(x) TARGET_ISA_XSAVEOPT_P(x) | |
| 178 #define TARGET_PREFETCHWT1 TARGET_ISA_PREFETCHWT1 | |
| 179 #define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x) | |
| 180 #define TARGET_CLWB TARGET_ISA_CLWB | |
| 181 #define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x) | |
| 145 | 182 #define TARGET_MWAITX TARGET_ISA2_MWAITX |
| 183 #define TARGET_MWAITX_P(x) TARGET_ISA2_MWAITX_P(x) | |
| 111 | 184 #define TARGET_PKU TARGET_ISA_PKU |
| 185 #define TARGET_PKU_P(x) TARGET_ISA_PKU_P(x) | |
| 186 #define TARGET_SHSTK TARGET_ISA_SHSTK | |
| 187 #define TARGET_SHSTK_P(x) TARGET_ISA_SHSTK_P(x) | |
| 131 | 188 #define TARGET_MOVDIRI TARGET_ISA_MOVDIRI |
| 189 #define TARGET_MOVDIRI_P(x) TARGET_ISA_MOVDIRI_P(x) | |
| 145 | 190 #define TARGET_MOVDIR64B TARGET_ISA2_MOVDIR64B |
| 191 #define TARGET_MOVDIR64B_P(x) TARGET_ISA2_MOVDIR64B_P(x) | |
| 192 #define TARGET_WAITPKG TARGET_ISA2_WAITPKG | |
| 193 #define TARGET_WAITPKG_P(x) TARGET_ISA2_WAITPKG_P(x) | |
| 194 #define TARGET_CLDEMOTE TARGET_ISA2_CLDEMOTE | |
| 195 #define TARGET_CLDEMOTE_P(x) TARGET_ISA2_CLDEMOTE_P(x) | |
| 196 #define TARGET_PTWRITE TARGET_ISA2_PTWRITE | |
| 197 #define TARGET_PTWRITE_P(x) TARGET_ISA2_PTWRITE_P(x) | |
| 198 #define TARGET_AVX512BF16 TARGET_ISA2_AVX512BF16 | |
| 199 #define TARGET_AVX512BF16_P(x) TARGET_ISA2_AVX512BF16_P(x) | |
| 200 #define TARGET_ENQCMD TARGET_ISA2_ENQCMD | |
| 201 #define TARGET_ENQCMD_P(x) TARGET_ISA2_ENQCMD_P(x) | |
| 111 | 202 |
| 203 #define TARGET_LP64 TARGET_ABI_64 | |
| 204 #define TARGET_LP64_P(x) TARGET_ABI_64_P(x) | |
| 205 #define TARGET_X32 TARGET_ABI_X32 | |
| 206 #define TARGET_X32_P(x) TARGET_ABI_X32_P(x) | |
| 207 #define TARGET_16BIT TARGET_CODE16 | |
| 208 #define TARGET_16BIT_P(x) TARGET_CODE16_P(x) | |
| 0 | 209 |
| 145 | 210 #define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2) |
| 211 | |
| 0 | 212 #include "config/vxworks-dummy.h" |
| 213 | |
| 111 | 214 #include "config/i386/i386-opts.h" |
| 0 | 215 |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
216 #define MAX_STRINGOP_ALGS 4 |
| 0 | 217 |
| 218 /* Specify what algorithm to use for stringops on known size. | |
| 219 When size is unknown, the UNKNOWN_SIZE alg is used. When size is | |
| 220 known at compile time or estimated via feedback, the SIZE array | |
| 221 is walked in order until MAX is greater then the estimate (or -1 | |
| 222 means infinity). Corresponding ALG is used then. | |
| 111 | 223 When NOALIGN is true the code guaranting the alignment of the memory |
| 224 block is skipped. | |
| 225 | |
| 0 | 226 For example initializer: |
| 227 {{256, loop}, {-1, rep_prefix_4_byte}} | |
| 228 will use loop for blocks smaller or equal to 256 bytes, rep prefix will | |
| 229 be used otherwise. */ | |
| 230 struct stringop_algs | |
| 231 { | |
| 232 const enum stringop_alg unknown_size; | |
| 233 const struct stringop_strategy { | |
| 234 const int max; | |
| 235 const enum stringop_alg alg; | |
| 111 | 236 int noalign; |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
237 } size [MAX_STRINGOP_ALGS]; |
| 0 | 238 }; |
| 239 | |
| 145 | 240 /* Define the specific costs for a given cpu. NB: hard_register is used |
| 241 by TARGET_REGISTER_MOVE_COST and TARGET_MEMORY_MOVE_COST to compute | |
| 242 hard register move costs by register allocator. Relative costs of | |
| 243 pseudo register load and store versus pseudo register moves in RTL | |
| 244 expressions for TARGET_RTX_COSTS can be different from relative | |
| 245 costs of hard registers to get the most efficient operations with | |
| 246 pseudo registers. */ | |
| 0 | 247 |
| 248 struct processor_costs { | |
| 145 | 249 /* Costs used by register allocator. integer->integer register move |
| 250 cost is 2. */ | |
| 251 struct | |
| 252 { | |
| 253 const int movzbl_load; /* cost of loading using movzbl */ | |
| 254 const int int_load[3]; /* cost of loading integer registers | |
| 255 in QImode, HImode and SImode relative | |
| 256 to reg-reg move (2). */ | |
| 257 const int int_store[3]; /* cost of storing integer register | |
| 258 in QImode, HImode and SImode */ | |
| 259 const int fp_move; /* cost of reg,reg fld/fst */ | |
| 260 const int fp_load[3]; /* cost of loading FP register | |
| 261 in SFmode, DFmode and XFmode */ | |
| 262 const int fp_store[3]; /* cost of storing FP register | |
| 263 in SFmode, DFmode and XFmode */ | |
| 264 const int mmx_move; /* cost of moving MMX register. */ | |
| 265 const int mmx_load[2]; /* cost of loading MMX register | |
| 266 in SImode and DImode */ | |
| 267 const int mmx_store[2]; /* cost of storing MMX register | |
| 268 in SImode and DImode */ | |
| 269 const int xmm_move; /* cost of moving XMM register. */ | |
| 270 const int ymm_move; /* cost of moving XMM register. */ | |
| 271 const int zmm_move; /* cost of moving XMM register. */ | |
| 272 const int sse_load[5]; /* cost of loading SSE register | |
| 273 in 32bit, 64bit, 128bit, 256bit and 512bit */ | |
| 274 const int sse_store[5]; /* cost of storing SSE register | |
| 275 in SImode, DImode and TImode. */ | |
| 276 const int sse_to_integer; /* cost of moving SSE register to integer. */ | |
| 277 const int integer_to_sse; /* cost of moving integer register to SSE. */ | |
| 278 } hard_register; | |
| 279 | |
| 0 | 280 const int add; /* cost of an add instruction */ |
| 281 const int lea; /* cost of a lea instruction */ | |
| 282 const int shift_var; /* variable shift costs */ | |
| 283 const int shift_const; /* constant shift costs */ | |
| 284 const int mult_init[5]; /* cost of starting a multiply | |
| 285 in QImode, HImode, SImode, DImode, TImode*/ | |
| 286 const int mult_bit; /* cost of multiply per each bit set */ | |
| 287 const int divide[5]; /* cost of a divide/mod | |
| 288 in QImode, HImode, SImode, DImode, TImode*/ | |
| 289 int movsx; /* The cost of movsx operation. */ | |
| 290 int movzx; /* The cost of movzx operation. */ | |
| 291 const int large_insn; /* insns larger than this cost more */ | |
| 292 const int move_ratio; /* The threshold of number of scalar | |
| 293 memory-to-memory move insns. */ | |
| 145 | 294 const int clear_ratio; /* The threshold of number of scalar |
| 295 memory clearing insns. */ | |
| 0 | 296 const int int_load[3]; /* cost of loading integer registers |
| 297 in QImode, HImode and SImode relative | |
| 298 to reg-reg move (2). */ | |
| 299 const int int_store[3]; /* cost of storing integer register | |
| 300 in QImode, HImode and SImode */ | |
| 145 | 301 const int sse_load[5]; /* cost of loading SSE register |
| 302 in 32bit, 64bit, 128bit, 256bit and 512bit */ | |
| 303 const int sse_store[5]; /* cost of storing SSE register | |
| 304 in 32bit, 64bit, 128bit, 256bit and 512bit */ | |
| 305 const int sse_unaligned_load[5];/* cost of unaligned load. */ | |
| 306 const int sse_unaligned_store[5];/* cost of unaligned store. */ | |
| 111 | 307 const int xmm_move, ymm_move, /* cost of moving XMM and YMM register. */ |
| 308 zmm_move; | |
| 145 | 309 const int sse_to_integer; /* cost of moving SSE register to integer. */ |
| 111 | 310 const int gather_static, gather_per_elt; /* Cost of gather load is computed |
| 311 as static + per_item * nelts. */ | |
| 312 const int scatter_static, scatter_per_elt; /* Cost of gather store is | |
| 313 computed as static + per_item * nelts. */ | |
| 0 | 314 const int l1_cache_size; /* size of l1 cache, in kilobytes. */ |
| 315 const int l2_cache_size; /* size of l2 cache, in kilobytes. */ | |
| 316 const int prefetch_block; /* bytes moved to cache for prefetch. */ | |
| 317 const int simultaneous_prefetches; /* number of parallel prefetch | |
| 318 operations. */ | |
| 319 const int branch_cost; /* Default value for BRANCH_COST. */ | |
| 320 const int fadd; /* cost of FADD and FSUB instructions. */ | |
| 321 const int fmul; /* cost of FMUL instruction. */ | |
| 322 const int fdiv; /* cost of FDIV instruction. */ | |
| 323 const int fabs; /* cost of FABS instruction. */ | |
| 324 const int fchs; /* cost of FCHS instruction. */ | |
| 325 const int fsqrt; /* cost of FSQRT instruction. */ | |
| 326 /* Specify what algorithm | |
| 327 to use for stringops on unknown size. */ | |
| 111 | 328 const int sse_op; /* cost of cheap SSE instruction. */ |
| 329 const int addss; /* cost of ADDSS/SD SUBSS/SD instructions. */ | |
| 330 const int mulss; /* cost of MULSS instructions. */ | |
| 331 const int mulsd; /* cost of MULSD instructions. */ | |
| 332 const int fmass; /* cost of FMASS instructions. */ | |
| 333 const int fmasd; /* cost of FMASD instructions. */ | |
| 334 const int divss; /* cost of DIVSS instructions. */ | |
| 335 const int divsd; /* cost of DIVSD instructions. */ | |
| 336 const int sqrtss; /* cost of SQRTSS instructions. */ | |
| 337 const int sqrtsd; /* cost of SQRTSD instructions. */ | |
| 338 const int reassoc_int, reassoc_fp, reassoc_vec_int, reassoc_vec_fp; | |
| 339 /* Specify reassociation width for integer, | |
| 340 fp, vector integer and vector fp | |
| 341 operations. Generally should correspond | |
| 342 to number of instructions executed in | |
| 343 parallel. See also | |
| 344 ix86_reassociation_width. */ | |
| 345 struct stringop_algs *memcpy, *memset; | |
| 0 | 346 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer |
| 347 cost model. */ | |
| 348 const int cond_not_taken_branch_cost;/* Cost of not taken branch for | |
| 349 vectorizer cost model. */ | |
| 131 | 350 |
| 351 /* The "0:0:8" label alignment specified for some processors generates | |
| 352 secondary 8-byte alignment only for those label/jump/loop targets | |
| 353 which have primary alignment. */ | |
| 354 const char *const align_loop; /* Loop alignment. */ | |
| 355 const char *const align_jump; /* Jump alignment. */ | |
| 356 const char *const align_label; /* Label alignment. */ | |
| 357 const char *const align_func; /* Function alignment. */ | |
| 0 | 358 }; |
| 359 | |
| 360 extern const struct processor_costs *ix86_cost; | |
| 361 extern const struct processor_costs ix86_size_cost; | |
| 362 | |
| 363 #define ix86_cur_cost() \ | |
| 364 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) | |
| 365 | |
| 366 /* Macros used in the machine description to test the flags. */ | |
| 367 | |
| 111 | 368 /* configure can arrange to change it. */ |
| 0 | 369 |
| 370 #ifndef TARGET_CPU_DEFAULT | |
| 111 | 371 #define TARGET_CPU_DEFAULT PROCESSOR_GENERIC |
| 0 | 372 #endif |
| 373 | |
| 374 #ifndef TARGET_FPMATH_DEFAULT | |
| 375 #define TARGET_FPMATH_DEFAULT \ | |
| 376 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) | |
| 377 #endif | |
| 378 | |
| 111 | 379 #ifndef TARGET_FPMATH_DEFAULT_P |
| 380 #define TARGET_FPMATH_DEFAULT_P(x) \ | |
| 381 (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387) | |
| 382 #endif | |
| 383 | |
| 384 /* If the i387 is disabled or -miamcu is used , then do not return | |
| 385 values in it. */ | |
| 386 #define TARGET_FLOAT_RETURNS_IN_80387 \ | |
| 387 (TARGET_FLOAT_RETURNS && TARGET_80387 && !TARGET_IAMCU) | |
| 388 #define TARGET_FLOAT_RETURNS_IN_80387_P(x) \ | |
| 389 (TARGET_FLOAT_RETURNS_P(x) && TARGET_80387_P(x) && !TARGET_IAMCU_P(x)) | |
| 0 | 390 |
| 391 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a | |
| 392 compile-time constant. */ | |
| 393 #ifdef IN_LIBGCC2 | |
| 394 #undef TARGET_64BIT | |
| 395 #ifdef __x86_64__ | |
| 396 #define TARGET_64BIT 1 | |
| 397 #else | |
| 398 #define TARGET_64BIT 0 | |
| 399 #endif | |
| 400 #else | |
| 401 #ifndef TARGET_BI_ARCH | |
| 402 #undef TARGET_64BIT | |
| 111 | 403 #undef TARGET_64BIT_P |
| 0 | 404 #if TARGET_64BIT_DEFAULT |
| 405 #define TARGET_64BIT 1 | |
| 111 | 406 #define TARGET_64BIT_P(x) 1 |
| 0 | 407 #else |
| 408 #define TARGET_64BIT 0 | |
| 111 | 409 #define TARGET_64BIT_P(x) 0 |
| 0 | 410 #endif |
| 411 #endif | |
| 412 #endif | |
| 413 | |
| 414 #define HAS_LONG_COND_BRANCH 1 | |
| 415 #define HAS_LONG_UNCOND_BRANCH 1 | |
| 416 | |
| 417 #define TARGET_386 (ix86_tune == PROCESSOR_I386) | |
| 418 #define TARGET_486 (ix86_tune == PROCESSOR_I486) | |
| 419 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) | |
| 420 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) | |
| 421 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) | |
| 422 #define TARGET_K6 (ix86_tune == PROCESSOR_K6) | |
| 423 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) | |
| 424 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) | |
| 425 #define TARGET_K8 (ix86_tune == PROCESSOR_K8) | |
| 426 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) | |
| 427 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) | |
| 111 | 428 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) |
| 429 #define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM) | |
| 430 #define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE) | |
| 431 #define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL) | |
| 432 #define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL) | |
| 433 #define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT) | |
| 131 | 434 #define TARGET_GOLDMONT (ix86_tune == PROCESSOR_GOLDMONT) |
| 435 #define TARGET_GOLDMONT_PLUS (ix86_tune == PROCESSOR_GOLDMONT_PLUS) | |
| 436 #define TARGET_TREMONT (ix86_tune == PROCESSOR_TREMONT) | |
| 111 | 437 #define TARGET_KNL (ix86_tune == PROCESSOR_KNL) |
| 438 #define TARGET_KNM (ix86_tune == PROCESSOR_KNM) | |
| 131 | 439 #define TARGET_SKYLAKE (ix86_tune == PROCESSOR_SKYLAKE) |
| 111 | 440 #define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512) |
| 131 | 441 #define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE) |
| 442 #define TARGET_ICELAKE_CLIENT (ix86_tune == PROCESSOR_ICELAKE_CLIENT) | |
| 443 #define TARGET_ICELAKE_SERVER (ix86_tune == PROCESSOR_ICELAKE_SERVER) | |
| 145 | 444 #define TARGET_CASCADELAKE (ix86_tune == PROCESSOR_CASCADELAKE) |
| 445 #define TARGET_TIGERLAKE (ix86_tune == PROCESSOR_TIGERLAKE) | |
| 446 #define TARGET_COOPERLAKE (ix86_tune == PROCESSOR_COOPERLAKE) | |
| 111 | 447 #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL) |
| 448 #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC) | |
| 0 | 449 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) |
|
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
450 #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1) |
| 111 | 451 #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2) |
| 452 #define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3) | |
| 453 #define TARGET_BDVER4 (ix86_tune == PROCESSOR_BDVER4) | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
454 #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1) |
| 111 | 455 #define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2) |
| 456 #define TARGET_ZNVER1 (ix86_tune == PROCESSOR_ZNVER1) | |
| 145 | 457 #define TARGET_ZNVER2 (ix86_tune == PROCESSOR_ZNVER2) |
| 0 | 458 |
| 459 /* Feature tests against the various tunings. */ | |
| 460 enum ix86_tune_indices { | |
| 111 | 461 #undef DEF_TUNE |
| 462 #define DEF_TUNE(tune, name, selector) tune, | |
| 463 #include "x86-tune.def" | |
| 464 #undef DEF_TUNE | |
| 465 X86_TUNE_LAST | |
| 0 | 466 }; |
| 467 | |
| 468 extern unsigned char ix86_tune_features[X86_TUNE_LAST]; | |
| 469 | |
| 470 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] | |
| 471 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] | |
| 472 #define TARGET_ZERO_EXTEND_WITH_AND \ | |
| 473 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] | |
| 474 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] | |
| 475 #define TARGET_BRANCH_PREDICTION_HINTS \ | |
| 476 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] | |
| 477 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] | |
| 478 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] | |
| 479 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] | |
| 480 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] | |
| 481 #define TARGET_PARTIAL_FLAG_REG_STALL \ | |
| 482 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] | |
| 111 | 483 #define TARGET_LCP_STALL \ |
| 484 ix86_tune_features[X86_TUNE_LCP_STALL] | |
| 0 | 485 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] |
| 486 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] | |
| 487 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] | |
| 488 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] | |
| 489 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] | |
| 490 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] | |
| 491 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] | |
| 492 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] | |
| 493 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] | |
| 494 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] | |
| 495 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] | |
| 111 | 496 #define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \ |
| 497 ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES] | |
| 0 | 498 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] |
| 499 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] | |
| 500 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] | |
| 501 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
502 #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
503 #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
504 #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
505 #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH] |
| 0 | 506 #define TARGET_INTEGER_DFMODE_MOVES \ |
| 507 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] | |
| 508 #define TARGET_PARTIAL_REG_DEPENDENCY \ | |
| 509 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] | |
| 510 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ | |
| 511 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] | |
|
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
512 #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ |
|
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
513 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL] |
|
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
514 #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \ |
|
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
515 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL] |
|
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
516 #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \ |
|
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
517 ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL] |
| 0 | 518 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] |
| 519 #define TARGET_SSE_TYPELESS_STORES \ | |
| 520 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] | |
| 521 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] | |
| 522 #define TARGET_MEMORY_MISMATCH_STALL \ | |
| 523 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] | |
| 524 #define TARGET_PROLOGUE_USING_MOVE \ | |
| 525 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] | |
| 526 #define TARGET_EPILOGUE_USING_MOVE \ | |
| 527 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] | |
| 528 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] | |
| 529 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] | |
| 111 | 530 #define TARGET_INTER_UNIT_MOVES_TO_VEC \ |
| 531 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC] | |
| 532 #define TARGET_INTER_UNIT_MOVES_FROM_VEC \ | |
| 533 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC] | |
| 534 #define TARGET_INTER_UNIT_CONVERSIONS \ | |
| 0 | 535 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] |
| 536 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] | |
| 537 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] | |
| 538 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] | |
| 539 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] | |
| 540 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
541 #define TARGET_PAD_SHORT_FUNCTION \ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
542 ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION] |
| 0 | 543 #define TARGET_EXT_80387_CONSTANTS \ |
| 544 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] | |
| 545 #define TARGET_AVOID_VECTOR_DECODE \ | |
| 546 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] | |
| 547 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ | |
| 548 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] | |
| 549 #define TARGET_SLOW_IMUL_IMM32_MEM \ | |
| 550 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] | |
| 551 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] | |
| 552 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] | |
| 553 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] | |
| 554 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] | |
| 555 #define TARGET_USE_VECTOR_FP_CONVERTS \ | |
| 556 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] | |
| 557 #define TARGET_USE_VECTOR_CONVERTS \ | |
| 558 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] | |
| 111 | 559 #define TARGET_SLOW_PSHUFB \ |
| 560 ix86_tune_features[X86_TUNE_SLOW_PSHUFB] | |
| 561 #define TARGET_AVOID_4BYTE_PREFIXES \ | |
| 562 ix86_tune_features[X86_TUNE_AVOID_4BYTE_PREFIXES] | |
| 131 | 563 #define TARGET_USE_GATHER \ |
| 564 ix86_tune_features[X86_TUNE_USE_GATHER] | |
| 111 | 565 #define TARGET_FUSE_CMP_AND_BRANCH_32 \ |
| 566 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32] | |
| 567 #define TARGET_FUSE_CMP_AND_BRANCH_64 \ | |
| 568 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64] | |
| 0 | 569 #define TARGET_FUSE_CMP_AND_BRANCH \ |
| 111 | 570 (TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \ |
| 571 : TARGET_FUSE_CMP_AND_BRANCH_32) | |
| 572 #define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \ | |
| 573 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS] | |
| 574 #define TARGET_FUSE_ALU_AND_BRANCH \ | |
| 575 ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH] | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
576 #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU] |
| 111 | 577 #define TARGET_AVOID_LEA_FOR_ADDR \ |
| 578 ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR] | |
| 579 #define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \ | |
| 580 ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL] | |
| 145 | 581 #define TARGET_AVX256_SPLIT_REGS \ |
| 582 ix86_tune_features[X86_TUNE_AVX256_SPLIT_REGS] | |
| 111 | 583 #define TARGET_GENERAL_REGS_SSE_SPILL \ |
| 584 ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL] | |
| 585 #define TARGET_AVOID_MEM_OPND_FOR_CMOVE \ | |
| 586 ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE] | |
| 587 #define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \ | |
| 588 ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS] | |
| 589 #define TARGET_ADJUST_UNROLL \ | |
| 590 ix86_tune_features[X86_TUNE_ADJUST_UNROLL] | |
| 591 #define TARGET_AVOID_FALSE_DEP_FOR_BMI \ | |
| 592 ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI] | |
| 593 #define TARGET_ONE_IF_CONV_INSN \ | |
| 594 ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN] | |
| 145 | 595 #define TARGET_USE_XCHG_FOR_ATOMIC_STORE \ |
| 596 ix86_tune_features[X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE] | |
| 131 | 597 #define TARGET_EMIT_VZEROUPPER \ |
| 598 ix86_tune_features[X86_TUNE_EMIT_VZEROUPPER] | |
| 145 | 599 #define TARGET_EXPAND_ABS \ |
| 600 ix86_tune_features[X86_TUNE_EXPAND_ABS] | |
| 0 | 601 |
| 602 /* Feature tests against the various architecture variations. */ | |
| 603 enum ix86_arch_indices { | |
| 111 | 604 X86_ARCH_CMOV, |
| 0 | 605 X86_ARCH_CMPXCHG, |
| 606 X86_ARCH_CMPXCHG8B, | |
| 607 X86_ARCH_XADD, | |
| 608 X86_ARCH_BSWAP, | |
| 609 | |
| 610 X86_ARCH_LAST | |
| 611 }; | |
| 612 | |
| 613 extern unsigned char ix86_arch_features[X86_ARCH_LAST]; | |
| 614 | |
| 111 | 615 #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV] |
| 0 | 616 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] |
| 617 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] | |
| 618 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] | |
| 619 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] | |
| 620 | |
| 111 | 621 /* For sane SSE instruction set generation we need fcomi instruction. |
| 622 It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic | |
| 623 expands to a sequence that includes conditional move. */ | |
| 624 #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND) | |
| 625 | |
| 0 | 626 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) |
| 627 | |
| 111 | 628 extern unsigned char x86_prefetch_sse; |
| 0 | 629 #define TARGET_PREFETCH_SSE x86_prefetch_sse |
| 630 | |
| 631 #define ASSEMBLER_DIALECT (ix86_asm_dialect) | |
| 632 | |
| 633 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) | |
| 634 #define TARGET_MIX_SSE_I387 \ | |
| 635 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) | |
| 636 | |
| 111 | 637 #define TARGET_HARD_SF_REGS (TARGET_80387 || TARGET_MMX || TARGET_SSE) |
| 638 #define TARGET_HARD_DF_REGS (TARGET_80387 || TARGET_SSE) | |
| 639 #define TARGET_HARD_XF_REGS (TARGET_80387) | |
| 640 | |
| 0 | 641 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) |
| 642 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) | |
| 643 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) | |
|
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
644 #define TARGET_SUN_TLS 0 |
| 0 | 645 |
| 646 #ifndef TARGET_64BIT_DEFAULT | |
| 647 #define TARGET_64BIT_DEFAULT 0 | |
| 648 #endif | |
| 649 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT | |
| 650 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 | |
| 651 #endif | |
| 652 | |
| 111 | 653 #define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL) |
| 654 #define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS) | |
| 655 | |
| 0 | 656 /* Fence to use after loop using storent. */ |
| 657 | |
| 658 extern tree x86_mfence; | |
| 659 #define FENCE_FOLLOWING_MOVNT x86_mfence | |
| 660 | |
| 661 /* Once GDB has been enhanced to deal with functions without frame | |
| 662 pointers, we can change this to allow for elimination of | |
| 663 the frame pointer in leaf functions. */ | |
| 664 #define TARGET_DEFAULT 0 | |
| 665 | |
| 666 /* Extra bits to force. */ | |
| 667 #define TARGET_SUBTARGET_DEFAULT 0 | |
| 668 #define TARGET_SUBTARGET_ISA_DEFAULT 0 | |
| 669 | |
| 670 /* Extra bits to force on w/ 32-bit mode. */ | |
| 671 #define TARGET_SUBTARGET32_DEFAULT 0 | |
| 672 #define TARGET_SUBTARGET32_ISA_DEFAULT 0 | |
| 673 | |
| 674 /* Extra bits to force on w/ 64-bit mode. */ | |
| 675 #define TARGET_SUBTARGET64_DEFAULT 0 | |
| 145 | 676 /* Enable MMX, SSE and SSE2 by default. */ |
| 677 #define TARGET_SUBTARGET64_ISA_DEFAULT \ | |
| 678 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2) | |
| 0 | 679 |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
680 /* Replace MACH-O, ifdefs by in-line tests, where possible. |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
681 (a) Macros defined in config/i386/darwin.h */ |
| 0 | 682 #define TARGET_MACHO 0 |
| 145 | 683 #define TARGET_MACHO_SYMBOL_STUBS 0 |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
684 #define MACHOPIC_ATT_STUB 0 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
685 /* (b) Macros defined in config/darwin.h */ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
686 #define MACHO_DYNAMIC_NO_PIC_P 0 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
687 #define MACHOPIC_INDIRECT 0 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
688 #define MACHOPIC_PURE 0 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
689 |
| 111 | 690 /* For the RDOS */ |
| 691 #define TARGET_RDOS 0 | |
| 692 | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
693 /* For the Windows 64-bit ABI. */ |
| 0 | 694 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) |
| 695 | |
| 111 | 696 /* For the Windows 32-bit ABI. */ |
| 697 #define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI) | |
| 698 | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
699 /* This is re-defined by cygming.h. */ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
700 #define TARGET_SEH 0 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
701 |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
702 /* The default abi used by target. */ |
| 0 | 703 #define DEFAULT_ABI SYSV_ABI |
| 704 | |
| 111 | 705 /* The default TLS segment register used by target. */ |
| 706 #define DEFAULT_TLS_SEG_REG \ | |
| 707 (TARGET_64BIT ? ADDR_SPACE_SEG_FS : ADDR_SPACE_SEG_GS) | |
| 708 | |
| 0 | 709 /* Subtargets may reset this to 1 in order to enable 96-bit long double |
| 710 with the rounding mode forced to 53 bits. */ | |
| 711 #define TARGET_96_ROUND_53_LONG_DOUBLE 0 | |
| 712 | |
| 145 | 713 #ifndef SUBTARGET_DRIVER_SELF_SPECS |
| 714 # define SUBTARGET_DRIVER_SELF_SPECS "" | |
| 715 #endif | |
| 716 | |
| 717 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS | |
| 718 | |
| 0 | 719 /* -march=native handling only makes sense with compiler running on |
| 720 an x86 or x86_64 chip. If changing this condition, also change | |
| 721 the condition in driver-i386.c. */ | |
| 722 #if defined(__i386__) || defined(__x86_64__) | |
| 723 /* In driver-i386.c. */ | |
| 724 extern const char *host_detect_local_cpu (int argc, const char **argv); | |
| 725 #define EXTRA_SPEC_FUNCTIONS \ | |
| 726 { "local_cpu_detect", host_detect_local_cpu }, | |
| 727 #define HAVE_LOCAL_CPU_DETECT | |
| 728 #endif | |
| 729 | |
| 730 #if TARGET_64BIT_DEFAULT | |
| 731 #define OPT_ARCH64 "!m32" | |
| 732 #define OPT_ARCH32 "m32" | |
| 733 #else | |
| 111 | 734 #define OPT_ARCH64 "m64|mx32" |
| 735 #define OPT_ARCH32 "m64|mx32:;" | |
| 0 | 736 #endif |
| 737 | |
| 738 /* Support for configure-time defaults of some command line options. | |
| 739 The order here is important so that -march doesn't squash the | |
| 740 tune or cpu values. */ | |
| 741 #define OPTION_DEFAULT_SPECS \ | |
| 742 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ | |
| 743 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
| 744 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
| 745 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ | |
| 746 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
| 747 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
| 748 {"arch", "%{!march=*:-march=%(VALUE)}"}, \ | |
| 749 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ | |
| 750 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, | |
| 751 | |
| 752 /* Specs for the compiler proper */ | |
| 753 | |
| 754 #ifndef CC1_CPU_SPEC | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
755 #define CC1_CPU_SPEC_1 "" |
| 0 | 756 |
| 757 #ifndef HAVE_LOCAL_CPU_DETECT | |
| 758 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 | |
| 759 #else | |
| 760 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
761 "%{march=native:%>march=native %:local_cpu_detect(arch) \ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
762 %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
763 %{mtune=native:%>mtune=native %:local_cpu_detect(tune)}" |
| 0 | 764 #endif |
| 765 #endif | |
| 766 | |
| 767 /* Target CPU builtins. */ | |
| 768 #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () | |
| 769 | |
| 770 /* Target Pragmas. */ | |
| 771 #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () | |
| 772 | |
| 145 | 773 /* Target CPU versions for D. */ |
| 774 #define TARGET_D_CPU_VERSIONS ix86_d_target_versions | |
| 775 | |
| 0 | 776 #ifndef CC1_SPEC |
| 777 #define CC1_SPEC "%(cc1_cpu) " | |
| 778 #endif | |
| 779 | |
| 780 /* This macro defines names of additional specifications to put in the | |
| 781 specs that can be used in various specifications like CC1_SPEC. Its | |
| 782 definition is an initializer with a subgrouping for each command option. | |
| 783 | |
| 784 Each subgrouping contains a string constant, that defines the | |
| 785 specification name, and a string constant that used by the GCC driver | |
| 786 program. | |
| 787 | |
| 788 Do not define this macro if it does not need to do anything. */ | |
| 789 | |
| 790 #ifndef SUBTARGET_EXTRA_SPECS | |
| 791 #define SUBTARGET_EXTRA_SPECS | |
| 792 #endif | |
| 793 | |
| 794 #define EXTRA_SPECS \ | |
| 795 { "cc1_cpu", CC1_CPU_SPEC }, \ | |
| 796 SUBTARGET_EXTRA_SPECS | |
| 797 | |
| 798 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
799 /* Whether to allow x87 floating-point arithmetic on MODE (one of |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
800 SFmode, DFmode and XFmode) in the current excess precision |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
801 configuration. */ |
| 111 | 802 #define X87_ENABLE_ARITH(MODE) \ |
| 803 (flag_unsafe_math_optimizations \ | |
| 804 || flag_excess_precision == EXCESS_PRECISION_FAST \ | |
| 805 || (MODE) == XFmode) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
806 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
807 /* Likewise, whether to allow direct conversions from integer mode |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
808 IMODE (HImode, SImode or DImode) to MODE. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
809 #define X87_ENABLE_FLOAT(MODE, IMODE) \ |
| 111 | 810 (flag_unsafe_math_optimizations \ |
| 811 || flag_excess_precision == EXCESS_PRECISION_FAST \ | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
812 || (MODE) == XFmode \ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
813 || ((MODE) == DFmode && (IMODE) == SImode) \ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
814 || (IMODE) == HImode) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
815 |
| 0 | 816 /* target machine storage layout */ |
| 817 | |
| 818 #define SHORT_TYPE_SIZE 16 | |
| 819 #define INT_TYPE_SIZE 32 | |
| 111 | 820 #define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) |
| 821 #define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
822 #define LONG_LONG_TYPE_SIZE 64 |
| 0 | 823 #define FLOAT_TYPE_SIZE 32 |
| 824 #define DOUBLE_TYPE_SIZE 64 | |
| 111 | 825 #define LONG_DOUBLE_TYPE_SIZE \ |
| 826 (TARGET_LONG_DOUBLE_64 ? 64 : (TARGET_LONG_DOUBLE_128 ? 128 : 80)) | |
| 827 | |
| 828 #define WIDEST_HARDWARE_FP_SIZE 80 | |
| 0 | 829 |
| 830 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT | |
| 831 #define MAX_BITS_PER_WORD 64 | |
| 832 #else | |
| 833 #define MAX_BITS_PER_WORD 32 | |
| 834 #endif | |
| 835 | |
| 836 /* Define this if most significant byte of a word is the lowest numbered. */ | |
| 837 /* That is true on the 80386. */ | |
| 838 | |
| 839 #define BITS_BIG_ENDIAN 0 | |
| 840 | |
| 841 /* Define this if most significant byte of a word is the lowest numbered. */ | |
| 842 /* That is not true on the 80386. */ | |
| 843 #define BYTES_BIG_ENDIAN 0 | |
| 844 | |
| 845 /* Define this if most significant word of a multiword number is the lowest | |
| 846 numbered. */ | |
| 847 /* Not true for 80386 */ | |
| 848 #define WORDS_BIG_ENDIAN 0 | |
| 849 | |
| 850 /* Width of a word, in units (bytes). */ | |
| 851 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
852 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
853 #ifndef IN_LIBGCC2 |
| 0 | 854 #define MIN_UNITS_PER_WORD 4 |
| 855 #endif | |
| 856 | |
| 857 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
| 858 #define PARM_BOUNDARY BITS_PER_WORD | |
| 859 | |
| 860 /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
| 145 | 861 #define STACK_BOUNDARY (TARGET_64BIT_MS_ABI ? 128 : BITS_PER_WORD) |
| 0 | 862 |
| 863 /* Stack boundary of the main function guaranteed by OS. */ | |
| 864 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) | |
| 865 | |
| 866 /* Minimum stack boundary. */ | |
| 111 | 867 #define MIN_STACK_BOUNDARY BITS_PER_WORD |
| 0 | 868 |
| 869 /* Boundary (in *bits*) on which the stack pointer prefers to be | |
| 870 aligned; the compiler cannot rely on having this alignment. */ | |
| 871 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary | |
| 872 | |
| 873 /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for | |
| 874 both 32bit and 64bit, to support codes that need 128 bit stack | |
| 875 alignment for SSE instructions, but can't realign the stack. */ | |
| 111 | 876 #define PREFERRED_STACK_BOUNDARY_DEFAULT \ |
| 877 (TARGET_IAMCU ? MIN_STACK_BOUNDARY : 128) | |
| 0 | 878 |
| 879 /* 1 if -mstackrealign should be turned on by default. It will | |
| 880 generate an alternate prologue and epilogue that realigns the | |
| 881 runtime stack if nessary. This supports mixing codes that keep a | |
| 882 4-byte aligned stack, as specified by i386 psABI, with codes that | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
883 need a 16-byte aligned stack, as required by SSE instructions. */ |
| 0 | 884 #define STACK_REALIGN_DEFAULT 0 |
| 885 | |
| 886 /* Boundary (in *bits*) on which the incoming stack is aligned. */ | |
| 887 #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary | |
| 888 | |
| 111 | 889 /* According to Windows x64 software convention, the maximum stack allocatable |
| 890 in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of | |
| 891 instructions allowed to adjust the stack pointer in the epilog, forcing the | |
| 892 use of frame pointer for frames larger than 2 GB. This theorical limit | |
| 893 is reduced by 256, an over-estimated upper bound for the stack use by the | |
| 894 prologue. | |
| 895 We define only one threshold for both the prolog and the epilog. When the | |
| 896 frame size is larger than this threshold, we allocate the area to save SSE | |
| 897 regs, then save them, and then allocate the remaining. There is no SEH | |
| 898 unwind info for this later allocation. */ | |
| 899 #define SEH_MAX_FRAME_SIZE ((2U << 30) - 256) | |
| 900 | |
| 0 | 901 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is |
| 902 mandatory for the 64-bit ABI, and may or may not be true for other | |
| 903 operating systems. */ | |
| 904 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT | |
| 905 | |
| 906 /* Minimum allocation boundary for the code of a function. */ | |
| 907 #define FUNCTION_BOUNDARY 8 | |
| 908 | |
| 909 /* C++ stores the virtual bit in the lowest bit of function pointers. */ | |
| 910 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn | |
| 911 | |
| 912 /* Minimum size in bits of the largest boundary to which any | |
| 913 and all fundamental data types supported by the hardware | |
| 914 might need to be aligned. No data type wants to be aligned | |
| 915 rounder than this. | |
| 916 | |
| 917 Pentium+ prefers DFmode values to be aligned to 64 bit boundary | |
| 111 | 918 and Pentium Pro XFmode values at 128 bit boundaries. |
| 919 | |
| 920 When increasing the maximum, also update | |
| 921 TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */ | |
| 922 | |
| 923 #define BIGGEST_ALIGNMENT \ | |
| 924 (TARGET_IAMCU ? 32 : (TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128))) | |
| 0 | 925 |
| 926 /* Maximum stack alignment. */ | |
| 927 #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT | |
| 928 | |
| 929 /* Alignment value for attribute ((aligned)). It is a constant since | |
| 930 it is the part of the ABI. We shouldn't change it with -mavx. */ | |
| 111 | 931 #define ATTRIBUTE_ALIGNED_VALUE (TARGET_IAMCU ? 32 : 128) |
| 0 | 932 |
| 933 /* Decide whether a variable of mode MODE should be 128 bit aligned. */ | |
| 934 #define ALIGN_MODE_128(MODE) \ | |
| 935 ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) | |
| 936 | |
| 937 /* The published ABIs say that doubles should be aligned on word | |
| 938 boundaries, so lower the alignment for structure fields unless | |
| 939 -malign-double is set. */ | |
| 940 | |
| 941 /* ??? Blah -- this macro is used directly by libobjc. Since it | |
| 942 supports no vector modes, cut out the complexity and fall back | |
| 943 on BIGGEST_FIELD_ALIGNMENT. */ | |
| 944 #ifdef IN_TARGET_LIBS | |
| 945 #ifdef __x86_64__ | |
| 946 #define BIGGEST_FIELD_ALIGNMENT 128 | |
| 947 #else | |
| 948 #define BIGGEST_FIELD_ALIGNMENT 32 | |
| 949 #endif | |
| 950 #else | |
| 111 | 951 #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \ |
| 952 x86_field_alignment ((TYPE), (COMPUTED)) | |
| 0 | 953 #endif |
| 954 | |
| 955 /* If defined, a C expression to compute the alignment for a static | |
| 956 variable. TYPE is the data type, and ALIGN is the alignment that | |
| 957 the object would ordinarily have. The value of this macro is used | |
| 958 instead of that alignment to align the object. | |
| 959 | |
| 960 If this macro is not defined, then ALIGN is used. | |
| 961 | |
| 962 One use of this macro is to increase alignment of medium-size | |
| 963 data to make it all fit in fewer cache lines. Another is to | |
| 964 cause character arrays to be word-aligned so that `strcpy' calls | |
| 965 that copy constants to character arrays can be done inline. */ | |
| 966 | |
| 111 | 967 #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
| 968 ix86_data_alignment ((TYPE), (ALIGN), true) | |
| 969 | |
| 970 /* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates | |
| 971 some alignment increase, instead of optimization only purposes. E.g. | |
| 972 AMD x86-64 psABI says that variables with array type larger than 15 bytes | |
| 973 must be aligned to 16 byte boundaries. | |
| 974 | |
| 975 If this macro is not defined, then ALIGN is used. */ | |
| 976 | |
| 977 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ | |
| 978 ix86_data_alignment ((TYPE), (ALIGN), false) | |
| 0 | 979 |
| 980 /* If defined, a C expression to compute the alignment for a local | |
| 981 variable. TYPE is the data type, and ALIGN is the alignment that | |
| 982 the object would ordinarily have. The value of this macro is used | |
| 983 instead of that alignment to align the object. | |
| 984 | |
| 985 If this macro is not defined, then ALIGN is used. | |
| 986 | |
| 987 One use of this macro is to increase alignment of medium-size | |
| 988 data to make it all fit in fewer cache lines. */ | |
| 989 | |
| 990 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
| 991 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) | |
| 992 | |
| 993 /* If defined, a C expression to compute the alignment for stack slot. | |
| 994 TYPE is the data type, MODE is the widest mode available, and ALIGN | |
| 995 is the alignment that the slot would ordinarily have. The value of | |
| 996 this macro is used instead of that alignment to align the slot. | |
| 997 | |
| 998 If this macro is not defined, then ALIGN is used when TYPE is NULL, | |
| 999 Otherwise, LOCAL_ALIGNMENT will be used. | |
| 1000 | |
| 1001 One use of this macro is to set alignment of stack slot to the | |
| 1002 maximum alignment of all possible modes which the slot may have. */ | |
| 1003 | |
| 1004 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ | |
| 1005 ix86_local_alignment ((TYPE), (MODE), (ALIGN)) | |
| 1006 | |
| 1007 /* If defined, a C expression to compute the alignment for a local | |
| 1008 variable DECL. | |
| 1009 | |
| 1010 If this macro is not defined, then | |
| 1011 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. | |
| 1012 | |
| 1013 One use of this macro is to increase alignment of medium-size | |
| 1014 data to make it all fit in fewer cache lines. */ | |
| 1015 | |
| 1016 #define LOCAL_DECL_ALIGNMENT(DECL) \ | |
| 1017 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) | |
| 1018 | |
|
19
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
1019 /* If defined, a C expression to compute the minimum required alignment |
|
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
1020 for dynamic stack realignment purposes for EXP (a TYPE or DECL), |
|
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
1021 MODE, assuming normal alignment ALIGN. |
|
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
1022 |
|
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
1023 If this macro is not defined, then (ALIGN) will be used. */ |
|
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
1024 |
|
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
1025 #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ |
| 111 | 1026 ix86_minimum_alignment ((EXP), (MODE), (ALIGN)) |
|
19
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
1027 |
| 0 | 1028 |
| 1029 /* Set this nonzero if move instructions will actually fail to work | |
| 1030 when given unaligned data. */ | |
| 1031 #define STRICT_ALIGNMENT 0 | |
| 1032 | |
| 1033 /* If bit field type is int, don't let it cross an int, | |
| 1034 and give entire struct the alignment of an int. */ | |
| 1035 /* Required on the 386 since it doesn't have bit-field insns. */ | |
| 1036 #define PCC_BITFIELD_TYPE_MATTERS 1 | |
| 1037 | |
| 1038 /* Standard register usage. */ | |
| 1039 | |
| 1040 /* This processor has special stack-like registers. See reg-stack.c | |
| 1041 for details. */ | |
| 1042 | |
| 1043 #define STACK_REGS | |
| 1044 | |
| 111 | 1045 #define IS_STACK_MODE(MODE) \ |
| 1046 (X87_FLOAT_MODE_P (MODE) \ | |
| 1047 && (!(SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \ | |
| 1048 || TARGET_MIX_SSE_I387)) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1049 |
| 0 | 1050 /* Number of actual hardware registers. |
| 1051 The hardware registers are assigned numbers for the compiler | |
| 1052 from 0 to just below FIRST_PSEUDO_REGISTER. | |
| 1053 All registers that the compiler knows about must be given numbers, | |
| 1054 even those that are not normally considered general registers. | |
| 1055 | |
| 1056 In the 80386 we give the 8 general purpose registers the numbers 0-7. | |
| 1057 We number the floating point registers 8-15. | |
| 1058 Note that registers 0-7 can be accessed as a short or int, | |
| 1059 while only 0-3 may be used with byte `mov' instructions. | |
| 1060 | |
| 1061 Reg 16 does not correspond to any hardware register, but instead | |
| 1062 appears in the RTL as an argument pointer prior to reload, and is | |
| 1063 eliminated during reloading in favor of either the stack or frame | |
| 1064 pointer. */ | |
| 1065 | |
| 111 | 1066 #define FIRST_PSEUDO_REGISTER FIRST_PSEUDO_REG |
| 0 | 1067 |
| 1068 /* Number of hardware registers that go into the DWARF-2 unwind info. | |
| 1069 If not defined, equals FIRST_PSEUDO_REGISTER. */ | |
| 1070 | |
| 1071 #define DWARF_FRAME_REGISTERS 17 | |
| 1072 | |
| 1073 /* 1 for registers that have pervasive standard uses | |
| 1074 and are not available for the register allocator. | |
| 1075 On the 80386, the stack pointer is such, as is the arg pointer. | |
| 1076 | |
| 111 | 1077 REX registers are disabled for 32bit targets in |
| 1078 TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
| 1079 | |
| 0 | 1080 #define FIXED_REGISTERS \ |
| 1081 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
| 1082 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 131 | 1083 /*arg,flags,fpsr,frame*/ \ |
| 1084 1, 1, 1, 1, \ | |
| 0 | 1085 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
| 1086 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1087 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ | |
| 1088 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1089 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
| 111 | 1090 0, 0, 0, 0, 0, 0, 0, 0, \ |
| 0 | 1091 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
| 111 | 1092 0, 0, 0, 0, 0, 0, 0, 0, \ |
| 1093 /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ | |
| 1094 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1095 /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ | |
| 1096 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1097 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ | |
| 131 | 1098 0, 0, 0, 0, 0, 0, 0, 0 } |
| 0 | 1099 |
| 1100 /* 1 for registers not available across function calls. | |
| 1101 These must include the FIXED_REGISTERS and also any | |
| 1102 registers that can be used without being saved. | |
| 1103 The latter must include the registers where values are returned | |
| 1104 and the register where structure-value addresses are passed. | |
| 1105 Aside from that, you can include as many other registers as you like. | |
| 1106 | |
| 111 | 1107 Value is set to 1 if the register is call used unconditionally. |
| 1108 Bit one is set if the register is call used on TARGET_32BIT ABI. | |
| 1109 Bit two is set if the register is call used on TARGET_64BIT ABI. | |
| 1110 Bit three is set if the register is call used on TARGET_64BIT_MS_ABI. | |
| 1111 | |
| 1112 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
| 1113 | |
| 1114 #define CALL_USED_REGISTERS_MASK(IS_64BIT_MS_ABI) \ | |
| 1115 ((IS_64BIT_MS_ABI) ? (1 << 3) : TARGET_64BIT ? (1 << 2) : (1 << 1)) | |
| 1116 | |
| 0 | 1117 #define CALL_USED_REGISTERS \ |
| 1118 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
| 111 | 1119 { 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
| 131 | 1120 /*arg,flags,fpsr,frame*/ \ |
| 1121 1, 1, 1, 1, \ | |
| 0 | 1122 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
| 111 | 1123 1, 1, 1, 1, 1, 1, 6, 6, \ |
| 0 | 1124 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ |
| 1125 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 1126 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
| 1127 1, 1, 1, 1, 2, 2, 2, 2, \ | |
| 1128 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ | |
| 111 | 1129 6, 6, 6, 6, 6, 6, 6, 6, \ |
| 1130 /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ | |
| 145 | 1131 1, 1, 1, 1, 1, 1, 1, 1, \ |
| 111 | 1132 /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ |
| 145 | 1133 1, 1, 1, 1, 1, 1, 1, 1, \ |
| 111 | 1134 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ |
| 131 | 1135 1, 1, 1, 1, 1, 1, 1, 1 } |
| 0 | 1136 |
| 1137 /* Order in which to allocate registers. Each register must be | |
| 1138 listed once, even those in FIXED_REGISTERS. List frame pointer | |
| 1139 late and fixed registers last. Note that, in general, we prefer | |
| 1140 registers listed in CALL_USED_REGISTERS, keeping the others | |
| 1141 available for storage of persistent values. | |
| 1142 | |
|
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1143 The ADJUST_REG_ALLOC_ORDER actually overwrite the order, |
| 0 | 1144 so this is just empty initializer for array. */ |
| 1145 | |
| 131 | 1146 #define REG_ALLOC_ORDER \ |
| 1147 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ | |
| 1148 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ | |
| 1149 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
| 1150 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ | |
| 1151 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 } | |
| 0 | 1152 |
|
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1153 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order |
| 0 | 1154 to be rearranged based on a particular function. When using sse math, |
| 1155 we want to allocate SSE before x87 registers and vice versa. */ | |
| 1156 | |
|
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1157 #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () |
| 0 | 1158 |
| 1159 | |
| 1160 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) | |
| 1161 | |
| 1162 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ | |
| 111 | 1163 (TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT \ |
| 1164 && GENERAL_REGNO_P (REGNO) \ | |
| 1165 && ((MODE) == XFmode || (MODE) == XCmode)) | |
| 0 | 1166 |
| 1167 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) | |
| 1168 | |
| 145 | 1169 #define REGMODE_NATURAL_SIZE(MODE) ix86_regmode_natural_size (MODE) |
| 1170 | |
| 0 | 1171 #define VALID_AVX256_REG_MODE(MODE) \ |
| 1172 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ | |
| 111 | 1173 || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \ |
| 1174 || (MODE) == V4DFmode) | |
| 1175 | |
| 1176 #define VALID_AVX256_REG_OR_OI_MODE(MODE) \ | |
| 1177 (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode) | |
| 1178 | |
| 1179 #define VALID_AVX512F_SCALAR_MODE(MODE) \ | |
| 1180 ((MODE) == DImode || (MODE) == DFmode || (MODE) == SImode \ | |
| 1181 || (MODE) == SFmode) | |
| 1182 | |
| 1183 #define VALID_AVX512F_REG_MODE(MODE) \ | |
| 1184 ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \ | |
| 1185 || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \ | |
| 1186 || (MODE) == V4TImode) | |
| 1187 | |
| 131 | 1188 #define VALID_AVX512F_REG_OR_XI_MODE(MODE) \ |
| 1189 (VALID_AVX512F_REG_MODE (MODE) || (MODE) == XImode) | |
| 1190 | |
| 111 | 1191 #define VALID_AVX512VL_128_REG_MODE(MODE) \ |
| 1192 ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \ | |
| 1193 || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode \ | |
| 1194 || (MODE) == TFmode || (MODE) == V1TImode) | |
| 0 | 1195 |
| 1196 #define VALID_SSE2_REG_MODE(MODE) \ | |
| 1197 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
| 1198 || (MODE) == V2DImode || (MODE) == DFmode) | |
| 1199 | |
| 1200 #define VALID_SSE_REG_MODE(MODE) \ | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1201 ((MODE) == V1TImode || (MODE) == TImode \ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1202 || (MODE) == V4SFmode || (MODE) == V4SImode \ |
| 0 | 1203 || (MODE) == SFmode || (MODE) == TFmode) |
| 1204 | |
| 1205 #define VALID_MMX_REG_MODE_3DNOW(MODE) \ | |
| 1206 ((MODE) == V2SFmode || (MODE) == SFmode) | |
| 1207 | |
| 1208 #define VALID_MMX_REG_MODE(MODE) \ | |
| 145 | 1209 ((MODE) == V1DImode || (MODE) == DImode \ |
| 0 | 1210 || (MODE) == V2SImode || (MODE) == SImode \ |
| 1211 || (MODE) == V4HImode || (MODE) == V8QImode) | |
| 1212 | |
| 111 | 1213 #define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode) |
| 1214 | |
| 1215 #define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode) | |
| 1216 | |
| 0 | 1217 #define VALID_DFP_MODE_P(MODE) \ |
| 1218 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) | |
| 1219 | |
| 1220 #define VALID_FP_MODE_P(MODE) \ | |
| 1221 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ | |
| 1222 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ | |
| 1223 | |
| 1224 #define VALID_INT_MODE_P(MODE) \ | |
| 1225 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ | |
| 1226 || (MODE) == DImode \ | |
| 1227 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ | |
| 1228 || (MODE) == CDImode \ | |
| 1229 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ | |
| 1230 || (MODE) == TFmode || (MODE) == TCmode))) | |
| 1231 | |
| 1232 /* Return true for modes passed in SSE registers. */ | |
| 1233 #define SSE_REG_MODE_P(MODE) \ | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1234 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1235 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1236 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1237 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ |
| 111 | 1238 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \ |
| 1239 || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \ | |
| 1240 || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \ | |
| 1241 || (MODE) == V16SFmode) | |
| 1242 | |
| 1243 #define X87_FLOAT_MODE_P(MODE) \ | |
| 1244 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) | |
| 1245 | |
| 1246 #define SSE_FLOAT_MODE_P(MODE) \ | |
| 1247 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) | |
| 1248 | |
| 1249 #define FMA4_VEC_FLOAT_MODE_P(MODE) \ | |
| 1250 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \ | |
| 1251 || (MODE) == V8SFmode || (MODE) == V4DFmode)) | |
| 0 | 1252 |
| 1253 /* It is possible to write patterns to move flags; but until someone | |
| 1254 does it, */ | |
| 1255 #define AVOID_CCMODE_COPIES | |
| 1256 | |
| 1257 /* Specify the modes required to caller save a given hard regno. | |
| 1258 We do this on i386 to prevent flags from being saved at all. | |
| 1259 | |
| 1260 Kill any attempts to combine saving of modes. */ | |
| 1261 | |
| 1262 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ | |
| 1263 (CC_REGNO_P (REGNO) ? VOIDmode \ | |
| 1264 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ | |
| 145 | 1265 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), NULL) \ |
| 111 | 1266 : (MODE) == HImode && !((GENERAL_REGNO_P (REGNO) \ |
| 1267 && TARGET_PARTIAL_REG_STALL) \ | |
| 1268 || MASK_REGNO_P (REGNO)) ? SImode \ | |
| 1269 : (MODE) == QImode && !(ANY_QI_REGNO_P (REGNO) \ | |
| 1270 || MASK_REGNO_P (REGNO)) ? SImode \ | |
| 0 | 1271 : (MODE)) |
| 1272 | |
| 1273 /* Specify the registers used for certain standard purposes. | |
| 1274 The values of these macros are register numbers. */ | |
| 1275 | |
| 1276 /* on the 386 the pc register is %eip, and is not usable as a general | |
| 1277 register. The ordinary mov instructions won't work */ | |
| 1278 /* #define PC_REGNUM */ | |
| 1279 | |
| 111 | 1280 /* Base register for access to arguments of the function. */ |
| 1281 #define ARG_POINTER_REGNUM ARGP_REG | |
| 1282 | |
| 0 | 1283 /* Register to use for pushing function arguments. */ |
| 111 | 1284 #define STACK_POINTER_REGNUM SP_REG |
| 0 | 1285 |
| 1286 /* Base register for access to local variables of the function. */ | |
| 111 | 1287 #define FRAME_POINTER_REGNUM FRAME_REG |
| 1288 #define HARD_FRAME_POINTER_REGNUM BP_REG | |
| 1289 | |
| 1290 #define FIRST_INT_REG AX_REG | |
| 1291 #define LAST_INT_REG SP_REG | |
| 1292 | |
| 1293 #define FIRST_QI_REG AX_REG | |
| 1294 #define LAST_QI_REG BX_REG | |
| 0 | 1295 |
| 1296 /* First & last stack-like regs */ | |
| 111 | 1297 #define FIRST_STACK_REG ST0_REG |
| 1298 #define LAST_STACK_REG ST7_REG | |
| 1299 | |
| 1300 #define FIRST_SSE_REG XMM0_REG | |
| 1301 #define LAST_SSE_REG XMM7_REG | |
| 1302 | |
| 1303 #define FIRST_MMX_REG MM0_REG | |
| 1304 #define LAST_MMX_REG MM7_REG | |
| 1305 | |
| 1306 #define FIRST_REX_INT_REG R8_REG | |
| 1307 #define LAST_REX_INT_REG R15_REG | |
| 1308 | |
| 1309 #define FIRST_REX_SSE_REG XMM8_REG | |
| 1310 #define LAST_REX_SSE_REG XMM15_REG | |
| 1311 | |
| 1312 #define FIRST_EXT_REX_SSE_REG XMM16_REG | |
| 1313 #define LAST_EXT_REX_SSE_REG XMM31_REG | |
| 1314 | |
| 1315 #define FIRST_MASK_REG MASK0_REG | |
| 1316 #define LAST_MASK_REG MASK7_REG | |
| 1317 | |
| 0 | 1318 /* Override this in other tm.h files to cope with various OS lossage |
| 1319 requiring a frame pointer. */ | |
| 1320 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
| 1321 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
| 1322 #endif | |
| 1323 | |
| 1324 /* Make sure we can access arbitrary call frames. */ | |
| 1325 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () | |
| 1326 | |
| 1327 /* Register to hold the addressing base for position independent | |
| 1328 code access to data items. We don't use PIC pointer for 64bit | |
| 1329 mode. Define the regnum to dummy value to prevent gcc from | |
| 1330 pessimizing code dealing with EBX. | |
| 1331 | |
| 1332 To avoid clobbering a call-saved register unnecessarily, we renumber | |
| 1333 the pic register when possible. The change is visible after the | |
| 1334 prologue has been emitted. */ | |
| 1335 | |
| 111 | 1336 #define REAL_PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? R15_REG : BX_REG) |
| 1337 | |
| 1338 #define PIC_OFFSET_TABLE_REGNUM \ | |
| 1339 (ix86_use_pseudo_pic_reg () \ | |
| 1340 ? (pic_offset_table_rtx \ | |
| 1341 ? INVALID_REGNUM \ | |
| 1342 : REAL_PIC_OFFSET_TABLE_REGNUM) \ | |
| 1343 : INVALID_REGNUM) | |
| 0 | 1344 |
| 1345 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" | |
| 1346 | |
| 1347 /* This is overridden by <cygwin.h>. */ | |
| 1348 #define MS_AGGREGATE_RETURN 0 | |
| 1349 | |
| 1350 #define KEEP_AGGREGATE_RETURN_POINTER 0 | |
| 1351 | |
| 1352 /* Define the classes of registers for register constraints in the | |
| 1353 machine description. Also define ranges of constants. | |
| 1354 | |
| 1355 One of the classes must always be named ALL_REGS and include all hard regs. | |
| 1356 If there is more than one class, another class must be named NO_REGS | |
| 1357 and contain no registers. | |
| 1358 | |
| 1359 The name GENERAL_REGS must be the name of a class (or an alias for | |
| 1360 another name such as ALL_REGS). This is the class of registers | |
| 1361 that is allowed by "g" or "r" in a register constraint. | |
| 1362 Also, registers outside this class are allocated only when | |
| 1363 instructions express preferences for them. | |
| 1364 | |
| 1365 The classes must be numbered in nondecreasing order; that is, | |
| 1366 a larger-numbered class must never be contained completely | |
| 111 | 1367 in a smaller-numbered class. This is why CLOBBERED_REGS class |
| 1368 is listed early, even though in 64-bit mode it contains more | |
| 1369 registers than just %eax, %ecx, %edx. | |
| 0 | 1370 |
| 1371 For any two classes, it is very desirable that there be another | |
| 1372 class that represents their union. | |
| 1373 | |
| 131 | 1374 The flags and fpsr registers are in no class. */ |
| 0 | 1375 |
| 1376 enum reg_class | |
| 1377 { | |
| 1378 NO_REGS, | |
| 1379 AREG, DREG, CREG, BREG, SIREG, DIREG, | |
| 1380 AD_REGS, /* %eax/%edx for DImode */ | |
| 111 | 1381 CLOBBERED_REGS, /* call-clobbered integer registers */ |
| 0 | 1382 Q_REGS, /* %eax %ebx %ecx %edx */ |
| 1383 NON_Q_REGS, /* %esi %edi %ebp %esp */ | |
| 111 | 1384 TLS_GOTBASE_REGS, /* %ebx %ecx %edx %esi %edi %ebp */ |
| 0 | 1385 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ |
| 1386 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1387 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1388 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ |
| 0 | 1389 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ |
| 1390 FLOAT_REGS, | |
| 1391 SSE_FIRST_REG, | |
| 111 | 1392 NO_REX_SSE_REGS, |
| 0 | 1393 SSE_REGS, |
| 111 | 1394 ALL_SSE_REGS, |
| 0 | 1395 MMX_REGS, |
| 1396 FLOAT_SSE_REGS, | |
| 1397 FLOAT_INT_REGS, | |
| 1398 INT_SSE_REGS, | |
| 1399 FLOAT_INT_SSE_REGS, | |
| 111 | 1400 MASK_REGS, |
| 131 | 1401 ALL_MASK_REGS, |
| 1402 ALL_REGS, | |
| 1403 LIM_REG_CLASSES | |
| 0 | 1404 }; |
| 1405 | |
| 1406 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) | |
| 1407 | |
| 1408 #define INTEGER_CLASS_P(CLASS) \ | |
| 1409 reg_class_subset_p ((CLASS), GENERAL_REGS) | |
| 1410 #define FLOAT_CLASS_P(CLASS) \ | |
| 1411 reg_class_subset_p ((CLASS), FLOAT_REGS) | |
| 1412 #define SSE_CLASS_P(CLASS) \ | |
| 111 | 1413 reg_class_subset_p ((CLASS), ALL_SSE_REGS) |
| 0 | 1414 #define MMX_CLASS_P(CLASS) \ |
| 1415 ((CLASS) == MMX_REGS) | |
| 111 | 1416 #define MASK_CLASS_P(CLASS) \ |
| 131 | 1417 reg_class_subset_p ((CLASS), ALL_MASK_REGS) |
| 0 | 1418 #define MAYBE_INTEGER_CLASS_P(CLASS) \ |
| 1419 reg_classes_intersect_p ((CLASS), GENERAL_REGS) | |
| 1420 #define MAYBE_FLOAT_CLASS_P(CLASS) \ | |
| 1421 reg_classes_intersect_p ((CLASS), FLOAT_REGS) | |
| 1422 #define MAYBE_SSE_CLASS_P(CLASS) \ | |
| 111 | 1423 reg_classes_intersect_p ((CLASS), ALL_SSE_REGS) |
| 0 | 1424 #define MAYBE_MMX_CLASS_P(CLASS) \ |
| 111 | 1425 reg_classes_intersect_p ((CLASS), MMX_REGS) |
| 1426 #define MAYBE_MASK_CLASS_P(CLASS) \ | |
| 131 | 1427 reg_classes_intersect_p ((CLASS), ALL_MASK_REGS) |
| 0 | 1428 |
| 1429 #define Q_CLASS_P(CLASS) \ | |
| 1430 reg_class_subset_p ((CLASS), Q_REGS) | |
| 1431 | |
| 111 | 1432 #define MAYBE_NON_Q_CLASS_P(CLASS) \ |
| 1433 reg_classes_intersect_p ((CLASS), NON_Q_REGS) | |
| 1434 | |
| 0 | 1435 /* Give names of register classes as strings for dump file. */ |
| 1436 | |
| 1437 #define REG_CLASS_NAMES \ | |
| 1438 { "NO_REGS", \ | |
| 1439 "AREG", "DREG", "CREG", "BREG", \ | |
| 1440 "SIREG", "DIREG", \ | |
| 1441 "AD_REGS", \ | |
|
19
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
1442 "CLOBBERED_REGS", \ |
| 0 | 1443 "Q_REGS", "NON_Q_REGS", \ |
| 111 | 1444 "TLS_GOTBASE_REGS", \ |
| 0 | 1445 "INDEX_REGS", \ |
| 1446 "LEGACY_REGS", \ | |
| 1447 "GENERAL_REGS", \ | |
| 1448 "FP_TOP_REG", "FP_SECOND_REG", \ | |
| 1449 "FLOAT_REGS", \ | |
| 1450 "SSE_FIRST_REG", \ | |
| 111 | 1451 "NO_REX_SSE_REGS", \ |
| 0 | 1452 "SSE_REGS", \ |
| 111 | 1453 "ALL_SSE_REGS", \ |
| 0 | 1454 "MMX_REGS", \ |
| 1455 "FLOAT_SSE_REGS", \ | |
| 1456 "FLOAT_INT_REGS", \ | |
| 1457 "INT_SSE_REGS", \ | |
| 1458 "FLOAT_INT_SSE_REGS", \ | |
| 111 | 1459 "MASK_REGS", \ |
| 131 | 1460 "ALL_MASK_REGS", \ |
| 0 | 1461 "ALL_REGS" } |
| 1462 | |
|
19
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
1463 /* Define which registers fit in which classes. This is an initializer |
|
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
1464 for a vector of HARD_REG_SET of length N_REG_CLASSES. |
|
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
1465 |
| 111 | 1466 Note that CLOBBERED_REGS are calculated by |
| 1467 TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
| 1468 | |
| 131 | 1469 #define REG_CLASS_CONTENTS \ |
| 1470 { { 0x0, 0x0, 0x0 }, /* NO_REGS */ \ | |
| 1471 { 0x01, 0x0, 0x0 }, /* AREG */ \ | |
| 1472 { 0x02, 0x0, 0x0 }, /* DREG */ \ | |
| 1473 { 0x04, 0x0, 0x0 }, /* CREG */ \ | |
| 1474 { 0x08, 0x0, 0x0 }, /* BREG */ \ | |
| 1475 { 0x10, 0x0, 0x0 }, /* SIREG */ \ | |
| 1476 { 0x20, 0x0, 0x0 }, /* DIREG */ \ | |
| 1477 { 0x03, 0x0, 0x0 }, /* AD_REGS */ \ | |
| 1478 { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \ | |
| 1479 { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \ | |
| 1480 { 0x900f0, 0x0, 0x0 }, /* NON_Q_REGS */ \ | |
| 1481 { 0x7e, 0xff0, 0x0 }, /* TLS_GOTBASE_REGS */ \ | |
| 1482 { 0x7f, 0xff0, 0x0 }, /* INDEX_REGS */ \ | |
| 1483 { 0x900ff, 0x0, 0x0 }, /* LEGACY_REGS */ \ | |
| 1484 { 0x900ff, 0xff0, 0x0 }, /* GENERAL_REGS */ \ | |
| 1485 { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \ | |
| 1486 { 0x200, 0x0, 0x0 }, /* FP_SECOND_REG */ \ | |
| 1487 { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \ | |
| 1488 { 0x100000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \ | |
| 1489 { 0xff00000, 0x0, 0x0 }, /* NO_REX_SSE_REGS */ \ | |
| 1490 { 0xff00000, 0xff000, 0x0 }, /* SSE_REGS */ \ | |
| 1491 { 0xff00000, 0xfffff000, 0xf }, /* ALL_SSE_REGS */ \ | |
| 1492 { 0xf0000000, 0xf, 0x0 }, /* MMX_REGS */ \ | |
| 1493 { 0xff0ff00, 0xfffff000, 0xf }, /* FLOAT_SSE_REGS */ \ | |
| 1494 { 0x9ffff, 0xff0, 0x0 }, /* FLOAT_INT_REGS */ \ | |
| 1495 { 0xff900ff, 0xfffffff0, 0xf }, /* INT_SSE_REGS */ \ | |
| 1496 { 0xff9ffff, 0xfffffff0, 0xf }, /* FLOAT_INT_SSE_REGS */ \ | |
| 1497 { 0x0, 0x0, 0xfe0 }, /* MASK_REGS */ \ | |
| 1498 { 0x0, 0x0, 0xff0 }, /* ALL_MASK_REGS */ \ | |
| 1499 { 0xffffffff, 0xffffffff, 0xfff } /* ALL_REGS */ \ | |
| 0 | 1500 } |
| 1501 | |
| 1502 /* The same information, inverted: | |
| 1503 Return the class number of the smallest class containing | |
| 1504 reg number REGNO. This could be a conditional expression | |
| 1505 or could index an array. */ | |
| 1506 | |
| 111 | 1507 #define REGNO_REG_CLASS(REGNO) (regclass_map[(REGNO)]) |
| 0 | 1508 |
|
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1509 /* When this hook returns true for MODE, the compiler allows |
|
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1510 registers explicitly used in the rtl to be used as spill registers |
|
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1511 but prevents the compiler from extending the lifetime of these |
|
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1512 registers. */ |
|
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1513 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true |
| 0 | 1514 |
| 111 | 1515 #define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X))) |
| 1516 #define QI_REGNO_P(N) IN_RANGE ((N), FIRST_QI_REG, LAST_QI_REG) | |
| 1517 | |
| 1518 #define LEGACY_INT_REG_P(X) (REG_P (X) && LEGACY_INT_REGNO_P (REGNO (X))) | |
| 1519 #define LEGACY_INT_REGNO_P(N) (IN_RANGE ((N), FIRST_INT_REG, LAST_INT_REG)) | |
| 1520 | |
| 1521 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) | |
| 0 | 1522 #define REX_INT_REGNO_P(N) \ |
| 1523 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) | |
| 111 | 1524 |
| 1525 #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) | |
| 1526 #define GENERAL_REGNO_P(N) \ | |
| 1527 (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N)) | |
| 1528 | |
| 1529 #define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X))) | |
| 1530 #define ANY_QI_REGNO_P(N) \ | |
| 1531 (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N)) | |
| 1532 | |
| 1533 #define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X))) | |
| 1534 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) | |
| 1535 | |
| 1536 #define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X))) | |
| 0 | 1537 #define SSE_REGNO_P(N) \ |
| 1538 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ | |
| 111 | 1539 || REX_SSE_REGNO_P (N) \ |
| 1540 || EXT_REX_SSE_REGNO_P (N)) | |
| 0 | 1541 |
| 1542 #define REX_SSE_REGNO_P(N) \ | |
| 1543 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) | |
| 1544 | |
| 111 | 1545 #define EXT_REX_SSE_REG_P(X) (REG_P (X) && EXT_REX_SSE_REGNO_P (REGNO (X))) |
| 1546 | |
| 1547 #define EXT_REX_SSE_REGNO_P(N) \ | |
| 1548 IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG) | |
| 1549 | |
| 1550 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) | |
| 1551 #define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N)) | |
| 1552 | |
| 1553 #define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X))) | |
| 1554 #define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG) | |
| 145 | 1555 #define MASK_PAIR_REGNO_P(N) ((((N) - FIRST_MASK_REG) & 1) == 0) |
| 111 | 1556 |
| 1557 #define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X))) | |
| 0 | 1558 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) |
| 1559 | |
| 1560 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) | |
| 131 | 1561 #define CC_REGNO_P(X) ((X) == FLAGS_REG) |
| 111 | 1562 |
| 1563 #define MOD4_SSE_REG_P(X) (REG_P (X) && MOD4_SSE_REGNO_P (REGNO (X))) | |
| 1564 #define MOD4_SSE_REGNO_P(N) ((N) == XMM0_REG \ | |
| 1565 || (N) == XMM4_REG \ | |
| 1566 || (N) == XMM8_REG \ | |
| 1567 || (N) == XMM12_REG \ | |
| 1568 || (N) == XMM16_REG \ | |
| 1569 || (N) == XMM20_REG \ | |
| 1570 || (N) == XMM24_REG \ | |
| 1571 || (N) == XMM28_REG) | |
| 1572 | |
| 1573 /* First floating point reg */ | |
| 1574 #define FIRST_FLOAT_REG FIRST_STACK_REG | |
| 1575 #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG) | |
| 1576 | |
| 131 | 1577 #define GET_SSE_REGNO(N) \ |
| 1578 ((N) < 8 ? FIRST_SSE_REG + (N) \ | |
| 1579 : (N) < 16 ? FIRST_REX_SSE_REG + (N) - 8 \ | |
| 1580 : FIRST_EXT_REX_SSE_REG + (N) - 16) | |
| 111 | 1581 |
| 0 | 1582 /* The class value for index registers, and the one for base regs. */ |
| 1583 | |
| 1584 #define INDEX_REG_CLASS INDEX_REGS | |
| 1585 #define BASE_REG_CLASS GENERAL_REGS | |
| 1586 | |
| 1587 /* Stack layout; function entry, exit and calling. */ | |
| 1588 | |
| 1589 /* Define this if pushing a word on the stack | |
| 1590 makes the stack pointer a smaller address. */ | |
| 111 | 1591 #define STACK_GROWS_DOWNWARD 1 |
| 0 | 1592 |
| 1593 /* Define this to nonzero if the nominal address of the stack frame | |
| 1594 is at the high-address end of the local variables; | |
| 1595 that is, each additional local variable allocated | |
| 1596 goes at a more negative offset in the frame. */ | |
| 1597 #define FRAME_GROWS_DOWNWARD 1 | |
| 1598 | |
| 131 | 1599 #define PUSH_ROUNDING(BYTES) ix86_push_rounding (BYTES) |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1600 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1601 /* If defined, the maximum amount of space required for outgoing arguments |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1602 will be computed and placed into the variable `crtl->outgoing_args_size'. |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1603 No space will be pushed onto the stack for each call; instead, the |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1604 function prologue should increase the stack frame size by this amount. |
| 111 | 1605 |
| 1606 In 32bit mode enabling argument accumulation results in about 5% code size | |
| 1607 growth because move instructions are less compact than push. In 64bit | |
| 1608 mode the difference is less drastic but visible. | |
| 1609 | |
| 1610 FIXME: Unlike earlier implementations, the size of unwind info seems to | |
| 1611 actually grow with accumulation. Is that because accumulated args | |
| 1612 unwind info became unnecesarily bloated? | |
| 1613 | |
| 1614 With the 64-bit MS ABI, we can generate correct code with or without | |
| 1615 accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code | |
| 1616 generated without accumulated args is terrible. | |
| 1617 | |
| 1618 If stack probes are required, the space used for large function | |
| 1619 arguments on the stack must also be probed, so enable | |
| 1620 -maccumulate-outgoing-args so this happens in the prologue. | |
| 1621 | |
| 1622 We must use argument accumulation in interrupt function if stack | |
| 1623 may be realigned to avoid DRAP. */ | |
| 0 | 1624 |
| 1625 #define ACCUMULATE_OUTGOING_ARGS \ | |
| 111 | 1626 ((TARGET_ACCUMULATE_OUTGOING_ARGS \ |
| 1627 && optimize_function_for_speed_p (cfun)) \ | |
| 1628 || (cfun->machine->func_type != TYPE_NORMAL \ | |
| 1629 && crtl->stack_realign_needed) \ | |
| 1630 || TARGET_STACK_PROBE \ | |
| 1631 || TARGET_64BIT_MS_ABI \ | |
| 1632 || (TARGET_MACHO && crtl->profile)) | |
| 0 | 1633 |
| 1634 /* If defined, a C expression whose value is nonzero when we want to use PUSH | |
| 1635 instructions to pass outgoing arguments. */ | |
| 1636 | |
| 1637 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) | |
| 1638 | |
| 1639 /* We want the stack and args grow in opposite directions, even if | |
| 1640 PUSH_ARGS is 0. */ | |
| 1641 #define PUSH_ARGS_REVERSED 1 | |
| 1642 | |
| 1643 /* Offset of first parameter from the argument pointer register value. */ | |
| 1644 #define FIRST_PARM_OFFSET(FNDECL) 0 | |
| 1645 | |
| 1646 /* Define this macro if functions should assume that stack space has been | |
| 1647 allocated for arguments even when their values are passed in registers. | |
| 1648 | |
| 1649 The value of this macro is the size, in bytes, of the area reserved for | |
| 1650 arguments passed in registers for the function represented by FNDECL. | |
| 1651 | |
| 1652 This space can be allocated by the caller, or be a part of the | |
| 1653 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says | |
| 1654 which. */ | |
| 1655 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) | |
| 1656 | |
| 1657 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ | |
| 111 | 1658 (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI) |
| 0 | 1659 |
| 1660 /* Define how to find the value returned by a library function | |
| 1661 assuming the value has mode MODE. */ | |
| 1662 | |
| 1663 #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) | |
| 1664 | |
| 1665 /* Define the size of the result block used for communication between | |
| 1666 untyped_call and untyped_return. The block contains a DImode value | |
| 1667 followed by the block used by fnsave and frstor. */ | |
| 1668 | |
| 1669 #define APPLY_RESULT_SIZE (8+108) | |
| 1670 | |
| 1671 /* 1 if N is a possible register number for function argument passing. */ | |
| 1672 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) | |
| 1673 | |
| 1674 /* Define a data type for recording info about an argument list | |
| 1675 during the scan of that argument list. This data type should | |
| 1676 hold all necessary information about the function itself | |
| 1677 and about the args processed so far, enough to enable macros | |
| 1678 such as FUNCTION_ARG to determine where the next arg should go. */ | |
| 1679 | |
| 1680 typedef struct ix86_args { | |
| 1681 int words; /* # words passed so far */ | |
| 1682 int nregs; /* # registers available for passing */ | |
| 1683 int regno; /* next available register number */ | |
|
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1684 int fastcall; /* fastcall or thiscall calling convention |
|
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1685 is used */ |
| 0 | 1686 int sse_words; /* # sse words passed so far */ |
| 1687 int sse_nregs; /* # sse registers available for passing */ | |
| 111 | 1688 int warn_avx512f; /* True when we want to warn |
| 1689 about AVX512F ABI. */ | |
| 0 | 1690 int warn_avx; /* True when we want to warn about AVX ABI. */ |
| 1691 int warn_sse; /* True when we want to warn about SSE ABI. */ | |
| 1692 int warn_mmx; /* True when we want to warn about MMX ABI. */ | |
| 131 | 1693 int warn_empty; /* True when we want to warn about empty classes |
| 1694 passing ABI change. */ | |
| 0 | 1695 int sse_regno; /* next available sse register number */ |
| 1696 int mmx_words; /* # mmx words passed so far */ | |
| 1697 int mmx_nregs; /* # mmx registers available for passing */ | |
| 1698 int mmx_regno; /* next available mmx register number */ | |
| 1699 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1700 int caller; /* true if it is caller. */ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1701 int float_in_sse; /* Set to 1 or 2 for 32bit targets if |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1702 SFmode/DFmode arguments should be passed |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1703 in SSE registers. Otherwise 0. */ |
| 111 | 1704 int stdarg; /* Set to 1 if function is stdarg. */ |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1705 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise |
| 0 | 1706 MS_ABI for ms abi. */ |
| 111 | 1707 tree decl; /* Callee decl. */ |
| 0 | 1708 } CUMULATIVE_ARGS; |
| 1709 | |
| 1710 /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
| 1711 for a call to a function whose data type is FNTYPE. | |
| 1712 For a library call, FNTYPE is 0. */ | |
| 1713 | |
| 1714 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1715 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1716 (N_NAMED_ARGS) != -1) |
| 0 | 1717 |
| 1718 /* Output assembler code to FILE to increment profiler label # LABELNO | |
| 1719 for profiling a function entry. */ | |
| 1720 | |
| 111 | 1721 #define FUNCTION_PROFILER(FILE, LABELNO) \ |
| 1722 x86_function_profiler ((FILE), (LABELNO)) | |
| 0 | 1723 |
| 1724 #define MCOUNT_NAME "_mcount" | |
| 1725 | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1726 #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1727 |
| 0 | 1728 #define PROFILE_COUNT_REGISTER "edx" |
| 1729 | |
| 1730 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
| 1731 the stack pointer does not matter. The value is tested only in | |
| 1732 functions that have frame pointers. | |
| 1733 No definition is equivalent to always zero. */ | |
| 1734 /* Note on the 386 it might be more efficient not to define this since | |
| 1735 we have to restore it ourselves from the frame pointer, in order to | |
| 1736 use pop */ | |
| 1737 | |
| 1738 #define EXIT_IGNORE_STACK 1 | |
| 1739 | |
| 111 | 1740 /* Define this macro as a C expression that is nonzero for registers |
| 1741 used by the epilogue or the `return' pattern. */ | |
| 1742 | |
| 1743 #define EPILOGUE_USES(REGNO) ix86_epilogue_uses (REGNO) | |
| 1744 | |
| 0 | 1745 /* Output assembler code for a block containing the constant parts |
| 1746 of a trampoline, leaving space for the variable parts. */ | |
| 1747 | |
| 1748 /* On the 386, the trampoline contains two instructions: | |
| 1749 mov #STATIC,ecx | |
| 1750 jmp FUNCTION | |
| 1751 The trampoline is generated entirely at runtime. The operand of JMP | |
| 1752 is the address of FUNCTION relative to the instruction following the | |
| 1753 JMP (which is 5 bytes long). */ | |
| 1754 | |
| 1755 /* Length in units of the trampoline for entering a nested function. */ | |
| 1756 | |
| 131 | 1757 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 28 : 14) |
| 0 | 1758 |
| 1759 /* Definitions for register eliminations. | |
| 1760 | |
| 1761 This is an array of structures. Each structure initializes one pair | |
| 1762 of eliminable registers. The "from" register number is given first, | |
| 1763 followed by "to". Eliminations of the same "from" register are listed | |
| 1764 in order of preference. | |
| 1765 | |
| 1766 There are two registers that can always be eliminated on the i386. | |
| 1767 The frame pointer and the arg pointer can be replaced by either the | |
| 1768 hard frame pointer or to the stack pointer, depending upon the | |
| 1769 circumstances. The hard frame pointer is not used before reload and | |
| 1770 so it is not eligible for elimination. */ | |
| 1771 | |
| 1772 #define ELIMINABLE_REGS \ | |
| 1773 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 1774 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
| 1775 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 1776 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ | |
| 1777 | |
| 1778 /* Define the offset between two registers, one to be eliminated, and the other | |
| 1779 its replacement, at the start of a routine. */ | |
| 1780 | |
| 1781 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
| 1782 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) | |
| 1783 | |
| 1784 /* Addressing modes, and classification of registers for them. */ | |
| 1785 | |
| 1786 /* Macros to check register numbers against specific register classes. */ | |
| 1787 | |
| 1788 /* These assume that REGNO is a hard or pseudo reg number. | |
| 1789 They give nonzero only if REGNO is a hard reg of the suitable class | |
| 1790 or a pseudo reg currently allocated to a suitable hard reg. | |
| 1791 Since they use reg_renumber, they are safe only once reg_renumber | |
| 111 | 1792 has been allocated, which happens in reginfo.c during register |
| 1793 allocation. */ | |
| 0 | 1794 |
| 1795 #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
| 1796 ((REGNO) < STACK_POINTER_REGNUM \ | |
| 1797 || REX_INT_REGNO_P (REGNO) \ | |
| 1798 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ | |
| 1799 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) | |
| 1800 | |
| 1801 #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
| 1802 (GENERAL_REGNO_P (REGNO) \ | |
| 1803 || (REGNO) == ARG_POINTER_REGNUM \ | |
| 1804 || (REGNO) == FRAME_POINTER_REGNUM \ | |
| 1805 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) | |
| 1806 | |
| 1807 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
| 1808 and check its validity for a certain class. | |
| 1809 We have two alternate definitions for each of them. | |
| 1810 The usual definition accepts all pseudo regs; the other rejects | |
| 1811 them unless they have been allocated suitable hard regs. | |
| 1812 The symbol REG_OK_STRICT causes the latter definition to be used. | |
| 1813 | |
| 1814 Most source files want to accept pseudo regs in the hope that | |
| 1815 they will get allocated to the class that the insn wants them to be in. | |
| 1816 Source files for reload pass need to be strict. | |
| 1817 After reload, it makes no difference, since pseudo regs have | |
| 1818 been eliminated by then. */ | |
| 1819 | |
| 1820 | |
| 1821 /* Non strict versions, pseudos are ok. */ | |
| 1822 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ | |
| 1823 (REGNO (X) < STACK_POINTER_REGNUM \ | |
| 1824 || REX_INT_REGNO_P (REGNO (X)) \ | |
| 1825 || REGNO (X) >= FIRST_PSEUDO_REGISTER) | |
| 1826 | |
| 1827 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ | |
| 1828 (GENERAL_REGNO_P (REGNO (X)) \ | |
| 1829 || REGNO (X) == ARG_POINTER_REGNUM \ | |
| 1830 || REGNO (X) == FRAME_POINTER_REGNUM \ | |
| 1831 || REGNO (X) >= FIRST_PSEUDO_REGISTER) | |
| 1832 | |
| 1833 /* Strict versions, hard registers only */ | |
| 1834 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
| 1835 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
| 1836 | |
| 1837 #ifndef REG_OK_STRICT | |
| 1838 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) | |
| 1839 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) | |
| 1840 | |
| 1841 #else | |
| 1842 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) | |
| 1843 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) | |
| 1844 #endif | |
| 1845 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1846 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression |
| 0 | 1847 that is a valid memory address for an instruction. |
| 1848 The MODE argument is the machine mode for the MEM expression | |
| 1849 that wants to use this address. | |
| 1850 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1851 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P, |
| 0 | 1852 except for CONSTANT_ADDRESS_P which is usually machine-independent. |
| 1853 | |
| 1854 See legitimize_pic_address in i386.c for details as to what | |
| 1855 constitutes a legitimate address when -fpic is used. */ | |
| 1856 | |
| 1857 #define MAX_REGS_PER_ADDRESS 2 | |
| 1858 | |
| 1859 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) | |
| 1860 | |
| 1861 /* If defined, a C expression to determine the base term of address X. | |
| 1862 This macro is used in only one place: `find_base_term' in alias.c. | |
| 1863 | |
| 1864 It is always safe for this macro to not be defined. It exists so | |
| 1865 that alias analysis can understand machine-dependent addresses. | |
| 1866 | |
| 1867 The typical use of this macro is to handle addresses containing | |
| 1868 a label_ref or symbol_ref within an UNSPEC. */ | |
| 1869 | |
| 1870 #define FIND_BASE_TERM(X) ix86_find_base_term (X) | |
| 1871 | |
| 1872 /* Nonzero if the constant value X is a legitimate general operand | |
| 1873 when generating PIC code. It is given that flag_pic is on and | |
| 1874 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
| 1875 | |
| 1876 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) | |
| 1877 | |
| 1878 #define SYMBOLIC_CONST(X) \ | |
| 1879 (GET_CODE (X) == SYMBOL_REF \ | |
| 1880 || GET_CODE (X) == LABEL_REF \ | |
| 1881 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
| 1882 | |
| 1883 /* Max number of args passed in registers. If this is more than 3, we will | |
| 1884 have problems with ebx (register #4), since it is a caller save register and | |
| 1885 is also used as the pic register in ELF. So for now, don't allow more than | |
| 1886 3 registers to be passed in registers. */ | |
| 1887 | |
| 1888 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ | |
| 1889 #define X86_64_REGPARM_MAX 6 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1890 #define X86_64_MS_REGPARM_MAX 4 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1891 |
| 0 | 1892 #define X86_32_REGPARM_MAX 3 |
| 1893 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1894 #define REGPARM_MAX \ |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1895 (TARGET_64BIT \ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1896 ? (TARGET_64BIT_MS_ABI \ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1897 ? X86_64_MS_REGPARM_MAX \ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1898 : X86_64_REGPARM_MAX) \ |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1899 : X86_32_REGPARM_MAX) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1900 |
| 0 | 1901 #define X86_64_SSE_REGPARM_MAX 8 |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1902 #define X86_64_MS_SSE_REGPARM_MAX 4 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1903 |
|
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1904 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0) |
| 0 | 1905 |
| 1906 #define SSE_REGPARM_MAX \ | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1907 (TARGET_64BIT \ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1908 ? (TARGET_64BIT_MS_ABI \ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1909 ? X86_64_MS_SSE_REGPARM_MAX \ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1910 : X86_64_SSE_REGPARM_MAX) \ |
| 0 | 1911 : X86_32_SSE_REGPARM_MAX) |
| 1912 | |
| 1913 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) | |
| 1914 | |
| 1915 /* Specify the machine mode that this machine uses | |
| 1916 for the index in the tablejump instruction. */ | |
| 1917 #define CASE_VECTOR_MODE \ | |
| 111 | 1918 (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) |
| 0 | 1919 |
| 1920 /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
| 1921 #define DEFAULT_SIGNED_CHAR 1 | |
| 1922 | |
| 1923 /* Max number of bytes we can move from memory to memory | |
| 1924 in one reasonably fast instruction. */ | |
| 1925 #define MOVE_MAX 16 | |
| 1926 | |
| 1927 /* MOVE_MAX_PIECES is the number of bytes at a time which we can | |
| 1928 move efficiently, as opposed to MOVE_MAX which is the maximum | |
| 111 | 1929 number of bytes we can move with a single instruction. |
| 1930 | |
| 1931 ??? We should use TImode in 32-bit mode and use OImode or XImode | |
| 1932 if they are available. But since by_pieces_ninsns determines the | |
| 1933 widest mode with MAX_FIXED_MODE_SIZE, we can only use TImode in | |
| 1934 64-bit mode. */ | |
| 1935 #define MOVE_MAX_PIECES \ | |
| 1936 ((TARGET_64BIT \ | |
| 1937 && TARGET_SSE2 \ | |
| 1938 && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ | |
| 1939 && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \ | |
| 1940 ? GET_MODE_SIZE (TImode) : UNITS_PER_WORD) | |
| 0 | 1941 |
| 1942 /* If a memory-to-memory move would take MOVE_RATIO or more simple | |
| 145 | 1943 move-instruction pairs, we will do a cpymem or libcall instead. |
| 0 | 1944 Increasing the value will always make code faster, but eventually |
| 1945 incurs high cost in increased code size. | |
| 1946 | |
| 1947 If you don't define this, a reasonable default is used. */ | |
| 1948 | |
| 1949 #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) | |
| 1950 | |
| 1951 /* If a clear memory operation would take CLEAR_RATIO or more simple | |
| 1952 move-instruction sequences, we will do a clrmem or libcall instead. */ | |
| 1953 | |
| 145 | 1954 #define CLEAR_RATIO(speed) ((speed) ? ix86_cost->clear_ratio : 2) |
| 0 | 1955 |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1956 /* Define if shifts truncate the shift count which implies one can |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1957 omit a sign-extension or zero-extension of a shift count. |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1958 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1959 On i386, shifts do truncate the count. But bit test instructions |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1960 take the modulo of the bit offset operand. */ |
| 0 | 1961 |
| 1962 /* #define SHIFT_COUNT_TRUNCATED */ | |
| 1963 | |
| 1964 /* A macro to update M and UNSIGNEDP when an object whose type is | |
| 1965 TYPE and which has the specified mode and signedness is to be | |
| 1966 stored in a register. This macro is only called when TYPE is a | |
| 1967 scalar type. | |
| 1968 | |
| 1969 On i386 it is sometimes useful to promote HImode and QImode | |
| 1970 quantities to SImode. The choice depends on target type. */ | |
| 1971 | |
| 1972 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
| 1973 do { \ | |
| 1974 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ | |
| 1975 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ | |
| 1976 (MODE) = SImode; \ | |
| 1977 } while (0) | |
| 1978 | |
| 1979 /* Specify the machine mode that pointers have. | |
| 1980 After generation of rtl, the compiler makes no further distinction | |
| 1981 between pointers and any other objects of this machine mode. */ | |
| 111 | 1982 #define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode) |
| 1983 | |
| 131 | 1984 /* Supply a definition of STACK_SAVEAREA_MODE for emit_stack_save. |
| 1985 NONLOCAL needs space to save both shadow stack and stack pointers. | |
| 1986 | |
| 1987 FIXME: We only need to save and restore stack pointer in ptr_mode. | |
| 1988 But expand_builtin_setjmp_setup and expand_builtin_longjmp use Pmode | |
| 1989 to save and restore stack pointer. See | |
| 1990 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84150 | |
| 1991 */ | |
| 1992 #define STACK_SAVEAREA_MODE(LEVEL) \ | |
| 1993 ((LEVEL) == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode) | |
| 111 | 1994 |
| 145 | 1995 /* Specify the machine_mode of the size increment |
| 1996 operand of an 'allocate_stack' named pattern. */ | |
| 1997 #define STACK_SIZE_MODE Pmode | |
| 1998 | |
| 111 | 1999 /* A C expression whose value is zero if pointers that need to be extended |
| 2000 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and | |
| 2001 greater then zero if they are zero-extended and less then zero if the | |
| 2002 ptr_extend instruction should be used. */ | |
| 2003 | |
| 2004 #define POINTERS_EXTEND_UNSIGNED 1 | |
| 0 | 2005 |
| 2006 /* A function address in a call instruction | |
| 2007 is a byte address (for indexing purposes) | |
| 2008 so give the MEM rtx a byte's mode. */ | |
| 2009 #define FUNCTION_MODE QImode | |
| 2010 | |
| 2011 | |
| 2012 /* A C expression for the cost of a branch instruction. A value of 1 | |
| 2013 is the default; other values are interpreted relative to that. */ | |
| 2014 | |
| 2015 #define BRANCH_COST(speed_p, predictable_p) \ | |
| 2016 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) | |
| 2017 | |
| 111 | 2018 /* An integer expression for the size in bits of the largest integer machine |
| 2019 mode that should actually be used. We allow pairs of registers. */ | |
| 2020 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) | |
| 2021 | |
| 0 | 2022 /* Define this macro as a C expression which is nonzero if accessing |
| 2023 less than a word of memory (i.e. a `char' or a `short') is no | |
| 2024 faster than accessing a word of memory, i.e., if such access | |
| 2025 require more than one instruction or if there is no difference in | |
| 2026 cost between byte and (aligned) word loads. | |
| 2027 | |
| 2028 When this macro is not defined, the compiler will access a field by | |
| 2029 finding the smallest containing object; when it is defined, a | |
| 2030 fullword load will be used if alignment permits. Unless bytes | |
| 2031 accesses are faster than word accesses, using word accesses is | |
| 2032 preferable since it may eliminate subsequent memory access if | |
| 2033 subsequent accesses occur to other fields in the same word of the | |
| 2034 structure, but to different bytes. */ | |
| 2035 | |
| 2036 #define SLOW_BYTE_ACCESS 0 | |
| 2037 | |
| 2038 /* Nonzero if access to memory by shorts is slow and undesirable. */ | |
| 2039 #define SLOW_SHORT_ACCESS 0 | |
| 2040 | |
| 2041 /* Define this macro if it is as good or better to call a constant | |
| 2042 function address than to call an address kept in a register. | |
| 2043 | |
| 2044 Desirable on the 386 because a CALL with a constant address is | |
| 2045 faster than one with a register address. */ | |
| 2046 | |
| 111 | 2047 #define NO_FUNCTION_CSE 1 |
| 0 | 2048 |
| 2049 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
| 2050 return the mode to be used for the comparison. | |
| 2051 | |
| 2052 For floating-point equality comparisons, CCFPEQmode should be used. | |
| 2053 VOIDmode should be used in all other cases. | |
| 2054 | |
| 2055 For integer comparisons against zero, reduce to CCNOmode or CCZmode if | |
| 2056 possible, to allow for more combinations. */ | |
| 2057 | |
| 2058 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) | |
| 2059 | |
| 2060 /* Return nonzero if MODE implies a floating point inequality can be | |
| 2061 reversed. */ | |
| 2062 | |
| 2063 #define REVERSIBLE_CC_MODE(MODE) 1 | |
| 2064 | |
| 2065 /* A C expression whose value is reversed condition code of the CODE for | |
| 2066 comparison done in CC_MODE mode. */ | |
| 2067 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) | |
| 2068 | |
| 2069 | |
| 2070 /* Control the assembler format that we output, to the extent | |
| 2071 this does not vary between assemblers. */ | |
| 2072 | |
| 2073 /* How to refer to registers in assembler output. | |
| 2074 This sequence is indexed by compiler's hard-register-number (see above). */ | |
| 2075 | |
| 2076 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". | |
| 2077 For non floating point regs, the following are the HImode names. | |
| 2078 | |
| 2079 For float regs, the stack top is sometimes referred to as "%st(0)" | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2080 instead of just "%st". TARGET_PRINT_OPERAND handles this with the |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2081 "y" code. */ |
| 0 | 2082 |
| 2083 #define HI_REGISTER_NAMES \ | |
| 2084 {"ax","dx","cx","bx","si","di","bp","sp", \ | |
| 2085 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ | |
| 131 | 2086 "argp", "flags", "fpsr", "frame", \ |
| 0 | 2087 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ |
| 2088 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ | |
| 2089 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
| 111 | 2090 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \ |
| 2091 "xmm16", "xmm17", "xmm18", "xmm19", \ | |
| 2092 "xmm20", "xmm21", "xmm22", "xmm23", \ | |
| 2093 "xmm24", "xmm25", "xmm26", "xmm27", \ | |
| 2094 "xmm28", "xmm29", "xmm30", "xmm31", \ | |
| 131 | 2095 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" } |
| 0 | 2096 |
| 2097 #define REGISTER_NAMES HI_REGISTER_NAMES | |
| 2098 | |
| 145 | 2099 #define QI_REGISTER_NAMES \ |
| 2100 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl"} | |
| 2101 | |
| 2102 #define QI_HIGH_REGISTER_NAMES \ | |
| 2103 {"ah", "dh", "ch", "bh"} | |
| 2104 | |
| 0 | 2105 /* Table of additional register names to use in user input. */ |
| 2106 | |
| 131 | 2107 #define ADDITIONAL_REGISTER_NAMES \ |
| 2108 { \ | |
| 2109 { "eax", AX_REG }, { "edx", DX_REG }, { "ecx", CX_REG }, { "ebx", BX_REG }, \ | |
| 2110 { "esi", SI_REG }, { "edi", DI_REG }, { "ebp", BP_REG }, { "esp", SP_REG }, \ | |
| 2111 { "rax", AX_REG }, { "rdx", DX_REG }, { "rcx", CX_REG }, { "rbx", BX_REG }, \ | |
| 2112 { "rsi", SI_REG }, { "rdi", DI_REG }, { "rbp", BP_REG }, { "rsp", SP_REG }, \ | |
| 2113 { "al", AX_REG }, { "dl", DX_REG }, { "cl", CX_REG }, { "bl", BX_REG }, \ | |
| 145 | 2114 { "sil", SI_REG }, { "dil", DI_REG }, { "bpl", BP_REG }, { "spl", SP_REG }, \ |
| 131 | 2115 { "ah", AX_REG }, { "dh", DX_REG }, { "ch", CX_REG }, { "bh", BX_REG }, \ |
| 2116 { "ymm0", XMM0_REG }, { "ymm1", XMM1_REG }, { "ymm2", XMM2_REG }, { "ymm3", XMM3_REG }, \ | |
| 2117 { "ymm4", XMM4_REG }, { "ymm5", XMM5_REG }, { "ymm6", XMM6_REG }, { "ymm7", XMM7_REG }, \ | |
| 2118 { "ymm8", XMM8_REG }, { "ymm9", XMM9_REG }, { "ymm10", XMM10_REG }, { "ymm11", XMM11_REG }, \ | |
| 2119 { "ymm12", XMM12_REG }, { "ymm13", XMM13_REG }, { "ymm14", XMM14_REG }, { "ymm15", XMM15_REG }, \ | |
| 2120 { "ymm16", XMM16_REG }, { "ymm17", XMM17_REG }, { "ymm18", XMM18_REG }, { "ymm19", XMM19_REG }, \ | |
| 2121 { "ymm20", XMM20_REG }, { "ymm21", XMM21_REG }, { "ymm22", XMM22_REG }, { "ymm23", XMM23_REG }, \ | |
| 2122 { "ymm24", XMM24_REG }, { "ymm25", XMM25_REG }, { "ymm26", XMM26_REG }, { "ymm27", XMM27_REG }, \ | |
| 2123 { "ymm28", XMM28_REG }, { "ymm29", XMM29_REG }, { "ymm30", XMM30_REG }, { "ymm31", XMM31_REG }, \ | |
| 2124 { "zmm0", XMM0_REG }, { "zmm1", XMM1_REG }, { "zmm2", XMM2_REG }, { "zmm3", XMM3_REG }, \ | |
| 2125 { "zmm4", XMM4_REG }, { "zmm5", XMM5_REG }, { "zmm6", XMM6_REG }, { "zmm7", XMM7_REG }, \ | |
| 2126 { "zmm8", XMM8_REG }, { "zmm9", XMM9_REG }, { "zmm10", XMM10_REG }, { "zmm11", XMM11_REG }, \ | |
| 2127 { "zmm12", XMM12_REG }, { "zmm13", XMM13_REG }, { "zmm14", XMM14_REG }, { "zmm15", XMM15_REG }, \ | |
| 2128 { "zmm16", XMM16_REG }, { "zmm17", XMM17_REG }, { "zmm18", XMM18_REG }, { "zmm19", XMM19_REG }, \ | |
| 2129 { "zmm20", XMM20_REG }, { "zmm21", XMM21_REG }, { "zmm22", XMM22_REG }, { "zmm23", XMM23_REG }, \ | |
| 2130 { "zmm24", XMM24_REG }, { "zmm25", XMM25_REG }, { "zmm26", XMM26_REG }, { "zmm27", XMM27_REG }, \ | |
| 2131 { "zmm28", XMM28_REG }, { "zmm29", XMM29_REG }, { "zmm30", XMM30_REG }, { "zmm31", XMM31_REG } \ | |
| 2132 } | |
| 0 | 2133 |
| 2134 /* How to renumber registers for dbx and gdb. */ | |
| 2135 | |
| 2136 #define DBX_REGISTER_NUMBER(N) \ | |
| 2137 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) | |
| 2138 | |
| 2139 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
| 2140 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; | |
| 2141 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
| 2142 | |
| 2143 /* Before the prologue, RA is at 0(%esp). */ | |
| 2144 #define INCOMING_RETURN_ADDR_RTX \ | |
| 111 | 2145 gen_rtx_MEM (Pmode, stack_pointer_rtx) |
| 0 | 2146 |
| 2147 /* After the prologue, RA is at -4(AP) in the current frame. */ | |
| 111 | 2148 #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
| 2149 ((COUNT) == 0 \ | |
| 2150 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \ | |
| 2151 -UNITS_PER_WORD)) \ | |
| 2152 : gen_rtx_MEM (Pmode, plus_constant (Pmode, (FRAME), UNITS_PER_WORD))) | |
| 0 | 2153 |
| 2154 /* PC is dbx register 8; let's use that column for RA. */ | |
| 2155 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) | |
| 2156 | |
| 111 | 2157 /* Before the prologue, there are return address and error code for |
| 2158 exception handler on the top of the frame. */ | |
| 2159 #define INCOMING_FRAME_SP_OFFSET \ | |
| 2160 (cfun->machine->func_type == TYPE_EXCEPTION \ | |
| 2161 ? 2 * UNITS_PER_WORD : UNITS_PER_WORD) | |
| 0 | 2162 |
| 131 | 2163 /* The value of INCOMING_FRAME_SP_OFFSET the assembler assumes in |
| 2164 .cfi_startproc. */ | |
| 2165 #define DEFAULT_INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD | |
| 2166 | |
| 0 | 2167 /* Describe how we implement __builtin_eh_return. */ |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2168 #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2169 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG) |
| 0 | 2170 |
| 2171 | |
| 2172 /* Select a format to encode pointers in exception handling data. CODE | |
| 2173 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
| 2174 true if the symbol may be affected by dynamic relocations. | |
| 2175 | |
| 2176 ??? All x86 object file formats are capable of representing this. | |
| 2177 After all, the relocation needed is the same as for the call insn. | |
| 2178 Whether or not a particular assembler allows us to enter such, I | |
| 2179 guess we'll have to see. */ | |
| 2180 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
| 2181 asm_preferred_eh_data_format ((CODE), (GLOBAL)) | |
| 2182 | |
| 111 | 2183 /* These are a couple of extensions to the formats accepted |
| 2184 by asm_fprintf: | |
| 2185 %z prints out opcode suffix for word-mode instruction | |
| 2186 %r prints out word-mode name for reg_names[arg] */ | |
| 2187 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ | |
| 2188 case 'z': \ | |
| 2189 fputc (TARGET_64BIT ? 'q' : 'l', (FILE)); \ | |
| 2190 break; \ | |
| 2191 \ | |
| 2192 case 'r': \ | |
| 2193 { \ | |
| 2194 unsigned int regno = va_arg ((ARGS), int); \ | |
| 2195 if (LEGACY_INT_REGNO_P (regno)) \ | |
| 2196 fputc (TARGET_64BIT ? 'r' : 'e', (FILE)); \ | |
| 2197 fputs (reg_names[regno], (FILE)); \ | |
| 2198 break; \ | |
| 2199 } | |
| 2200 | |
| 2201 /* This is how to output an insn to push a register on the stack. */ | |
| 2202 | |
| 2203 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ | |
| 2204 asm_fprintf ((FILE), "\tpush%z\t%%%r\n", (REGNO)) | |
| 2205 | |
| 2206 /* This is how to output an insn to pop a register from the stack. */ | |
| 0 | 2207 |
| 2208 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ | |
| 111 | 2209 asm_fprintf ((FILE), "\tpop%z\t%%%r\n", (REGNO)) |
| 0 | 2210 |
| 2211 /* This is how to output an element of a case-vector that is absolute. */ | |
| 2212 | |
| 2213 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
| 2214 ix86_output_addr_vec_elt ((FILE), (VALUE)) | |
| 2215 | |
| 2216 /* This is how to output an element of a case-vector that is relative. */ | |
| 2217 | |
| 2218 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
| 2219 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) | |
| 2220 | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2221 /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */ |
| 0 | 2222 |
| 2223 #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ | |
| 2224 { \ | |
| 2225 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2226 (PTR) += TARGET_AVX ? 1 : 2; \ |
| 0 | 2227 } |
| 2228 | |
| 2229 /* A C statement or statements which output an assembler instruction | |
| 2230 opcode to the stdio stream STREAM. The macro-operand PTR is a | |
| 2231 variable of type `char *' which points to the opcode name in | |
| 2232 its "internal" form--the form that is written in the machine | |
| 2233 description. */ | |
| 2234 | |
| 2235 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ | |
| 2236 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) | |
| 2237 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2238 /* A C statement to output to the stdio stream FILE an assembler |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2239 command to pad the location counter to a multiple of 1<<LOG |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2240 bytes if it is within MAX_SKIP bytes. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2241 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2242 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2243 #undef ASM_OUTPUT_MAX_SKIP_PAD |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2244 #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2245 if ((LOG) != 0) \ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2246 { \ |
| 131 | 2247 if ((MAX_SKIP) == 0 || (MAX_SKIP) >= (1 << (LOG)) - 1) \ |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2248 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2249 else \ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2250 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2251 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2252 #endif |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2253 |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2254 /* Write the extra assembler code needed to declare a function |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2255 properly. */ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2256 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2257 #undef ASM_OUTPUT_FUNCTION_LABEL |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2258 #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ |
| 111 | 2259 ix86_asm_output_function_label ((FILE), (NAME), (DECL)) |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2260 |
| 145 | 2261 /* A C statement (sans semicolon) to output a reference to SYMBOL_REF SYM. |
| 2262 If not defined, assemble_name will be used to output the name of the | |
| 2263 symbol. This macro may be used to modify the way a symbol is referenced | |
| 2264 depending on information encoded by TARGET_ENCODE_SECTION_INFO. */ | |
| 2265 | |
| 2266 #ifndef ASM_OUTPUT_SYMBOL_REF | |
| 2267 #define ASM_OUTPUT_SYMBOL_REF(FILE, SYM) \ | |
| 2268 do { \ | |
| 2269 const char *name \ | |
| 2270 = assemble_name_resolve (XSTR (x, 0)); \ | |
| 2271 /* In -masm=att wrap identifiers that start with $ \ | |
| 2272 into parens. */ \ | |
| 2273 if (ASSEMBLER_DIALECT == ASM_ATT \ | |
| 2274 && name[0] == '$' \ | |
| 2275 && user_label_prefix[0] == '\0') \ | |
| 2276 { \ | |
| 2277 fputc ('(', (FILE)); \ | |
| 2278 assemble_name_raw ((FILE), name); \ | |
| 2279 fputc (')', (FILE)); \ | |
| 2280 } \ | |
| 2281 else \ | |
| 2282 assemble_name_raw ((FILE), name); \ | |
| 2283 } while (0) | |
| 2284 #endif | |
| 2285 | |
| 0 | 2286 /* Under some conditions we need jump tables in the text section, |
| 2287 because the assembler cannot handle label differences between | |
| 2288 sections. This is the case for x86_64 on Mach-O for example. */ | |
| 2289 | |
| 2290 #define JUMP_TABLES_IN_TEXT_SECTION \ | |
| 2291 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ | |
| 2292 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) | |
| 2293 | |
| 2294 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, | |
| 2295 and switch back. For x86 we do this only to save a few bytes that | |
| 2296 would otherwise be unused in the text section. */ | |
|
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2297 #define CRT_MKSTR2(VAL) #VAL |
|
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2298 #define CRT_MKSTR(x) CRT_MKSTR2(x) |
|
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2299 |
|
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2300 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ |
|
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2301 asm (SECTION_OP "\n\t" \ |
|
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2302 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \ |
| 0 | 2303 TEXT_SECTION_ASM_OP); |
| 111 | 2304 |
| 2305 /* Default threshold for putting data in large sections | |
| 2306 with x86-64 medium memory model */ | |
| 2307 #define DEFAULT_LARGE_SECTION_THRESHOLD 65536 | |
| 0 | 2308 |
| 111 | 2309 /* Which processor to tune code generation for. These must be in sync |
| 2310 with processor_target_table in i386.c. */ | |
| 0 | 2311 |
| 2312 enum processor_type | |
| 2313 { | |
| 111 | 2314 PROCESSOR_GENERIC = 0, |
| 2315 PROCESSOR_I386, /* 80386 */ | |
| 0 | 2316 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ |
| 2317 PROCESSOR_PENTIUM, | |
| 111 | 2318 PROCESSOR_LAKEMONT, |
| 0 | 2319 PROCESSOR_PENTIUMPRO, |
| 111 | 2320 PROCESSOR_PENTIUM4, |
| 2321 PROCESSOR_NOCONA, | |
| 2322 PROCESSOR_CORE2, | |
| 2323 PROCESSOR_NEHALEM, | |
| 2324 PROCESSOR_SANDYBRIDGE, | |
| 2325 PROCESSOR_HASWELL, | |
| 2326 PROCESSOR_BONNELL, | |
| 2327 PROCESSOR_SILVERMONT, | |
| 131 | 2328 PROCESSOR_GOLDMONT, |
| 2329 PROCESSOR_GOLDMONT_PLUS, | |
| 2330 PROCESSOR_TREMONT, | |
| 111 | 2331 PROCESSOR_KNL, |
| 2332 PROCESSOR_KNM, | |
| 131 | 2333 PROCESSOR_SKYLAKE, |
| 111 | 2334 PROCESSOR_SKYLAKE_AVX512, |
| 131 | 2335 PROCESSOR_CANNONLAKE, |
| 2336 PROCESSOR_ICELAKE_CLIENT, | |
| 2337 PROCESSOR_ICELAKE_SERVER, | |
| 145 | 2338 PROCESSOR_CASCADELAKE, |
| 2339 PROCESSOR_TIGERLAKE, | |
| 2340 PROCESSOR_COOPERLAKE, | |
| 111 | 2341 PROCESSOR_INTEL, |
| 0 | 2342 PROCESSOR_GEODE, |
| 2343 PROCESSOR_K6, | |
| 2344 PROCESSOR_ATHLON, | |
| 2345 PROCESSOR_K8, | |
| 2346 PROCESSOR_AMDFAM10, | |
|
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2347 PROCESSOR_BDVER1, |
| 111 | 2348 PROCESSOR_BDVER2, |
| 2349 PROCESSOR_BDVER3, | |
| 2350 PROCESSOR_BDVER4, | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2351 PROCESSOR_BTVER1, |
| 111 | 2352 PROCESSOR_BTVER2, |
| 2353 PROCESSOR_ZNVER1, | |
| 145 | 2354 PROCESSOR_ZNVER2, |
| 0 | 2355 PROCESSOR_max |
| 2356 }; | |
| 2357 | |
| 131 | 2358 #if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS) |
| 145 | 2359 extern const char *const processor_names[]; |
| 131 | 2360 |
| 2361 #include "wide-int-bitmask.h" | |
| 2362 | |
| 2363 const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0); | |
| 2364 const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1); | |
| 2365 const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2); | |
| 2366 const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3); | |
| 2367 const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4); | |
| 2368 const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5); | |
| 2369 const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6); | |
| 2370 const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7); | |
| 2371 const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8); | |
| 2372 const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9); | |
| 2373 const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10); | |
| 2374 const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11); | |
| 2375 const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12); | |
| 2376 const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13); | |
| 2377 const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14); | |
| 2378 const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15); | |
| 2379 const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16); | |
| 2380 const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17); | |
| 2381 const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18); | |
| 2382 const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19); | |
| 2383 const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20); | |
| 2384 const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21); | |
| 2385 const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22); | |
| 2386 const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23); | |
| 2387 const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24); | |
| 2388 const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25); | |
| 2389 const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26); | |
| 2390 const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27); | |
| 2391 const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28); | |
| 2392 const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29); | |
| 2393 const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30); | |
| 2394 const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31); | |
| 2395 const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32); | |
| 2396 const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33); | |
| 2397 const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34); | |
| 2398 const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35); | |
| 2399 const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36); | |
| 2400 const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37); | |
| 2401 const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38); | |
| 2402 const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39); | |
| 2403 const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40); | |
| 2404 const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41); | |
| 2405 const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42); | |
| 2406 const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43); | |
| 2407 /* Hole after PTA_MPX was removed. */ | |
| 2408 const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45); | |
| 2409 const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46); | |
| 2410 const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47); | |
| 2411 const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48); | |
| 2412 const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49); | |
| 2413 const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50); | |
| 2414 const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51); | |
| 2415 const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52); | |
| 2416 const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53); | |
| 2417 const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54); | |
| 2418 const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55); | |
| 2419 const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56); | |
| 2420 const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57); | |
| 2421 const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58); | |
| 2422 const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59); | |
| 2423 const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60); | |
| 2424 const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61); | |
| 2425 const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62); | |
| 2426 const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63); | |
| 2427 const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U); | |
| 2428 const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1); | |
| 2429 const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2); | |
| 2430 const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3); | |
| 2431 const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4); | |
| 2432 const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5); | |
| 2433 const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6); | |
| 2434 const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7); | |
| 2435 const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8); | |
| 145 | 2436 const wide_int_bitmask PTA_AVX512VP2INTERSECT (0, HOST_WIDE_INT_1U << 9); |
| 131 | 2437 const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9); |
| 145 | 2438 const wide_int_bitmask PTA_PTWRITE (0, HOST_WIDE_INT_1U << 10); |
| 2439 const wide_int_bitmask PTA_AVX512BF16 (0, HOST_WIDE_INT_1U << 11); | |
| 2440 const wide_int_bitmask PTA_MOVDIRI(0, HOST_WIDE_INT_1U << 13); | |
| 2441 const wide_int_bitmask PTA_MOVDIR64B(0, HOST_WIDE_INT_1U << 14); | |
| 131 | 2442 |
| 2443 const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | |
| 2444 | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR; | |
| 2445 const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | |
| 2446 | PTA_POPCNT; | |
| 145 | 2447 const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_PCLMUL; |
| 131 | 2448 const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE |
| 2449 | PTA_XSAVEOPT; | |
| 2450 const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE | |
| 2451 | PTA_RDRND | PTA_F16C; | |
| 2452 const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | |
| 2453 | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE; | |
| 2454 const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW | |
| 2455 | PTA_RDSEED; | |
| 145 | 2456 const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES | PTA_CLFLUSHOPT |
| 131 | 2457 | PTA_XSAVEC | PTA_XSAVES | PTA_SGX; |
| 2458 const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F | |
| 2459 | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU | |
| 2460 | PTA_CLWB; | |
| 145 | 2461 const wide_int_bitmask PTA_CASCADELAKE = PTA_SKYLAKE_AVX512 | PTA_AVX512VNNI; |
| 2462 const wide_int_bitmask PTA_COOPERLAKE = PTA_CASCADELAKE | PTA_AVX512BF16; | |
| 131 | 2463 const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F |
| 2464 | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU | |
| 2465 | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA; | |
| 2466 const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI | |
| 2467 | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG | |
| 145 | 2468 | PTA_RDPID | PTA_CLWB | PTA_AVX512VPOPCNTDQ; |
| 131 | 2469 const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG |
| 2470 | PTA_WBNOINVD; | |
| 145 | 2471 const wide_int_bitmask PTA_TIGERLAKE = PTA_ICELAKE_CLIENT | PTA_MOVDIRI |
| 2472 | PTA_MOVDIR64B | PTA_AVX512VP2INTERSECT; | |
| 131 | 2473 const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER |
| 2474 | PTA_AVX512F | PTA_AVX512CD; | |
| 2475 const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE; | |
| 2476 const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND; | |
| 145 | 2477 const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_AES | PTA_SHA | PTA_XSAVE |
| 131 | 2478 | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT |
| 2479 | PTA_FSGSBASE; | |
| 2480 const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID | |
| 145 | 2481 | PTA_SGX | PTA_PTWRITE; |
| 131 | 2482 const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB |
| 2483 | PTA_GFNI; | |
| 2484 const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW | |
| 2485 | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ; | |
| 2486 | |
| 2487 #ifndef GENERATOR_FILE | |
| 2488 | |
| 2489 #include "insn-attr-common.h" | |
| 2490 | |
| 145 | 2491 class pta |
| 131 | 2492 { |
| 145 | 2493 public: |
| 131 | 2494 const char *const name; /* processor name or nickname. */ |
| 2495 const enum processor_type processor; | |
| 2496 const enum attr_cpu schedule; | |
| 2497 const wide_int_bitmask flags; | |
| 2498 }; | |
| 2499 | |
| 2500 extern const pta processor_alias_table[]; | |
| 2501 extern int const pta_size; | |
| 2502 #endif | |
| 2503 | |
| 2504 #endif | |
| 2505 | |
| 0 | 2506 extern enum processor_type ix86_tune; |
| 2507 extern enum processor_type ix86_arch; | |
| 2508 | |
| 2509 /* Size of the RED_ZONE area. */ | |
| 2510 #define RED_ZONE_SIZE 128 | |
| 2511 /* Reserved area of the red zone for temporaries. */ | |
| 2512 #define RED_ZONE_RESERVE 8 | |
| 2513 | |
| 2514 extern unsigned int ix86_preferred_stack_boundary; | |
| 2515 extern unsigned int ix86_incoming_stack_boundary; | |
| 2516 | |
| 2517 /* Smallest class containing REGNO. */ | |
| 2518 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; | |
| 2519 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2520 enum ix86_fpcmp_strategy { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2521 IX86_FPCMP_SAHF, |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2522 IX86_FPCMP_COMI, |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2523 IX86_FPCMP_ARITH |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2524 }; |
| 0 | 2525 |
| 2526 /* To properly truncate FP values into integers, we need to set i387 control | |
| 2527 word. We can't emit proper mode switching code before reload, as spills | |
| 2528 generated by reload may truncate values incorrectly, but we still can avoid | |
| 2529 redundant computation of new control word by the mode switching pass. | |
| 2530 The fldcw instructions are still emitted redundantly, but this is probably | |
| 2531 not going to be noticeable problem, as most CPUs do have fast path for | |
| 2532 the sequence. | |
| 2533 | |
| 2534 The machinery is to emit simple truncation instructions and split them | |
| 2535 before reload to instructions having USEs of two memory locations that | |
| 2536 are filled by this code to old and new control word. | |
| 2537 | |
| 2538 Post-reload pass may be later used to eliminate the redundant fildcw if | |
| 2539 needed. */ | |
| 2540 | |
| 111 | 2541 enum ix86_stack_slot |
| 2542 { | |
| 2543 SLOT_TEMP = 0, | |
| 2544 SLOT_CW_STORED, | |
| 145 | 2545 SLOT_CW_ROUNDEVEN, |
| 111 | 2546 SLOT_CW_TRUNC, |
| 2547 SLOT_CW_FLOOR, | |
| 2548 SLOT_CW_CEIL, | |
| 2549 SLOT_STV_TEMP, | |
| 2550 MAX_386_STACK_LOCALS | |
| 2551 }; | |
| 2552 | |
| 0 | 2553 enum ix86_entity |
| 2554 { | |
| 111 | 2555 X86_DIRFLAG = 0, |
| 2556 AVX_U128, | |
| 145 | 2557 I387_ROUNDEVEN, |
| 111 | 2558 I387_TRUNC, |
| 0 | 2559 I387_FLOOR, |
| 2560 I387_CEIL, | |
| 2561 MAX_386_ENTITIES | |
| 2562 }; | |
| 2563 | |
| 111 | 2564 enum x86_dirflag_state |
| 0 | 2565 { |
| 111 | 2566 X86_DIRFLAG_RESET, |
| 2567 X86_DIRFLAG_ANY | |
| 2568 }; | |
| 2569 | |
| 2570 enum avx_u128_state | |
| 2571 { | |
| 2572 AVX_U128_CLEAN, | |
| 2573 AVX_U128_DIRTY, | |
| 2574 AVX_U128_ANY | |
| 0 | 2575 }; |
| 2576 | |
| 2577 /* Define this macro if the port needs extra instructions inserted | |
| 2578 for mode switching in an optimizing compilation. */ | |
| 2579 | |
| 2580 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ | |
| 2581 ix86_optimize_mode_switching[(ENTITY)] | |
| 2582 | |
| 2583 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as | |
| 2584 initializer for an array of integers. Each initializer element N | |
| 2585 refers to an entity that needs mode switching, and specifies the | |
| 2586 number of different modes that might need to be set for this | |
| 2587 entity. The position of the initializer in the initializer - | |
| 2588 starting counting at zero - determines the integer that is used to | |
| 2589 refer to the mode-switched entity in question. */ | |
| 2590 | |
| 111 | 2591 #define NUM_MODES_FOR_MODE_SWITCHING \ |
| 2592 { X86_DIRFLAG_ANY, AVX_U128_ANY, \ | |
| 145 | 2593 I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } |
| 0 | 2594 |
| 2595 | |
| 2596 /* Avoid renaming of stack registers, as doing so in combination with | |
| 2597 scheduling just increases amount of live registers at time and in | |
| 2598 the turn amount of fxch instructions needed. | |
| 2599 | |
| 111 | 2600 ??? Maybe Pentium chips benefits from renaming, someone can try.... |
| 2601 | |
| 2602 Don't rename evex to non-evex sse registers. */ | |
| 2603 | |
| 2604 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ | |
| 2605 (!STACK_REGNO_P (SRC) \ | |
| 2606 && EXT_REX_SSE_REGNO_P (SRC) == EXT_REX_SSE_REGNO_P (TARGET)) | |
| 0 | 2607 |
| 2608 | |
| 2609 #define FASTCALL_PREFIX '@' | |
| 2610 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2611 #ifndef USED_FOR_TARGET |
| 111 | 2612 /* Structure describing stack frame layout. |
| 2613 Stack grows downward: | |
| 2614 | |
| 2615 [arguments] | |
| 2616 <- ARG_POINTER | |
| 2617 saved pc | |
| 2618 | |
| 2619 saved static chain if ix86_static_chain_on_stack | |
| 2620 | |
| 2621 saved frame pointer if frame_pointer_needed | |
| 2622 <- HARD_FRAME_POINTER | |
| 2623 [saved regs] | |
| 2624 <- reg_save_offset | |
| 2625 [padding0] | |
| 2626 <- stack_realign_offset | |
| 2627 [saved SSE regs] | |
| 2628 OR | |
| 2629 [stub-saved registers for ms x64 --> sysv clobbers | |
| 2630 <- Start of out-of-line, stub-saved/restored regs | |
| 2631 (see libgcc/config/i386/(sav|res)ms64*.S) | |
| 2632 [XMM6-15] | |
| 2633 [RSI] | |
| 2634 [RDI] | |
| 2635 [?RBX] only if RBX is clobbered | |
| 2636 [?RBP] only if RBP and RBX are clobbered | |
| 2637 [?R12] only if R12 and all previous regs are clobbered | |
| 2638 [?R13] only if R13 and all previous regs are clobbered | |
| 2639 [?R14] only if R14 and all previous regs are clobbered | |
| 2640 [?R15] only if R15 and all previous regs are clobbered | |
| 2641 <- end of stub-saved/restored regs | |
| 2642 [padding1] | |
| 2643 ] | |
| 2644 <- sse_reg_save_offset | |
| 2645 [padding2] | |
| 2646 | <- FRAME_POINTER | |
| 2647 [va_arg registers] | | |
| 2648 | | |
| 2649 [frame] | | |
| 2650 | | |
| 2651 [padding2] | = to_allocate | |
| 2652 <- STACK_POINTER | |
| 2653 */ | |
| 2654 struct GTY(()) ix86_frame | |
| 2655 { | |
| 2656 int nsseregs; | |
| 2657 int nregs; | |
| 2658 int va_arg_size; | |
| 2659 int red_zone_size; | |
| 2660 int outgoing_arguments_size; | |
| 2661 | |
| 2662 /* The offsets relative to ARG_POINTER. */ | |
| 2663 HOST_WIDE_INT frame_pointer_offset; | |
| 2664 HOST_WIDE_INT hard_frame_pointer_offset; | |
| 2665 HOST_WIDE_INT stack_pointer_offset; | |
| 2666 HOST_WIDE_INT hfp_save_offset; | |
| 2667 HOST_WIDE_INT reg_save_offset; | |
| 2668 HOST_WIDE_INT stack_realign_allocate; | |
| 2669 HOST_WIDE_INT stack_realign_offset; | |
| 2670 HOST_WIDE_INT sse_reg_save_offset; | |
| 2671 | |
| 2672 /* When save_regs_using_mov is set, emit prologue using | |
| 2673 move instead of push instructions. */ | |
| 2674 bool save_regs_using_mov; | |
| 145 | 2675 |
| 2676 /* Assume without checking that: | |
| 2677 EXPENSIVE_P = expensive_function_p (EXPENSIVE_COUNT). */ | |
| 2678 bool expensive_p; | |
| 2679 int expensive_count; | |
| 111 | 2680 }; |
| 2681 | |
| 2682 /* Machine specific frame tracking during prologue/epilogue generation. All | |
| 2683 values are positive, but since the x86 stack grows downward, are subtratced | |
| 2684 from the CFA to produce a valid address. */ | |
| 2685 | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2686 struct GTY(()) machine_frame_state |
| 0 | 2687 { |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2688 /* This pair tracks the currently active CFA as reg+offset. When reg |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2689 is drap_reg, we don't bother trying to record here the real CFA when |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2690 it might really be a DW_CFA_def_cfa_expression. */ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2691 rtx cfa_reg; |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2692 HOST_WIDE_INT cfa_offset; |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2693 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2694 /* The current offset (canonically from the CFA) of ESP and EBP. |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2695 When stack frame re-alignment is active, these may not be relative |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2696 to the CFA. However, in all cases they are relative to the offsets |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2697 of the saved registers stored in ix86_frame. */ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2698 HOST_WIDE_INT sp_offset; |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2699 HOST_WIDE_INT fp_offset; |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2700 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2701 /* The size of the red-zone that may be assumed for the purposes of |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2702 eliding register restore notes in the epilogue. This may be zero |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2703 if no red-zone is in effect, or may be reduced from the real |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2704 red-zone value by a maximum runtime stack re-alignment value. */ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2705 int red_zone_offset; |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2706 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2707 /* Indicate whether each of ESP, EBP or DRAP currently holds a valid |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2708 value within the frame. If false then the offset above should be |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2709 ignored. Note that DRAP, if valid, *always* points to the CFA and |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2710 thus has an offset of zero. */ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2711 BOOL_BITFIELD sp_valid : 1; |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2712 BOOL_BITFIELD fp_valid : 1; |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2713 BOOL_BITFIELD drap_valid : 1; |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2714 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2715 /* Indicate whether the local stack frame has been re-aligned. When |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2716 set, the SP/FP offsets above are relative to the aligned frame |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2717 and not the CFA. */ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2718 BOOL_BITFIELD realigned : 1; |
| 111 | 2719 |
| 2720 /* Indicates whether the stack pointer has been re-aligned. When set, | |
| 2721 SP/FP continue to be relative to the CFA, but the stack pointer | |
| 2722 should only be used for offsets > sp_realigned_offset, while | |
| 2723 the frame pointer should be used for offsets <= sp_realigned_fp_last. | |
| 2724 The flags realigned and sp_realigned are mutually exclusive. */ | |
| 2725 BOOL_BITFIELD sp_realigned : 1; | |
| 2726 | |
| 2727 /* If sp_realigned is set, this is the last valid offset from the CFA | |
| 2728 that can be used for access with the frame pointer. */ | |
| 2729 HOST_WIDE_INT sp_realigned_fp_last; | |
| 2730 | |
| 2731 /* If sp_realigned is set, this is the offset from the CFA that the stack | |
| 2732 pointer was realigned, and may or may not be equal to sp_realigned_fp_last. | |
| 2733 Access via the stack pointer is only valid for offsets that are greater than | |
| 2734 this value. */ | |
| 2735 HOST_WIDE_INT sp_realigned_offset; | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2736 }; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2737 |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2738 /* Private to winnt.c. */ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2739 struct seh_frame_state; |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2740 |
| 111 | 2741 enum function_type |
| 2742 { | |
| 2743 TYPE_UNKNOWN = 0, | |
| 2744 TYPE_NORMAL, | |
| 2745 /* The current function is an interrupt service routine with a | |
| 2746 pointer argument as specified by the "interrupt" attribute. */ | |
| 2747 TYPE_INTERRUPT, | |
| 2748 /* The current function is an interrupt service routine with a | |
| 2749 pointer argument and an integer argument as specified by the | |
| 2750 "interrupt" attribute. */ | |
| 2751 TYPE_EXCEPTION | |
| 2752 }; | |
| 2753 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2754 struct GTY(()) machine_function { |
| 0 | 2755 struct stack_local_entry *stack_locals; |
| 2756 int varargs_gpr_size; | |
| 2757 int varargs_fpr_size; | |
| 2758 int optimize_mode_switching[MAX_386_ENTITIES]; | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2759 |
| 111 | 2760 /* Cached initial frame layout for the current function. */ |
| 2761 struct ix86_frame frame; | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2762 |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2763 /* For -fsplit-stack support: A stack local which holds a pointer to |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2764 the stack arguments for a function with a variable number of |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2765 arguments. This is set at the start of the function and is used |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2766 to initialize the overflow_arg_area field of the va_list |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2767 structure. */ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2768 rtx split_stack_varargs_pointer; |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2769 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2770 /* This value is used for amd64 targets and specifies the current abi |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2771 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2772 ENUM_BITFIELD(calling_abi) call_abi : 8; |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2773 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2774 /* Nonzero if the function accesses a previous frame. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2775 BOOL_BITFIELD accesses_prev_frame : 1; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2776 |
| 0 | 2777 /* Set by ix86_compute_frame_layout and used by prologue/epilogue |
| 2778 expander to determine the style used. */ | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2779 BOOL_BITFIELD use_fast_prologue_epilogue : 1; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2780 |
| 111 | 2781 /* Nonzero if the current function calls pc thunk and |
| 2782 must not use the red zone. */ | |
| 2783 BOOL_BITFIELD pc_thunk_call_expanded : 1; | |
| 2784 | |
| 0 | 2785 /* If true, the current function needs the default PIC register, not |
| 2786 an alternate register (on x86) and must not use the red zone (on | |
| 2787 x86_64), even if it's a leaf function. We don't want the | |
| 2788 function to be regarded as non-leaf because TLS calls need not | |
| 2789 affect register allocation. This flag is set when a TLS call | |
| 2790 instruction is expanded within a function, and never reset, even | |
| 2791 if all such instructions are optimized away. Use the | |
| 2792 ix86_current_function_calls_tls_descriptor macro for a better | |
| 2793 approximation. */ | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2794 BOOL_BITFIELD tls_descriptor_call_expanded_p : 1; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2795 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2796 /* If true, the current function has a STATIC_CHAIN is placed on the |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2797 stack below the return address. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2798 BOOL_BITFIELD static_chain_on_stack : 1; |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2799 |
| 111 | 2800 /* If true, it is safe to not save/restore DRAP register. */ |
| 2801 BOOL_BITFIELD no_drap_save_restore : 1; | |
| 2802 | |
| 2803 /* Function type. */ | |
| 2804 ENUM_BITFIELD(function_type) func_type : 2; | |
| 2805 | |
| 131 | 2806 /* How to generate indirec branch. */ |
| 2807 ENUM_BITFIELD(indirect_branch) indirect_branch_type : 3; | |
| 2808 | |
| 2809 /* If true, the current function has local indirect jumps, like | |
| 2810 "indirect_jump" or "tablejump". */ | |
| 2811 BOOL_BITFIELD has_local_indirect_jump : 1; | |
| 2812 | |
| 2813 /* How to generate function return. */ | |
| 2814 ENUM_BITFIELD(indirect_branch) function_return_type : 3; | |
| 2815 | |
| 111 | 2816 /* If true, the current function is a function specified with |
| 2817 the "interrupt" or "no_caller_saved_registers" attribute. */ | |
| 2818 BOOL_BITFIELD no_caller_saved_registers : 1; | |
| 2819 | |
| 2820 /* If true, there is register available for argument passing. This | |
| 2821 is used only in ix86_function_ok_for_sibcall by 32-bit to determine | |
| 2822 if there is scratch register available for indirect sibcall. In | |
| 2823 64-bit, rax, r10 and r11 are scratch registers which aren't used to | |
| 2824 pass arguments and can be used for indirect sibcall. */ | |
| 2825 BOOL_BITFIELD arg_reg_available : 1; | |
| 2826 | |
| 2827 /* If true, we're out-of-lining reg save/restore for regs clobbered | |
| 2828 by 64-bit ms_abi functions calling a sysv_abi function. */ | |
| 2829 BOOL_BITFIELD call_ms2sysv : 1; | |
| 2830 | |
| 2831 /* If true, the incoming 16-byte aligned stack has an offset (of 8) and | |
| 2832 needs padding prior to out-of-line stub save/restore area. */ | |
| 2833 BOOL_BITFIELD call_ms2sysv_pad_in : 1; | |
| 2834 | |
| 2835 /* This is the number of extra registers saved by stub (valid range is | |
| 2836 0-6). Each additional register is only saved/restored by the stubs | |
| 2837 if all successive ones are. (Will always be zero when using a hard | |
| 2838 frame pointer.) */ | |
| 2839 unsigned int call_ms2sysv_extra_regs:3; | |
| 2840 | |
| 2841 /* Nonzero if the function places outgoing arguments on stack. */ | |
| 2842 BOOL_BITFIELD outgoing_args_on_stack : 1; | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2843 |
| 131 | 2844 /* If true, ENDBR is queued at function entrance. */ |
| 2845 BOOL_BITFIELD endbr_queued_at_entrance : 1; | |
| 2846 | |
| 145 | 2847 /* True if the function needs a stack frame. */ |
| 2848 BOOL_BITFIELD stack_frame_required : 1; | |
| 2849 | |
| 131 | 2850 /* The largest alignment, in bytes, of stack slot actually used. */ |
| 2851 unsigned int max_used_stack_alignment; | |
| 2852 | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2853 /* During prologue/epilogue generation, the current frame state. |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2854 Otherwise, the frame state at the end of the prologue. */ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2855 struct machine_frame_state fs; |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2856 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2857 /* During SEH output, this is non-null. */ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2858 struct seh_frame_state * GTY((skip(""))) seh; |
| 0 | 2859 }; |
| 145 | 2860 |
| 2861 extern GTY(()) tree sysv_va_list_type_node; | |
| 2862 extern GTY(()) tree ms_va_list_type_node; | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2863 #endif |
| 0 | 2864 |
| 2865 #define ix86_stack_locals (cfun->machine->stack_locals) | |
| 2866 #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) | |
| 2867 #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) | |
| 2868 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) | |
| 111 | 2869 #define ix86_pc_thunk_call_expanded (cfun->machine->pc_thunk_call_expanded) |
| 0 | 2870 #define ix86_tls_descriptor_calls_expanded_in_cfun \ |
| 2871 (cfun->machine->tls_descriptor_call_expanded_p) | |
| 2872 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS | |
| 2873 calls are optimized away, we try to detect cases in which it was | |
| 2874 optimized away. Since such instructions (use (reg REG_SP)), we can | |
| 2875 verify whether there's any such instruction live by testing that | |
| 2876 REG_SP is live. */ | |
| 2877 #define ix86_current_function_calls_tls_descriptor \ | |
| 2878 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2879 #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack) |
| 111 | 2880 #define ix86_red_zone_size (cfun->machine->frame.red_zone_size) |
| 0 | 2881 |
| 2882 /* Control behavior of x86_file_start. */ | |
| 2883 #define X86_FILE_START_VERSION_DIRECTIVE false | |
| 2884 #define X86_FILE_START_FLTUSED false | |
| 2885 | |
| 2886 /* Flag to mark data that is in the large address area. */ | |
| 2887 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) | |
| 2888 #define SYMBOL_REF_FAR_ADDR_P(X) \ | |
| 2889 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) | |
| 2890 | |
| 2891 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to | |
| 2892 have defined always, to avoid ifdefing. */ | |
| 2893 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) | |
| 2894 #define SYMBOL_REF_DLLIMPORT_P(X) \ | |
| 2895 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) | |
| 2896 | |
| 2897 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) | |
| 2898 #define SYMBOL_REF_DLLEXPORT_P(X) \ | |
| 2899 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) | |
| 2900 | |
| 111 | 2901 #define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4) |
| 2902 #define SYMBOL_REF_STUBVAR_P(X) \ | |
| 2903 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0) | |
| 2904 | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2905 extern void debug_ready_dispatch (void); |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2906 extern void debug_dispatch_window (int); |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2907 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2908 /* The value at zero is only defined for the BMI instructions |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2909 LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2910 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
| 111 | 2911 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI ? 1 : 0) |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
2912 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
| 111 | 2913 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT ? 1 : 0) |
| 2914 | |
| 2915 | |
| 2916 /* Flags returned by ix86_get_callcvt (). */ | |
| 2917 #define IX86_CALLCVT_CDECL 0x1 | |
| 2918 #define IX86_CALLCVT_STDCALL 0x2 | |
| 2919 #define IX86_CALLCVT_FASTCALL 0x4 | |
| 2920 #define IX86_CALLCVT_THISCALL 0x8 | |
| 2921 #define IX86_CALLCVT_REGPARM 0x10 | |
| 2922 #define IX86_CALLCVT_SSEREGPARM 0x20 | |
| 2923 | |
| 2924 #define IX86_BASE_CALLCVT(FLAGS) \ | |
| 2925 ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \ | |
| 2926 | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL)) | |
| 2927 | |
| 2928 #define RECIP_MASK_NONE 0x00 | |
| 2929 #define RECIP_MASK_DIV 0x01 | |
| 2930 #define RECIP_MASK_SQRT 0x02 | |
| 2931 #define RECIP_MASK_VEC_DIV 0x04 | |
| 2932 #define RECIP_MASK_VEC_SQRT 0x08 | |
| 2933 #define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \ | |
| 2934 | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) | |
| 2935 #define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) | |
| 2936 | |
| 2937 #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0) | |
| 2938 #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0) | |
| 2939 #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0) | |
| 2940 #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0) | |
| 2941 | |
| 131 | 2942 /* Use 128-bit AVX instructions in the auto-vectorizer. */ |
| 2943 #define TARGET_PREFER_AVX128 (prefer_vector_width_type == PVW_AVX128) | |
| 2944 /* Use 256-bit AVX instructions in the auto-vectorizer. */ | |
| 2945 #define TARGET_PREFER_AVX256 (TARGET_PREFER_AVX128 \ | |
| 2946 || prefer_vector_width_type == PVW_AVX256) | |
| 2947 | |
| 2948 #define TARGET_INDIRECT_BRANCH_REGISTER \ | |
| 2949 (ix86_indirect_branch_register \ | |
| 2950 || cfun->machine->indirect_branch_type != indirect_branch_keep) | |
| 2951 | |
| 111 | 2952 #define IX86_HLE_ACQUIRE (1 << 16) |
| 2953 #define IX86_HLE_RELEASE (1 << 17) | |
| 2954 | |
| 2955 /* For switching between functions with different target attributes. */ | |
| 2956 #define SWITCHABLE_TARGET 1 | |
| 2957 | |
| 2958 #define TARGET_SUPPORTS_WIDE_INT 1 | |
| 0 | 2959 |
| 145 | 2960 #if !defined(GENERATOR_FILE) && !defined(IN_LIBGCC2) |
| 2961 extern enum attr_cpu ix86_schedule; | |
| 2962 | |
| 2963 #define NUM_X86_64_MS_CLOBBERED_REGS 12 | |
| 2964 #endif | |
| 2965 | |
| 0 | 2966 /* |
| 2967 Local variables: | |
| 2968 version-control: t | |
| 2969 End: | |
| 2970 */ |