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1 ;; DFA-based pipeline descriptions for MIPS Technologies 24K core.
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2 ;; Contributed by Chao-ying Fu (fu@mips.com), Nigel Stephens (nigel@mips.com)
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3 ;; and David Ung (davidu@mips.com)
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4 ;;
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5 ;; The 24kf2_1 is a single-issue processor with a half-clocked fpu.
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6 ;; The 24kf1_1 is 24k with 1:1 clocked fpu.
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7 ;;
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8 ;; References:
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9 ;; "MIPS32 24K Processor Core Family Software User's Manual, Rev 3.04."
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10 ;;
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145
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11 ;; Copyright (C) 2005-2020 Free Software Foundation, Inc.
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12 ;;
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13 ;; This file is part of GCC.
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14 ;;
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15 ;; GCC is free software; you can redistribute it and/or modify it
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16 ;; under the terms of the GNU General Public License as published
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17 ;; by the Free Software Foundation; either version 3, or (at your
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18 ;; option) any later version.
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19
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20 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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21 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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22 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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23 ;; License for more details.
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24
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25 ;; You should have received a copy of the GNU General Public License
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26 ;; along with GCC; see the file COPYING3. If not see
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27 ;; <http://www.gnu.org/licenses/>.
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28
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29 (define_automaton "r24k_cpu, r24k_mdu, r24k_fpu")
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30
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31 ;; Integer execution unit.
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32 (define_cpu_unit "r24k_iss" "r24k_cpu")
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33 (define_cpu_unit "r24k_ixu_arith" "r24k_cpu")
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34 (define_cpu_unit "r24k_mul3a" "r24k_mdu")
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35 (define_cpu_unit "r24k_mul3b" "r24k_mdu")
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36 (define_cpu_unit "r24k_mul3c" "r24k_mdu")
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37
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38 ;; --------------------------------------------------------------
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39 ;; Producers
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40 ;; --------------------------------------------------------------
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41
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42 ;; 1. Loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
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43 (define_insn_reservation "r24k_int_load" 2
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44 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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45 (eq_attr "type" "load"))
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46 "r24k_iss+r24k_ixu_arith")
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47
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48
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49 ;; 2. Arithmetic: add, addi, addiu, addiupc, addu, and, andi, clo, clz,
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50 ;; ext, ins, lui, movn, movz, nor, or, ori, rotr, rotrv, seb, seh, sll,
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51 ;; sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, wsbh,
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52 ;; xor, xori
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53 ;; (movn/movz is not matched, we'll need to split condmov to
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54 ;; differentiate between integer/float moves)
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55 (define_insn_reservation "r24k_int_arith" 1
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56 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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57 (eq_attr "type" "arith,const,logical,move,nop,shift,signext,slt"))
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58 "r24k_iss+r24k_ixu_arith")
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59
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60
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61 ;; 3. Links: bgezal, bgezall, bltzal, bltzall, jal, jalr, jalx
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62 ;; 3a. jr/jalr consumer
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63 (define_insn_reservation "r24k_int_jump" 1
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64 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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65 (eq_attr "type" "call,jump"))
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66 "r24k_iss+r24k_ixu_arith")
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67
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68 ;; 3b. branch consumer
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69 (define_insn_reservation "r24k_int_branch" 1
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70 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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71 (eq_attr "type" "branch"))
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72 "r24k_iss+r24k_ixu_arith")
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73
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74
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75 ;; 4. MDU: fully pipelined multiplier
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76 ;; mult - delivers result to hi/lo in 1 cycle (pipelined)
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77 (define_insn_reservation "r24k_int_mult" 1
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78 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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79 (eq_attr "type" "imul"))
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80 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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81
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82 ;; madd, msub - delivers result to hi/lo in 1 cycle (pipelined)
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83 (define_insn_reservation "r24k_int_madd" 1
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84 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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85 (eq_attr "type" "imadd"))
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86 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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87
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88 ;; mul - delivers result to gpr in 5 cycles
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89 (define_insn_reservation "r24k_int_mul3" 5
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90 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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91 (eq_attr "type" "imul3"))
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92 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)*5")
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93
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94 ;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles
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95 (define_insn_reservation "r24k_int_mfhilo" 5
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96 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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97 (eq_attr "type" "mfhi,mflo"))
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98 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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99
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100 ;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
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101 (define_insn_reservation "r24k_int_mthilo" 1
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102 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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103 (eq_attr "type" "mthi,mtlo"))
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104 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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105
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106 ;; div - default to 36 cycles for 32bit operands. Faster for 24bit, 16bit and
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107 ;; 8bit, but is tricky to identify.
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108 (define_insn_reservation "r24k_int_div" 36
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109 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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110 (eq_attr "type" "idiv"))
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111 "r24k_iss+(r24k_mul3a+r24k_mul3b+r24k_mul3c)*36")
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112
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113
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114 ;; 5. Cop: cfc1, di, ei, mfc0, mtc0
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115 ;; (Disabled until we add proper cop0 support)
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116 ;;(define_insn_reservation "r24k_int_cop" 3
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117 ;; (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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118 ;; (eq_attr "type" "cop0"))
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119 ;; "r24k_iss+r24k_ixu_arith")
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120
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121
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122 ;; 6. Store
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123 (define_insn_reservation "r24k_int_store" 1
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124 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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125 (eq_attr "type" "store"))
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126 "r24k_iss+r24k_ixu_arith")
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127
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128
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129 ;; 7. Multiple instructions
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130 (define_insn_reservation "r24k_int_multi" 1
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131 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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132 (eq_attr "type" "multi"))
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133 "r24k_iss+r24k_ixu_arith+r24k_fpu_arith+(r24k_mul3a+r24k_mul3b+r24k_mul3c)")
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134
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135
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136 ;; 8. Unknowns - Currently these include blockage, consttable and alignment
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137 ;; rtls. They do not really affect scheduling latency, (blockage affects
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138 ;; scheduling via log links, but not used here).
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139 (define_insn_reservation "r24k_int_unknown" 0
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140 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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111
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141 (eq_attr "type" "unknown,atomic,syncloop"))
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142 "r24k_iss")
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143
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144
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145 ;; 9. Prefetch
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146 (define_insn_reservation "r24k_int_prefetch" 1
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147 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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148 (eq_attr "type" "prefetch,prefetchx"))
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149 "r24k_iss+r24k_ixu_arith")
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150
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151
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152 ;; --------------------------------------------------------------
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153 ;; Bypass to Consumer
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154 ;; --------------------------------------------------------------
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155
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156 ;; load->next use : 2 cycles (Default)
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157 ;; load->load base: 3 cycles
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158 ;; load->store base: 3 cycles
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159 ;; load->prefetch: 3 cycles
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160 (define_bypass 3 "r24k_int_load" "r24k_int_load")
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111
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161 (define_bypass 3 "r24k_int_load" "r24k_int_store" "!mips_store_data_bypass_p")
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162 (define_bypass 3 "r24k_int_load" "r24k_int_prefetch")
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163
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164 ;; arith->next use : 1 cycles (Default)
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165 ;; arith->load base: 2 cycles
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166 ;; arith->store base: 2 cycles
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167 ;; arith->prefetch: 2 cycles
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168 (define_bypass 2 "r24k_int_arith" "r24k_int_load")
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111
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169 (define_bypass 2 "r24k_int_arith" "r24k_int_store" "!mips_store_data_bypass_p")
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170 (define_bypass 2 "r24k_int_arith" "r24k_int_prefetch")
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171
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172 ;; mul3->next use : 5 cycles (default)
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173 ;; mul3->l/s base : 6 cycles
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174 ;; mul3->prefetch : 6 cycles
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175 (define_bypass 6 "r24k_int_mul3" "r24k_int_load")
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111
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176 (define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!mips_store_data_bypass_p")
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177 (define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch")
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178
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179 ;; mul3->madd/msub : 1 cycle
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180 (define_bypass 1 "r24k_int_mul3" "r24k_int_madd" "mips_linked_madd_p")
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181
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182 ;; mfhilo->next use : 5 cycles (default)
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183 ;; mfhilo->l/s base : 6 cycles
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184 ;; mfhilo->prefetch : 6 cycles
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185 ;; mthilo->madd/msub : 2 cycle (only for mthi/lo not mfhi/lo)
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186 (define_bypass 6 "r24k_int_mfhilo" "r24k_int_load")
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111
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187 (define_bypass 6 "r24k_int_mfhilo" "r24k_int_store"
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188 "!mips_store_data_bypass_p")
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189 (define_bypass 6 "r24k_int_mfhilo" "r24k_int_prefetch")
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190 (define_bypass 2 "r24k_int_mthilo" "r24k_int_madd")
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191
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192 ;; cop->next use : 3 cycles (Default)
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193 ;; cop->l/s base : 4 cycles
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194 ;; (define_bypass 4 "r24k_int_cop" "r24k_int_load")
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111
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195 ;; (define_bypass 4 "r24k_int_cop" "r24k_int_store"
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196 ;; "!mips_store_data_bypass_p")
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197
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198 ;; multi->next use : 1 cycles (Default)
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199 ;; multi->l/s base : 2 cycles
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200 ;; multi->prefetch : 2 cycles
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201 (define_bypass 2 "r24k_int_multi" "r24k_int_load")
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111
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202 (define_bypass 2 "r24k_int_multi" "r24k_int_store" "!mips_store_data_bypass_p")
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203 (define_bypass 2 "r24k_int_multi" "r24k_int_prefetch")
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204
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205
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206 ;; --------------------------------------------------------------
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111
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207 ;; DSP instructions
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208 ;; --------------------------------------------------------------
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209
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210 ;; absq, addq, addsc, addu, addwc, bitrev, cmp, cmpgu, cmpu, insv, modsub,
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211 ;; packrl, pick, preceq, preceu, precequ, precrq, precrqu, raddu, rddsp, repl,
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212 ;; replv, shll, shllv, shra, shrav, shrl, shrlv, subq, subu, wrdsp
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213 (define_insn_reservation "r24k_dsp_alu" 2
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214 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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215 (eq_attr "type" "dspalu,dspalusat"))
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216 "r24k_iss+r24k_ixu_arith")
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217
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218 ;; dpaq_s, dpau, dpsq_s, dpsu, maq_s, mulsaq
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219 (define_insn_reservation "r24k_dsp_mac" 1
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220 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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221 (eq_attr "type" "dspmac"))
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222 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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223
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224 ;; dpaq_sa, dpsq_sa, maq_sa
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225 (define_insn_reservation "r24k_dsp_mac_sat" 1
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226 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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227 (eq_attr "type" "dspmacsat"))
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228 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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229
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230 ;; extp, extpdp, extpdpv, extpv, extr, extrv
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231 (define_insn_reservation "r24k_dsp_acc_ext" 5
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232 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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233 (eq_attr "type" "accext"))
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234 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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235
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236 ;; mthlip, shilo, shilov
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237 (define_insn_reservation "r24k_dsp_acc_mod" 1
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238 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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239 (eq_attr "type" "accmod"))
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240 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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241
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242
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243 ;; mult/madd->dsp_acc_ext : 4 cycles
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244 ;; mult/madd->dsp_acc_mod : 4 cycles
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245 (define_bypass 4 "r24k_int_mult" "r24k_dsp_acc_ext")
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246 (define_bypass 4 "r24k_int_mult" "r24k_dsp_acc_mod")
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247
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248 ;; mthilo->dsp_acc_ext : 4 cycles
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249 ;; mthilo->dsp_acc_ext : 4 cycles
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250 (define_bypass 4 "r24k_int_mthilo" "r24k_dsp_acc_ext")
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251 (define_bypass 4 "r24k_int_mthilo" "r24k_dsp_acc_mod")
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252
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253 ;; dsp_mac->next use : 1 cycles (default)
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254 ;; dsp_mac->dsp_acc_ext : 4 cycles
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255 ;; dsp_mac->dsp_acc_mod : 4 cycles
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256 (define_bypass 4 "r24k_dsp_mac" "r24k_dsp_acc_ext")
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257 (define_bypass 4 "r24k_dsp_mac" "r24k_dsp_acc_mod")
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258
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259 ;; dsp_mac_sat->next use : 1 cycles (default)
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260 ;; dsp_mac_sat->mult/madd : 2 cycles
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261 ;; dsp_mac_sat->dsp_mac : 2 cycles
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262 ;; dsp_mac_sat->dsp_mac_sat : 2 cycles
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263 ;; dsp_mac_sat->dsp_acc_ext : 4 cycles
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264 ;; dsp_mac_sat->dsp_acc_mod : 4 cycles
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265 (define_bypass 2 "r24k_dsp_mac_sat" "r24k_int_mult")
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266 (define_bypass 2 "r24k_dsp_mac_sat" "r24k_dsp_mac")
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267 (define_bypass 2 "r24k_dsp_mac_sat" "r24k_dsp_mac_sat")
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268 (define_bypass 4 "r24k_dsp_mac_sat" "r24k_dsp_acc_ext")
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269 (define_bypass 4 "r24k_dsp_mac_sat" "r24k_dsp_acc_mod")
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270
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271 ;; dsp_acc_ext->next use : 5 cycles (default)
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272 ;; dsp_acc_ext->l/s base : 6 cycles
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273 ;; dsp_acc_ext->prefetch : 6 cycles
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274 (define_bypass 6 "r24k_dsp_acc_ext" "r24k_int_load")
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275 (define_bypass 6 "r24k_dsp_acc_ext" "r24k_int_store"
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276 "!mips_store_data_bypass_p")
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277 (define_bypass 6 "r24k_dsp_acc_ext" "r24k_int_prefetch")
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278
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279 ;; dsp_acc_mod->next use : 1 cycles (default)
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280 ;; dsp_acc_mod->mult/madd : 2 cycles
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281 ;; dsp_acc_mod->dsp_mac : 2 cycles
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282 ;; dsp_acc_mod->dsp_mac_sat : 2 cycles
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283 ;; dsp_acc_mod->dsp_acc_ext : 4 cycles
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284 ;; dsp_acc_mod->dsp_acc_mod : 4 cycles
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285 (define_bypass 2 "r24k_dsp_acc_mod" "r24k_int_mult")
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286 (define_bypass 2 "r24k_dsp_acc_mod" "r24k_dsp_mac")
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287 (define_bypass 2 "r24k_dsp_acc_mod" "r24k_dsp_mac_sat")
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288 (define_bypass 4 "r24k_dsp_acc_mod" "r24k_dsp_acc_ext")
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289 (define_bypass 4 "r24k_dsp_acc_mod" "r24k_dsp_acc_mod")
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290
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291 ;; dspalu->next use : 2 cycles (default)
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292 ;; dspalu->l/s base : 3 cycles
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293 ;; dspalu->prefetch : 3 cycles
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294 ;; some pairs of dspalu (addsc/addwc, cmp/pick, wrdsp/insv) : 1 cycle
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295 (define_bypass 3 "r24k_dsp_alu" "r24k_int_load")
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296 (define_bypass 3 "r24k_dsp_alu" "r24k_int_store" "!mips_store_data_bypass_p")
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297 (define_bypass 3 "r24k_dsp_alu" "r24k_int_prefetch")
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298 (define_bypass 1 "r24k_dsp_alu" "r24k_dsp_alu" "mips_dspalu_bypass_p")
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299
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300
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301 ;; --------------------------------------------------------------
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0
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302 ;; Floating Point Instructions
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303 ;; --------------------------------------------------------------
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304
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305 (define_cpu_unit "r24k_fpu_arith" "r24k_fpu")
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306
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307 ;; The 24k is a single issue cpu, and the fpu runs at half clock speed,
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308 ;; so each fpu instruction ties up the shared instruction scheduler for
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309 ;; 1 cycle, and the fpu scheduler for 2 cycles.
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310 ;;
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311 ;; These timings are therefore twice the values in the 24K manual,
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312 ;; which are quoted in fpu clocks.
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313 ;;
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314 ;; The 24kf1_1 is a 24k configured with 1:1 cpu and fpu, so use
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315 ;; the unscaled timings
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316
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317 (define_reservation "r24kf2_1_fpu_iss" "r24k_iss+(r24k_fpu_arith*2)")
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318
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319 ;; fadd, fabs, fneg
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320 (define_insn_reservation "r24kf2_1_fadd" 8
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321 (and (eq_attr "cpu" "24kf2_1")
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322 (eq_attr "type" "fadd,fabs,fneg"))
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323 "r24kf2_1_fpu_iss")
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324
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325 ;; fmove, fcmove
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326 (define_insn_reservation "r24kf2_1_fmove" 8
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327 (and (eq_attr "cpu" "24kf2_1")
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328 (eq_attr "type" "fmove,condmove"))
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329 "r24kf2_1_fpu_iss")
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330
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331 ;; fload
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332 (define_insn_reservation "r24kf2_1_fload" 6
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333 (and (eq_attr "cpu" "24kf2_1")
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334 (eq_attr "type" "fpload,fpidxload"))
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335 "r24kf2_1_fpu_iss")
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336
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337 ;; fstore
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338 (define_insn_reservation "r24kf2_1_fstore" 2
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339 (and (eq_attr "cpu" "24kf2_1")
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340 (eq_attr "type" "fpstore"))
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341 "r24kf2_1_fpu_iss")
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342
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343 ;; fmul, fmadd
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344 (define_insn_reservation "r24kf2_1_fmul_sf" 8
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345 (and (eq_attr "cpu" "24kf2_1")
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346 (and (eq_attr "type" "fmul,fmadd")
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347 (eq_attr "mode" "SF")))
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348 "r24kf2_1_fpu_iss")
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349
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350 (define_insn_reservation "r24kf2_1_fmul_df" 10
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351 (and (eq_attr "cpu" "24kf2_1")
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352 (and (eq_attr "type" "fmul,fmadd")
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353 (eq_attr "mode" "DF")))
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354 "r24kf2_1_fpu_iss,(r24k_fpu_arith*2)")
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355
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356
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357 ;; fdiv, fsqrt, frsqrt
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358 (define_insn_reservation "r24kf2_1_fdiv_sf" 34
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359 (and (eq_attr "cpu" "24kf2_1")
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360 (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
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361 (eq_attr "mode" "SF")))
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362 "r24kf2_1_fpu_iss,(r24k_fpu_arith*26)")
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363
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364 (define_insn_reservation "r24kf2_1_fdiv_df" 64
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365 (and (eq_attr "cpu" "24kf2_1")
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366 (and (eq_attr "type" "fdiv,fsqrt")
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367 (eq_attr "mode" "DF")))
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368 "r24kf2_1_fpu_iss,(r24k_fpu_arith*56)")
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369
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370 ;; frsqrt
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371 (define_insn_reservation "r24kf2_1_frsqrt_df" 70
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372 (and (eq_attr "cpu" "24kf2_1")
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373 (and (eq_attr "type" "frsqrt")
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374 (eq_attr "mode" "DF")))
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375 "r24kf2_1_fpu_iss,(r24k_fpu_arith*60)")
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376
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377 ;; fcmp
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378 (define_insn_reservation "r24kf2_1_fcmp" 4
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379 (and (eq_attr "cpu" "24kf2_1")
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380 (eq_attr "type" "fcmp"))
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381 "r24kf2_1_fpu_iss")
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382
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383 ;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition)
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384 (define_bypass 2 "r24kf2_1_fcmp" "r24kf2_1_fmove")
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385
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386 ;; fcvt (cvt.d.s, cvt.[sd].[wl])
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387 (define_insn_reservation "r24kf2_1_fcvt_i2f_s2d" 8
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388 (and (eq_attr "cpu" "24kf2_1")
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389 (and (eq_attr "type" "fcvt")
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390 (eq_attr "cnv_mode" "I2S,I2D,S2D")))
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391 "r24kf2_1_fpu_iss")
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392
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393 ;; fcvt (cvt.s.d)
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394 (define_insn_reservation "r24kf2_1_fcvt_s2d" 12
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395 (and (eq_attr "cpu" "24kf2_1")
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396 (and (eq_attr "type" "fcvt")
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397 (eq_attr "cnv_mode" "D2S")))
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398 "r24kf2_1_fpu_iss")
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399
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400 ;; fcvt (cvt.[wl].[sd], etc)
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401 (define_insn_reservation "r24kf2_1_fcvt_f2i" 10
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402 (and (eq_attr "cpu" "24kf2_1")
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403 (and (eq_attr "type" "fcvt")
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404 (eq_attr "cnv_mode" "S2I,D2I")))
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405 "r24kf2_1_fpu_iss")
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406
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407 ;; fxfer (mfc1, mfhc1, mtc1, mthc1)
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408 (define_insn_reservation "r24kf2_1_fxfer" 4
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409 (and (eq_attr "cpu" "24kf2_1")
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410 (eq_attr "type" "mfc,mtc"))
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411 "r24kf2_1_fpu_iss")
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412
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413 ;; --------------------------------------------------------------
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414 ;; Bypass to Consumer
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415 ;; --------------------------------------------------------------
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416 ;; r24kf2_1_fcvt_f2i->l/s base : 11 cycles
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417 ;; r24kf2_1_fcvt_f2i->prefetch : 11 cycles
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418 (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_load")
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111
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419 (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_store"
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420 "!mips_store_data_bypass_p")
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0
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421 (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_prefetch")
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422
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423 ;; r24kf2_1_fxfer->l/s base : 5 cycles
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424 ;; r24kf2_1_fxfer->prefetch : 5 cycles
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425 (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_load")
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111
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426 (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_store" "!mips_store_data_bypass_p")
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0
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427 (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_prefetch")
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428
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429 ;; --------------------------------------------------------------
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430 ;; The 24kf1_1 is a 24k configured with 1:1 cpu and fpu, so use
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431 ;; the unscaled timings
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432 ;; --------------------------------------------------------------
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433
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434 (define_reservation "r24kf1_1_fpu_iss" "r24k_iss+r24k_fpu_arith")
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435
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436 ;; fadd, fabs, fneg
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437 (define_insn_reservation "r24kf1_1_fadd" 4
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438 (and (eq_attr "cpu" "24kf1_1")
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439 (eq_attr "type" "fadd,fabs,fneg"))
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440 "r24kf1_1_fpu_iss")
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441
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442 ;; fmove, fcmove
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443 (define_insn_reservation "r24kf1_1_fmove" 4
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444 (and (eq_attr "cpu" "24kf1_1")
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445 (eq_attr "type" "fmove,condmove"))
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446 "r24kf1_1_fpu_iss")
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447
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448 ;; fload
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449 (define_insn_reservation "r24kf1_1_fload" 3
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450 (and (eq_attr "cpu" "24kf1_1")
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451 (eq_attr "type" "fpload,fpidxload"))
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452 "r24kf1_1_fpu_iss")
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453
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454 ;; fstore
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455 (define_insn_reservation "r24kf1_1_fstore" 1
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456 (and (eq_attr "cpu" "24kf1_1")
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457 (eq_attr "type" "fpstore"))
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458 "r24kf1_1_fpu_iss")
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459
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460 ;; fmul, fmadd
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461 (define_insn_reservation "r24kf1_1_fmul_sf" 4
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462 (and (eq_attr "cpu" "24kf1_1")
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463 (and (eq_attr "type" "fmul,fmadd")
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464 (eq_attr "mode" "SF")))
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465 "r24kf1_1_fpu_iss")
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466
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467 (define_insn_reservation "r24kf1_1_fmul_df" 5
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468 (and (eq_attr "cpu" "24kf1_1")
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469 (and (eq_attr "type" "fmul,fmadd")
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470 (eq_attr "mode" "DF")))
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471 "r24kf1_1_fpu_iss,r24k_fpu_arith")
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472
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473
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474 ;; fdiv, fsqrt, frsqrt
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475 (define_insn_reservation "r24kf1_1_fdiv_sf" 17
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476 (and (eq_attr "cpu" "24kf1_1")
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477 (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
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478 (eq_attr "mode" "SF")))
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479 "r24kf1_1_fpu_iss,(r24k_fpu_arith*13)")
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480
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481 (define_insn_reservation "r24kf1_1_fdiv_df" 32
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482 (and (eq_attr "cpu" "24kf1_1")
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483 (and (eq_attr "type" "fdiv,fsqrt")
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484 (eq_attr "mode" "DF")))
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485 "r24kf1_1_fpu_iss,(r24k_fpu_arith*28)")
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486
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487 ;; frsqrt
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488 (define_insn_reservation "r24kf1_1_frsqrt_df" 35
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489 (and (eq_attr "cpu" "24kf1_1")
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490 (and (eq_attr "type" "frsqrt")
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491 (eq_attr "mode" "DF")))
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492 "r24kf1_1_fpu_iss,(r24k_fpu_arith*30)")
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493
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494 ;; fcmp
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495 (define_insn_reservation "r24kf1_1_fcmp" 2
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496 (and (eq_attr "cpu" "24kf1_1")
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497 (eq_attr "type" "fcmp"))
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498 "r24kf1_1_fpu_iss")
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499
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500 ;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition)
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501 (define_bypass 1 "r24kf1_1_fcmp" "r24kf1_1_fmove")
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502
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503 ;; fcvt (cvt.d.s, cvt.[sd].[wl])
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504 (define_insn_reservation "r24kf1_1_fcvt_i2f_s2d" 4
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505 (and (eq_attr "cpu" "24kf1_1")
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506 (and (eq_attr "type" "fcvt")
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507 (eq_attr "cnv_mode" "I2S,I2D,S2D")))
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508 "r24kf1_1_fpu_iss")
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509
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|
510 ;; fcvt (cvt.s.d)
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511 (define_insn_reservation "r24kf1_1_fcvt_s2d" 6
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512 (and (eq_attr "cpu" "24kf1_1")
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513 (and (eq_attr "type" "fcvt")
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514 (eq_attr "cnv_mode" "D2S")))
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515 "r24kf1_1_fpu_iss")
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516
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517 ;; fcvt (cvt.[wl].[sd], etc)
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518 (define_insn_reservation "r24kf1_1_fcvt_f2i" 5
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519 (and (eq_attr "cpu" "24kf1_1")
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520 (and (eq_attr "type" "fcvt")
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521 (eq_attr "cnv_mode" "S2I,D2I")))
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522 "r24kf1_1_fpu_iss")
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523
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|
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524 ;; fxfer (mfc1, mfhc1, mtc1, mthc1)
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525 (define_insn_reservation "r24kf1_1_fxfer" 2
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526 (and (eq_attr "cpu" "24kf1_1")
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527 (eq_attr "type" "mfc,mtc"))
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528 "r24kf1_1_fpu_iss")
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529
|
|
|
530 ;; --------------------------------------------------------------
|
|
|
531 ;; Bypass to Consumer
|
|
|
532 ;; --------------------------------------------------------------
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|
|
533 ;; r24kf1_1_fcvt_f2i->l/s base : 6 cycles
|
|
|
534 ;; r24kf1_1_fcvt_f2i->prefetch : 6 cycles
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|
|
535 (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_load")
|
|
111
|
536 (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_store"
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|
|
537 "!mips_store_data_bypass_p")
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0
|
538 (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_prefetch")
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|
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539
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|
|
540 ;; r24kf1_1_fxfer->l/s base : 3 cycles
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|
|
541 ;; r24kf1_1_fxfer->prefetch : 3 cycles
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|
542 (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_load")
|
|
111
|
543 (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_store" "!mips_store_data_bypass_p")
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0
|
544 (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_prefetch")
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|
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545
|
