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comparison gcc/config/mips/4k.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents a06113de4d67
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
8 ;; 8 ;;
9 ;; 4Kc - pipelined multiplier and translation lookaside buffer (TLB) 9 ;; 4Kc - pipelined multiplier and translation lookaside buffer (TLB)
10 ;; 4km - pipelined multiplier and block address translator (BAT) 10 ;; 4km - pipelined multiplier and block address translator (BAT)
11 ;; 4kp - non-pipelined multiplier and block address translator (BAT) 11 ;; 4kp - non-pipelined multiplier and block address translator (BAT)
12 ;; 12 ;;
13 ;; Copyright (C) 2005, 2007 Free Software Foundation, Inc. 13 ;; Copyright (C) 2005-2017 Free Software Foundation, Inc.
14 ;; 14 ;;
15 ;; This file is part of GCC. 15 ;; This file is part of GCC.
16 ;; 16 ;;
17 ;; GCC is free software; you can redistribute it and/or modify it 17 ;; GCC is free software; you can redistribute it and/or modify it
18 ;; under the terms of the GNU General Public License as published 18 ;; under the terms of the GNU General Public License as published
112 "r4k_ixu_arith+(r4k_ixu_mpydiv*34)") 112 "r4k_ixu_arith+(r4k_ixu_mpydiv*34)")
113 113
114 ;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency. 114 ;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
115 (define_insn_reservation "r4k_int_mthilo" 1 115 (define_insn_reservation "r4k_int_mthilo" 1
116 (and (eq_attr "cpu" "4kc,4kp") 116 (and (eq_attr "cpu" "4kc,4kp")
117 (eq_attr "type" "mthilo")) 117 (eq_attr "type" "mthi,mtlo"))
118 "r4k_ixu_arith+r4k_ixu_mpydiv") 118 "r4k_ixu_arith+r4k_ixu_mpydiv")
119 119
120 ;; Move from HI/LO -> integer operation has a 2 cycle latency. 120 ;; Move from HI/LO -> integer operation has a 2 cycle latency.
121 (define_insn_reservation "r4k_int_mfhilo" 2 121 (define_insn_reservation "r4k_int_mfhilo" 2
122 (and (eq_attr "cpu" "4kc,4kp") 122 (and (eq_attr "cpu" "4kc,4kp")
123 (eq_attr "type" "mfhilo")) 123 (eq_attr "type" "mfhi,mflo"))
124 "r4k_ixu_arith+r4k_ixu_mpydiv") 124 "r4k_ixu_arith+r4k_ixu_mpydiv")
125 125
126 ;; All other integer insns. 126 ;; All other integer insns.
127 (define_insn_reservation "r4k_int_alu" 1 127 (define_insn_reservation "r4k_int_alu" 1
128 (and (eq_attr "cpu" "4kc,4kp") 128 (and (eq_attr "cpu" "4kc,4kp")
147 ;; "r4k_ixu_arith") 147 ;; "r4k_ixu_arith")
148 148
149 ;; Unknown or multi - single issue 149 ;; Unknown or multi - single issue
150 (define_insn_reservation "r4k_unknown" 1 150 (define_insn_reservation "r4k_unknown" 1
151 (and (eq_attr "cpu" "4kc,4kp") 151 (and (eq_attr "cpu" "4kc,4kp")
152 (eq_attr "type" "unknown,multi")) 152 (eq_attr "type" "unknown,multi,atomic,syncloop"))
153 "r4k_ixu_arith+r4k_ixu_mpydiv") 153 "r4k_ixu_arith+r4k_ixu_mpydiv")