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1 ;; DFA-based pipeline descriptions for MIPS32 4K processor family
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2 ;; Contributed by Nigel Stephens (nigel@mips.com)
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3 ;; and David Ung (davidu@mips.com)
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4 ;;
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5 ;; References:
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6 ;; "MIPS32 4K Processor Core Family Software User's Manual,
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7 ;; Doc no: MD00016, Rev 1.18, Nov 15, 2004."
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8 ;;
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9 ;; 4Kc - pipelined multiplier and translation lookaside buffer (TLB)
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10 ;; 4km - pipelined multiplier and block address translator (BAT)
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11 ;; 4kp - non-pipelined multiplier and block address translator (BAT)
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12 ;;
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111
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13 ;; Copyright (C) 2005-2017 Free Software Foundation, Inc.
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14 ;;
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15 ;; This file is part of GCC.
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16 ;;
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17 ;; GCC is free software; you can redistribute it and/or modify it
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18 ;; under the terms of the GNU General Public License as published
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19 ;; by the Free Software Foundation; either version 3, or (at your
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20 ;; option) any later version.
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21
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22 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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23 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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24 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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25 ;; License for more details.
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26
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27 ;; You should have received a copy of the GNU General Public License
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28 ;; along with GCC; see the file COPYING3. If not see
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29 ;; <http://www.gnu.org/licenses/>.
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30
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31 (define_automaton "r4k_cpu, r4k_mdu")
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32
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33 ;; Integer execution unit.
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34 (define_cpu_unit "r4k_ixu_arith" "r4k_cpu")
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35 (define_cpu_unit "r4k_ixu_mpydiv" "r4k_mdu")
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36
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37 (define_insn_reservation "r4k_int_load" 2
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38 (and (eq_attr "cpu" "4kc,4kp")
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39 (eq_attr "type" "load"))
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40 "r4k_ixu_arith")
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41
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42 (define_insn_reservation "r4k_int_prefetch" 1
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43 (and (eq_attr "cpu" "4kc,4kp")
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44 (eq_attr "type" "prefetch"))
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45 "r4k_ixu_arith")
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46
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47 (define_insn_reservation "r4k_int_store" 1
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48 (and (eq_attr "cpu" "4kc,4kp")
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49 (eq_attr "type" "store"))
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50 "r4k_ixu_arith")
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51
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52 ;; 4Kc/4Km
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53 ;; unsigned divide - 8/16/24/32-bit operand have latencies 9/17/25/33
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54 ;; signed divide - 8/16/24/32-bit operand have latencies 10/18/26/34
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55 (define_insn_reservation "r4k_idiv_4kc" 34
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56 (and (eq_attr "cpu" "4kc")
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57 (and (eq_attr "type" "idiv")
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58 (eq_attr "mode" "!DI")))
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59 "r4k_ixu_arith+(r4k_ixu_mpydiv*34)")
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60
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61 ;; 4Kp
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62 ;; unsigned divide - 33
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63 ;; signed divide - 33-35
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64 (define_insn_reservation "r4k_idiv_4kp" 35
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65 (and (eq_attr "cpu" "4kp")
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66 (and (eq_attr "type" "idiv")
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67 (eq_attr "mode" "!DI")))
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68 "r4k_ixu_arith+(r4k_ixu_mpydiv*35)")
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69
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70 ;; 4Kc/4Km fast 32x32 multiply
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71 ;; 16x32 is faster, but there's no way to detect this
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72 (define_insn_reservation "r4k_mult_4kc" 2
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73 (and (eq_attr "cpu" "4kc")
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74 (and (eq_attr "type" "imul,imadd")
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75 (eq_attr "mode" "SI")))
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76 "r4k_ixu_arith+(r4k_ixu_mpydiv*2)")
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77
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78 ;; 4Kc/4Km MUL has 2 cycle latency, but has the special property that it will
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79 ;; stall the integer unit pipeline. MUL 16x16 or 32x16 forces 1 cycle stall,
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80 ;; while MUL 32x32 forces 2 cycle stall. If next insn use the result, an
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81 ;; additional stall is forced.
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82 (define_insn_reservation "r4k_mul_4kc" 4
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83 (and (eq_attr "cpu" "4kc")
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84 (and (eq_attr "type" "imul3")
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85 (eq_attr "mode" "SI")))
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86 "(r4k_ixu_arith+r4k_ixu_mpydiv)*3")
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87
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88 ;; 4Kp slow iterative 2-op MULT
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89 ;; Latency of 32 if next insn is MADD/MSUB,MFHI/MFLO.
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90 ;; Repeat rate of 33 cycles.
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91 (define_insn_reservation "r4k_mult_4kp" 32
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92 (and (eq_attr "cpu" "4kp")
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93 (and (eq_attr "type" "imul")
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94 (eq_attr "mode" "SI")))
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95 "r4k_ixu_arith+(r4k_ixu_mpydiv*32)")
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96
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97 ;; 4Kp slow iterative 3-op MUL
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98 ;; Latency of 32 cycles, but stalls the whole pipeline until complete.
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99 (define_insn_reservation "r4k_mul_4kp" 32
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100 (and (eq_attr "cpu" "4kp")
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101 (and (eq_attr "type" "imul3")
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102 (eq_attr "mode" "SI")))
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103 "(r4k_ixu_arith+r4k_ixu_mpydiv)*32")
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104
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105 ;; 4Kp slow iterative MADD
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106 ;; Latency of 34 if next use insn is MADD/MSUB,MFHI/MFLO.
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107 ;; Repeat rate of 35 cycles.
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108 (define_insn_reservation "r4k_madd_4kp" 34
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109 (and (eq_attr "cpu" "4kp")
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110 (and (eq_attr "type" "imadd")
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111 (eq_attr "mode" "SI")))
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112 "r4k_ixu_arith+(r4k_ixu_mpydiv*34)")
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113
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114 ;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
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115 (define_insn_reservation "r4k_int_mthilo" 1
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116 (and (eq_attr "cpu" "4kc,4kp")
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117 (eq_attr "type" "mthi,mtlo"))
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118 "r4k_ixu_arith+r4k_ixu_mpydiv")
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119
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120 ;; Move from HI/LO -> integer operation has a 2 cycle latency.
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121 (define_insn_reservation "r4k_int_mfhilo" 2
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122 (and (eq_attr "cpu" "4kc,4kp")
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123 (eq_attr "type" "mfhi,mflo"))
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124 "r4k_ixu_arith+r4k_ixu_mpydiv")
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125
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126 ;; All other integer insns.
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127 (define_insn_reservation "r4k_int_alu" 1
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128 (and (eq_attr "cpu" "4kc,4kp")
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129 (eq_attr "type" "arith,condmove,const,logical,move,nop,shift,signext,slt"))
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130 "r4k_ixu_arith")
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131
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132 (define_insn_reservation "r4k_int_branch" 1
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133 (and (eq_attr "cpu" "4kc,4kp")
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134 (eq_attr "type" "branch"))
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135 "r4k_ixu_arith")
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136
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137 (define_insn_reservation "r4k_int_jump_4k" 1
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138 (and (eq_attr "cpu" "4kc,4kp")
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139 (eq_attr "type" "jump,call"))
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140 "r4k_ixu_arith")
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141
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142 ;; mfcx/mtcx - non FPU
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143 ;; (Disabled until we add cop0 support)
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144 ;; (define_insn_reservation "r4k_int_cop" 2
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145 ;; (and (eq_attr "cpu" "4kc,4kp")
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146 ;; (eq_attr "type" "cop0"))
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147 ;; "r4k_ixu_arith")
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148
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149 ;; Unknown or multi - single issue
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150 (define_insn_reservation "r4k_unknown" 1
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151 (and (eq_attr "cpu" "4kc,4kp")
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152 (eq_attr "type" "unknown,multi,atomic,syncloop"))
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153 "r4k_ixu_arith+r4k_ixu_mpydiv")
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