--- a/gcc/config/mips/4k.md	Sun Aug 21 07:07:55 2011 +0900
+++ b/gcc/config/mips/4k.md	Fri Oct 27 22:46:09 2017 +0900
@@ -10,7 +10,7 @@
 ;; 4km - pipelined multiplier and block address translator (BAT)
 ;; 4kp - non-pipelined multiplier and block address translator (BAT)
 ;;
-;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
+;; Copyright (C) 2005-2017 Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
 ;;
@@ -114,13 +114,13 @@
 ;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
 (define_insn_reservation "r4k_int_mthilo" 1
   (and (eq_attr "cpu" "4kc,4kp")
-       (eq_attr "type" "mthilo"))
+       (eq_attr "type" "mthi,mtlo"))
   "r4k_ixu_arith+r4k_ixu_mpydiv")
 
 ;; Move from HI/LO -> integer operation has a 2 cycle latency.
 (define_insn_reservation "r4k_int_mfhilo" 2
   (and (eq_attr "cpu" "4kc,4kp")
-       (eq_attr "type" "mfhilo"))
+       (eq_attr "type" "mfhi,mflo"))
   "r4k_ixu_arith+r4k_ixu_mpydiv")
 
 ;; All other integer insns.
@@ -149,5 +149,5 @@
 ;; Unknown or multi - single issue
 (define_insn_reservation "r4k_unknown" 1
   (and (eq_attr "cpu" "4kc,4kp")
-       (eq_attr "type" "unknown,multi"))
+       (eq_attr "type" "unknown,multi,atomic,syncloop"))
   "r4k_ixu_arith+r4k_ixu_mpydiv")