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comparison gcc/common/config/i386/i386-common.c @ 145:1830386684a0

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gcc-9.2.0
author anatofuz
date Thu, 13 Feb 2020 11:34:05 +0900
parents 84e7813d76e9
children
comparison
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131:84e7813d76e9 145:1830386684a0
1 /* IA-32 common hooks. 1 /* IA-32 common hooks.
2 Copyright (C) 1988-2018 Free Software Foundation, Inc. 2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
3 3
4 This file is part of GCC. 4 This file is part of GCC.
5 5
6 GCC is free software; you can redistribute it and/or modify 6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by 7 it under the terms of the GNU General Public License as published by
76 (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET) 76 (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
77 #define OPTION_MASK_ISA_AVX512IFMA_SET \ 77 #define OPTION_MASK_ISA_AVX512IFMA_SET \
78 (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET) 78 (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
79 #define OPTION_MASK_ISA_AVX512VBMI_SET \ 79 #define OPTION_MASK_ISA_AVX512VBMI_SET \
80 (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET) 80 (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
81 #define OPTION_MASK_ISA_AVX5124FMAPS_SET OPTION_MASK_ISA_AVX5124FMAPS 81 #define OPTION_MASK_ISA2_AVX5124FMAPS_SET OPTION_MASK_ISA2_AVX5124FMAPS
82 #define OPTION_MASK_ISA_AVX5124VNNIW_SET OPTION_MASK_ISA_AVX5124VNNIW 82 #define OPTION_MASK_ISA2_AVX5124VNNIW_SET OPTION_MASK_ISA2_AVX5124VNNIW
83 #define OPTION_MASK_ISA_AVX512VBMI2_SET \ 83 #define OPTION_MASK_ISA_AVX512VBMI2_SET \
84 (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET) 84 (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET)
85 #define OPTION_MASK_ISA_AVX512VNNI_SET \ 85 #define OPTION_MASK_ISA_AVX512VNNI_SET \
86 (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET) 86 (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
87 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \ 87 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
88 (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET) 88 (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
89 #define OPTION_MASK_ISA_AVX512BITALG_SET \ 89 #define OPTION_MASK_ISA_AVX512BITALG_SET \
90 (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET) 90 (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET)
91 #define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16
91 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM 92 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
92 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW 93 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
93 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED 94 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
94 #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX 95 #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
95 #define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1 96 #define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1
97 #define OPTION_MASK_ISA_XSAVES_SET \ 98 #define OPTION_MASK_ISA_XSAVES_SET \
98 (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET) 99 (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET)
99 #define OPTION_MASK_ISA_XSAVEC_SET \ 100 #define OPTION_MASK_ISA_XSAVEC_SET \
100 (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET) 101 (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
101 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB 102 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
103 #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT
102 104
103 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same 105 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
104 as -msse4.2. */ 106 as -msse4.2. */
105 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET 107 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
106 108
123 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET) 125 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
124 126
125 #define OPTION_MASK_ISA_ABM_SET \ 127 #define OPTION_MASK_ISA_ABM_SET \
126 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT) 128 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
127 129
128 #define OPTION_MASK_ISA_PCONFIG_SET OPTION_MASK_ISA_PCONFIG 130 #define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG
129 #define OPTION_MASK_ISA_WBNOINVD_SET OPTION_MASK_ISA_WBNOINVD 131 #define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD
130 #define OPTION_MASK_ISA_SGX_SET OPTION_MASK_ISA_SGX 132 #define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX
131 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI 133 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
132 #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2 134 #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
133 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT 135 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
134 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM 136 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
135 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT 137 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
136 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16 138 #define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16
137 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF 139 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
138 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE 140 #define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE
139 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32 141 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
140 142
141 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE 143 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
142 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND 144 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
145 #define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE
143 #define OPTION_MASK_ISA_F16C_SET \ 146 #define OPTION_MASK_ISA_F16C_SET \
144 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET) 147 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
145 #define OPTION_MASK_ISA_MWAITX_SET OPTION_MASK_ISA_MWAITX 148 #define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX
146 #define OPTION_MASK_ISA_CLZERO_SET OPTION_MASK_ISA_CLZERO 149 #define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO
147 #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU 150 #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
148 #define OPTION_MASK_ISA_RDPID_SET OPTION_MASK_ISA_RDPID 151 #define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID
149 #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI 152 #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
150 #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK 153 #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
151 #define OPTION_MASK_ISA_VAES_SET OPTION_MASK_ISA_VAES 154 #define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES
152 #define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ 155 #define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ
153 #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI 156 #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
154 #define OPTION_MASK_ISA_MOVDIR64B_SET OPTION_MASK_ISA_MOVDIR64B 157 #define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B
155 #define OPTION_MASK_ISA_WAITPKG_SET OPTION_MASK_ISA_WAITPKG 158 #define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG
156 #define OPTION_MASK_ISA_CLDEMOTE_SET OPTION_MASK_ISA_CLDEMOTE 159 #define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE
160 #define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
157 161
158 /* Define a set of ISAs which aren't available when a given ISA is 162 /* Define a set of ISAs which aren't available when a given ISA is
159 disabled. MMX and SSE ISAs are handled separately. */ 163 disabled. MMX and SSE ISAs are handled separately. */
160 164
161 #define OPTION_MASK_ISA_MMX_UNSET \ 165 #define OPTION_MASK_ISA_MMX_UNSET \
206 #define OPTION_MASK_ISA_AVX512BW_UNSET \ 210 #define OPTION_MASK_ISA_AVX512BW_UNSET \
207 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET) 211 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET)
208 #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL 212 #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
209 #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA 213 #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
210 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI 214 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
211 #define OPTION_MASK_ISA_AVX5124FMAPS_UNSET OPTION_MASK_ISA_AVX5124FMAPS 215 #define OPTION_MASK_ISA2_AVX5124FMAPS_UNSET OPTION_MASK_ISA2_AVX5124FMAPS
212 #define OPTION_MASK_ISA_AVX5124VNNIW_UNSET OPTION_MASK_ISA_AVX5124VNNIW 216 #define OPTION_MASK_ISA2_AVX5124VNNIW_UNSET OPTION_MASK_ISA2_AVX5124VNNIW
213 #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2 217 #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
214 #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI 218 #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
215 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ 219 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
216 #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG 220 #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
221 #define OPTION_MASK_ISA2_AVX512BF16_UNSET OPTION_MASK_ISA2_AVX512BF16
217 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM 222 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
218 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW 223 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
219 #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED 224 #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
220 #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX 225 #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
221 #define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1 226 #define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1
222 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT 227 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
223 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC 228 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
224 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES 229 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
225 #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB 230 #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
226 #define OPTION_MASK_ISA_MWAITX_UNSET OPTION_MASK_ISA_MWAITX 231 #define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX
227 #define OPTION_MASK_ISA_CLZERO_UNSET OPTION_MASK_ISA_CLZERO 232 #define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO
228 #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU 233 #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
229 #define OPTION_MASK_ISA_RDPID_UNSET OPTION_MASK_ISA_RDPID 234 #define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID
230 #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI 235 #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
231 #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK 236 #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
232 #define OPTION_MASK_ISA_VAES_UNSET OPTION_MASK_ISA_VAES 237 #define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES
233 #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ 238 #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
234 #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI 239 #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
235 #define OPTION_MASK_ISA_MOVDIR64B_UNSET OPTION_MASK_ISA_MOVDIR64B 240 #define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B
236 #define OPTION_MASK_ISA_WAITPKG_UNSET OPTION_MASK_ISA_WAITPKG 241 #define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG
237 #define OPTION_MASK_ISA_CLDEMOTE_UNSET OPTION_MASK_ISA_CLDEMOTE 242 #define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE
243 #define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD
244 #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT
238 245
239 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same 246 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
240 as -mno-sse4.1. */ 247 as -mno-sse4.1. */
241 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET 248 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
242 249
250 257
251 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES 258 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
252 #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA 259 #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
253 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL 260 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
254 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM 261 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
255 #define OPTION_MASK_ISA_PCONFIG_UNSET OPTION_MASK_ISA_PCONFIG 262 #define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG
256 #define OPTION_MASK_ISA_WBNOINVD_UNSET OPTION_MASK_ISA_WBNOINVD 263 #define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD
257 #define OPTION_MASK_ISA_SGX_UNSET OPTION_MASK_ISA_SGX 264 #define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX
258 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI 265 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
259 #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2 266 #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
260 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT 267 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
261 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM 268 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
262 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT 269 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
263 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16 270 #define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16
264 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF 271 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
265 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE 272 #define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE
266 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32 273 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
267 274
268 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE 275 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
269 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND 276 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
277 #define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE
270 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C 278 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
271 279
272 #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \ 280 #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
273 (OPTION_MASK_ISA_MMX_UNSET \ 281 (OPTION_MASK_ISA_MMX_UNSET \
274 | OPTION_MASK_ISA_SSE_UNSET) 282 | OPTION_MASK_ISA_SSE_UNSET)
275 283
276 #define OPTION_MASK_ISA2_AVX512F_UNSET \ 284 #define OPTION_MASK_ISA2_AVX512F_UNSET \
277 (OPTION_MASK_ISA_AVX5124FMAPS_UNSET | OPTION_MASK_ISA_AVX5124VNNIW_UNSET) 285 (OPTION_MASK_ISA2_AVX512BF16_UNSET \
286 | OPTION_MASK_ISA2_AVX5124FMAPS_UNSET \
287 | OPTION_MASK_ISA2_AVX5124VNNIW_UNSET \
288 | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET)
278 #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ 289 #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
279 (OPTION_MASK_ISA2_AVX512F_UNSET) 290 (OPTION_MASK_ISA2_AVX512F_UNSET)
291
292 #define OPTION_MASK_ISA2_AVX512BW_UNSET OPTION_MASK_ISA2_AVX512BF16_UNSET
280 293
281 /* Set 1 << value as value of -malign-FLAG option. */ 294 /* Set 1 << value as value of -malign-FLAG option. */
282 295
283 static void 296 static void
284 set_malign_value (const char **flag, unsigned value) 297 set_malign_value (const char **flag, unsigned value)
535 return true; 548 return true;
536 549
537 case OPT_mrdpid: 550 case OPT_mrdpid:
538 if (value) 551 if (value)
539 { 552 {
540 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID_SET; 553 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RDPID_SET;
541 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_SET; 554 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_SET;
542 } 555 }
543 else 556 else
544 { 557 {
545 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_RDPID_UNSET; 558 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RDPID_UNSET;
546 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_UNSET; 559 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_UNSET;
547 } 560 }
548 return true; 561 return true;
549 562
550 case OPT_mgfni: 563 case OPT_mgfni:
551 if (value) 564 if (value)
574 return true; 587 return true;
575 588
576 case OPT_mvaes: 589 case OPT_mvaes:
577 if (value) 590 if (value)
578 { 591 {
579 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_VAES_SET; 592 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_VAES_SET;
580 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_SET; 593 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_SET;
581 } 594 }
582 else 595 else
583 { 596 {
584 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_VAES_UNSET; 597 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_VAES_UNSET;
585 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_UNSET; 598 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_UNSET;
586 } 599 }
587 return true; 600 return true;
588 601
589 case OPT_mvpclmulqdq: 602 case OPT_mvpclmulqdq:
590 if (value) 603 if (value)
613 return true; 626 return true;
614 627
615 case OPT_mmovdir64b: 628 case OPT_mmovdir64b:
616 if (value) 629 if (value)
617 { 630 {
618 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVDIR64B_SET; 631 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVDIR64B_SET;
619 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_SET; 632 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_SET;
620 } 633 }
621 else 634 else
622 { 635 {
623 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVDIR64B_UNSET; 636 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVDIR64B_UNSET;
624 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_UNSET; 637 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_UNSET;
625 } 638 }
626 return true; 639 return true;
627 640
628 case OPT_mcldemote: 641 case OPT_mcldemote:
629 if (value) 642 if (value)
630 { 643 {
631 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLDEMOTE_SET; 644 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLDEMOTE_SET;
632 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLDEMOTE_SET; 645 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_SET;
633 } 646 }
634 else 647 else
635 { 648 {
636 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CLDEMOTE_UNSET; 649 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLDEMOTE_UNSET;
637 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLDEMOTE_UNSET; 650 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_UNSET;
638 } 651 }
639 return true; 652 return true;
640 653
641 case OPT_mwaitpkg: 654 case OPT_mwaitpkg:
642 if (value) 655 if (value)
643 { 656 {
644 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WAITPKG_SET; 657 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WAITPKG_SET;
645 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WAITPKG_SET; 658 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_SET;
646 } 659 }
647 else 660 else
648 { 661 {
649 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_WAITPKG_UNSET; 662 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WAITPKG_UNSET;
650 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WAITPKG_UNSET; 663 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_UNSET;
664 }
665 return true;
666
667 case OPT_menqcmd:
668 if (value)
669 {
670 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_ENQCMD_SET;
671 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_SET;
672 }
673 else
674 {
675 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_ENQCMD_UNSET;
676 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_UNSET;
651 } 677 }
652 return true; 678 return true;
653 679
654 case OPT_mavx5124fmaps: 680 case OPT_mavx5124fmaps:
655 if (value) 681 if (value)
656 { 682 {
657 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS_SET; 683 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124FMAPS_SET;
658 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_SET; 684 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124FMAPS_SET;
659 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; 685 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
660 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; 686 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
661 } 687 }
662 else 688 else
663 { 689 {
664 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124FMAPS_UNSET; 690 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX5124FMAPS_UNSET;
665 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_UNSET; 691 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124FMAPS_UNSET;
666 } 692 }
667 return true; 693 return true;
668 694
669 case OPT_mavx5124vnniw: 695 case OPT_mavx5124vnniw:
670 if (value) 696 if (value)
671 { 697 {
672 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124VNNIW_SET; 698 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124VNNIW_SET;
673 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_SET; 699 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124VNNIW_SET;
674 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; 700 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
675 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; 701 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
676 } 702 }
677 else 703 else
678 { 704 {
679 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124VNNIW_UNSET; 705 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX5124VNNIW_UNSET;
680 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_UNSET; 706 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124VNNIW_UNSET;
681 } 707 }
682 return true; 708 return true;
683 709
684 case OPT_mavx512vbmi2: 710 case OPT_mavx512vbmi2:
685 if (value) 711 if (value)
734 opts->x_ix86_isa_flags_explicit 760 opts->x_ix86_isa_flags_explicit
735 |= OPTION_MASK_ISA_AVX512BITALG_UNSET; 761 |= OPTION_MASK_ISA_AVX512BITALG_UNSET;
736 } 762 }
737 return true; 763 return true;
738 764
765 case OPT_mavx512bf16:
766 if (value)
767 {
768 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BF16_SET;
769 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_SET;
770 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
771 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
772 }
773 else
774 {
775 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET;
776 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET;
777 }
778 return true;
779
739 case OPT_msgx: 780 case OPT_msgx:
740 if (value) 781 if (value)
741 { 782 {
742 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX_SET; 783 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SGX_SET;
743 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_SET; 784 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_SET;
744 } 785 }
745 else 786 else
746 { 787 {
747 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_SGX_UNSET; 788 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SGX_UNSET;
748 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_UNSET; 789 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_UNSET;
749 } 790 }
750 return true; 791 return true;
751 792
752 case OPT_mpconfig: 793 case OPT_mpconfig:
753 if (value) 794 if (value)
754 { 795 {
755 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PCONFIG_SET; 796 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PCONFIG_SET;
756 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_SET; 797 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_SET;
757 } 798 }
758 else 799 else
759 { 800 {
760 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_PCONFIG_UNSET; 801 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PCONFIG_UNSET;
761 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_UNSET; 802 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_UNSET;
762 } 803 }
763 return true; 804 return true;
764 805
765 case OPT_mwbnoinvd: 806 case OPT_mwbnoinvd:
766 if (value) 807 if (value)
767 { 808 {
768 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WBNOINVD_SET; 809 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WBNOINVD_SET;
769 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_SET; 810 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_SET;
770 } 811 }
771 else 812 else
772 { 813 {
773 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_WBNOINVD_UNSET; 814 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WBNOINVD_UNSET;
774 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_UNSET; 815 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_UNSET;
775 } 816 }
776 return true; 817 return true;
777 818
778 case OPT_mavx512dq: 819 case OPT_mavx512dq:
779 if (value) 820 if (value)
796 } 837 }
797 else 838 else
798 { 839 {
799 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET; 840 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET;
800 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET; 841 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
842 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET;
843 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET;
801 } 844 }
802 return true; 845 return true;
803 846
804 case OPT_mavx512vl: 847 case OPT_mavx512vl:
805 if (value) 848 if (value)
835 } 878 }
836 else 879 else
837 { 880 {
838 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET; 881 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
839 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET; 882 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
883 }
884 return true;
885
886 case OPT_mavx512vp2intersect:
887 if (value)
888 {
889 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
890 opts->x_ix86_isa_flags2_explicit |=
891 OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
892 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
893 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
894 }
895 else
896 {
897 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
898 opts->x_ix86_isa_flags2_explicit |=
899 OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
840 } 900 }
841 return true; 901 return true;
842 902
843 case OPT_mfma: 903 case OPT_mfma:
844 if (value) 904 if (value)
1022 return true; 1082 return true;
1023 1083
1024 case OPT_mcx16: 1084 case OPT_mcx16:
1025 if (value) 1085 if (value)
1026 { 1086 {
1027 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CX16_SET; 1087 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CX16_SET;
1028 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_SET; 1088 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_SET;
1029 } 1089 }
1030 else 1090 else
1031 { 1091 {
1032 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CX16_UNSET; 1092 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CX16_UNSET;
1033 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_UNSET; 1093 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_UNSET;
1034 } 1094 }
1035 return true; 1095 return true;
1036 1096
1037 case OPT_mmovbe: 1097 case OPT_mmovbe:
1038 if (value) 1098 if (value)
1039 { 1099 {
1040 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVBE_SET; 1100 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVBE_SET;
1041 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_SET; 1101 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_SET;
1042 } 1102 }
1043 else 1103 else
1044 { 1104 {
1045 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVBE_UNSET; 1105 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVBE_UNSET;
1046 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_UNSET; 1106 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_UNSET;
1047 } 1107 }
1048 return true; 1108 return true;
1049 1109
1050 case OPT_mcrc32: 1110 case OPT_mcrc32:
1051 if (value) 1111 if (value)
1123 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET; 1183 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
1124 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET; 1184 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
1125 } 1185 }
1126 return true; 1186 return true;
1127 1187
1188 case OPT_mptwrite:
1189 if (value)
1190 {
1191 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PTWRITE_SET;
1192 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_SET;
1193 }
1194 else
1195 {
1196 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PTWRITE_UNSET;
1197 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_UNSET;
1198 }
1199 return true;
1200
1128 case OPT_mf16c: 1201 case OPT_mf16c:
1129 if (value) 1202 if (value)
1130 { 1203 {
1131 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET; 1204 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
1132 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET; 1205 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
1282 return true; 1355 return true;
1283 1356
1284 case OPT_mmwaitx: 1357 case OPT_mmwaitx:
1285 if (value) 1358 if (value)
1286 { 1359 {
1287 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MWAITX_SET; 1360 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAITX_SET;
1288 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_SET; 1361 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_SET;
1289 } 1362 }
1290 else 1363 else
1291 { 1364 {
1292 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MWAITX_UNSET; 1365 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAITX_UNSET;
1293 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_UNSET; 1366 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_UNSET;
1294 } 1367 }
1295 return true; 1368 return true;
1296 1369
1297 case OPT_mclzero: 1370 case OPT_mclzero:
1298 if (value) 1371 if (value)
1299 { 1372 {
1300 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLZERO_SET; 1373 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLZERO_SET;
1301 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_SET; 1374 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_SET;
1302 } 1375 }
1303 else 1376 else
1304 { 1377 {
1305 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CLZERO_UNSET; 1378 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLZERO_UNSET;
1306 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_UNSET; 1379 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_UNSET;
1307 } 1380 }
1308 return true; 1381 return true;
1309 1382
1310 case OPT_mpku: 1383 case OPT_mpku:
1311 if (value) 1384 if (value)
1320 } 1393 }
1321 return true; 1394 return true;
1322 1395
1323 1396
1324 case OPT_malign_loops_: 1397 case OPT_malign_loops_:
1325 warning_at (loc, 0, "-malign-loops is obsolete, use -falign-loops"); 1398 warning_at (loc, 0, "%<-malign-loops%> is obsolete, "
1399 "use %<-falign-loops%>");
1326 if (value > MAX_CODE_ALIGN) 1400 if (value > MAX_CODE_ALIGN)
1327 error_at (loc, "-malign-loops=%d is not between 0 and %d", 1401 error_at (loc, "%<-malign-loops=%d%> is not between 0 and %d",
1328 value, MAX_CODE_ALIGN); 1402 value, MAX_CODE_ALIGN);
1329 else 1403 else
1330 set_malign_value (&opts->x_str_align_loops, value); 1404 set_malign_value (&opts->x_str_align_loops, value);
1331 return true; 1405 return true;
1332 1406
1333 case OPT_malign_jumps_: 1407 case OPT_malign_jumps_:
1334 warning_at (loc, 0, "-malign-jumps is obsolete, use -falign-jumps"); 1408 warning_at (loc, 0, "%<-malign-jumps%> is obsolete, "
1409 "use %<-falign-jumps%>");
1335 if (value > MAX_CODE_ALIGN) 1410 if (value > MAX_CODE_ALIGN)
1336 error_at (loc, "-malign-jumps=%d is not between 0 and %d", 1411 error_at (loc, "%<-malign-jumps=%d%> is not between 0 and %d",
1337 value, MAX_CODE_ALIGN); 1412 value, MAX_CODE_ALIGN);
1338 else 1413 else
1339 set_malign_value (&opts->x_str_align_jumps, value); 1414 set_malign_value (&opts->x_str_align_jumps, value);
1340 return true; 1415 return true;
1341 1416
1342 case OPT_malign_functions_: 1417 case OPT_malign_functions_:
1343 warning_at (loc, 0, 1418 warning_at (loc, 0,
1344 "-malign-functions is obsolete, use -falign-functions"); 1419 "%<-malign-functions%> is obsolete, "
1420 "use %<-falign-functions%>");
1345 if (value > MAX_CODE_ALIGN) 1421 if (value > MAX_CODE_ALIGN)
1346 error_at (loc, "-malign-functions=%d is not between 0 and %d", 1422 error_at (loc, "%<-malign-functions=%d%> is not between 0 and %d",
1347 value, MAX_CODE_ALIGN); 1423 value, MAX_CODE_ALIGN);
1348 else 1424 else
1349 set_malign_value (&opts->x_str_align_functions, value); 1425 set_malign_value (&opts->x_str_align_functions, value);
1350 return true; 1426 return true;
1351 1427
1352 case OPT_mbranch_cost_: 1428 case OPT_mbranch_cost_:
1353 if (value > 5) 1429 if (value > 5)
1354 { 1430 {
1355 error_at (loc, "-mbranch-cost=%d is not between 0 and 5", value); 1431 error_at (loc, "%<-mbranch-cost=%d%> is not between 0 and 5", value);
1356 opts->x_ix86_branch_cost = 5; 1432 opts->x_ix86_branch_cost = 5;
1357 } 1433 }
1358 return true; 1434 return true;
1359 1435
1360 default: 1436 default:
1394 opts->x_flag_pcc_struct_return = 2; 1470 opts->x_flag_pcc_struct_return = 2;
1395 opts->x_flag_asynchronous_unwind_tables = 2; 1471 opts->x_flag_asynchronous_unwind_tables = 2;
1396 } 1472 }
1397 1473
1398 /* On the x86 -fsplit-stack and -fstack-protector both use the same 1474 /* On the x86 -fsplit-stack and -fstack-protector both use the same
1399 field in the TCB, so they can not be used together. */ 1475 field in the TCB, so they cannot be used together. */
1400 1476
1401 static bool 1477 static bool
1402 ix86_supports_split_stack (bool report ATTRIBUTE_UNUSED, 1478 ix86_supports_split_stack (bool report ATTRIBUTE_UNUSED,
1403 struct gcc_options *opts ATTRIBUTE_UNUSED) 1479 struct gcc_options *opts ATTRIBUTE_UNUSED)
1404 { 1480 {
1461 1537
1462 #undef TARGET_SUPPORTS_SPLIT_STACK 1538 #undef TARGET_SUPPORTS_SPLIT_STACK
1463 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack 1539 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
1464 1540
1465 /* This table must be in sync with enum processor_type in i386.h. */ 1541 /* This table must be in sync with enum processor_type in i386.h. */
1466 const char *const processor_names[PROCESSOR_max] = 1542 const char *const processor_names[] =
1467 { 1543 {
1468 "generic", 1544 "generic",
1469 "i386", 1545 "i386",
1470 "i486", 1546 "i486",
1471 "pentium", 1547 "pentium",
1487 "skylake", 1563 "skylake",
1488 "skylake-avx512", 1564 "skylake-avx512",
1489 "cannonlake", 1565 "cannonlake",
1490 "icelake-client", 1566 "icelake-client",
1491 "icelake-server", 1567 "icelake-server",
1568 "cascadelake",
1569 "tigerlake",
1570 "cooperlake",
1492 "intel", 1571 "intel",
1493 "geode", 1572 "geode",
1494 "k6", 1573 "k6",
1495 "athlon", 1574 "athlon",
1496 "k8", 1575 "k8",
1499 "bdver2", 1578 "bdver2",
1500 "bdver3", 1579 "bdver3",
1501 "bdver4", 1580 "bdver4",
1502 "btver1", 1581 "btver1",
1503 "btver2", 1582 "btver2",
1504 "znver1" 1583 "znver1",
1584 "znver2"
1505 }; 1585 };
1586
1587 /* Guarantee that the array is aligned with enum processor_type. */
1588 STATIC_ASSERT (ARRAY_SIZE (processor_names) == PROCESSOR_max);
1506 1589
1507 const pta processor_alias_table[] = 1590 const pta processor_alias_table[] =
1508 { 1591 {
1509 {"i386", PROCESSOR_I386, CPU_NONE, 0}, 1592 {"i386", PROCESSOR_I386, CPU_NONE, 0},
1510 {"i486", PROCESSOR_I486, CPU_NONE, 0}, 1593 {"i486", PROCESSOR_I486, CPU_NONE, 0},
1532 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 1615 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1533 PTA_MMX | PTA_SSE | PTA_FXSR}, 1616 PTA_MMX | PTA_SSE | PTA_FXSR},
1534 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 1617 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1535 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR}, 1618 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
1536 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE, 1619 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
1537 PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR}, 1620 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
1538 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE, 1621 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
1539 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR}, 1622 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
1540 {"prescott", PROCESSOR_NOCONA, CPU_NONE, 1623 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
1541 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR}, 1624 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
1542 {"nocona", PROCESSOR_NOCONA, CPU_NONE, 1625 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
1563 {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE}, 1646 {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
1564 {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL, 1647 {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
1565 PTA_ICELAKE_CLIENT}, 1648 PTA_ICELAKE_CLIENT},
1566 {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL, 1649 {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
1567 PTA_ICELAKE_SERVER}, 1650 PTA_ICELAKE_SERVER},
1651 {"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL,
1652 PTA_CASCADELAKE},
1653 {"tigerlake", PROCESSOR_TIGERLAKE, CPU_HASWELL, PTA_TIGERLAKE},
1654 {"cooperlake", PROCESSOR_COOPERLAKE, CPU_HASWELL, PTA_COOPERLAKE},
1568 {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL}, 1655 {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
1569 {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL}, 1656 {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
1570 {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT}, 1657 {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
1571 {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT}, 1658 {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
1572 {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT}, 1659 {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
1675 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW 1762 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
1676 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE 1763 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
1677 | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED 1764 | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
1678 | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES 1765 | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
1679 | PTA_SHA | PTA_LZCNT | PTA_POPCNT}, 1766 | PTA_SHA | PTA_LZCNT | PTA_POPCNT},
1767 {"znver2", PROCESSOR_ZNVER2, CPU_ZNVER2,
1768 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1769 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1770 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
1771 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
1772 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
1773 | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
1774 | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
1775 | PTA_SHA | PTA_LZCNT | PTA_POPCNT | PTA_CLWB | PTA_RDPID
1776 | PTA_WBNOINVD},
1680 {"btver1", PROCESSOR_BTVER1, CPU_GENERIC, 1777 {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
1681 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 1778 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1682 | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW 1779 | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_PRFCHW
1683 | PTA_FXSR | PTA_XSAVE}, 1780 | PTA_FXSR | PTA_XSAVE},
1684 {"btver2", PROCESSOR_BTVER2, CPU_BTVER2, 1781 {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
1685 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 1782 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1686 | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1 1783 | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_SSE4_1
1687 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX 1784 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
1688 | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW 1785 | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
1689 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT}, 1786 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
1690 1787
1691 {"generic", PROCESSOR_GENERIC, CPU_GENERIC, 1788 {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
1707 1804
1708 switch (opt) 1805 switch (opt)
1709 { 1806 {
1710 case OPT_march_: 1807 case OPT_march_:
1711 for (unsigned i = 0; i < pta_size; i++) 1808 for (unsigned i = 0; i < pta_size; i++)
1712 v.safe_push (processor_alias_table[i].name); 1809 {
1810 const char *name = processor_alias_table[i].name;
1811 gcc_checking_assert (name != NULL);
1812 v.safe_push (name);
1813 }
1814 #ifdef HAVE_LOCAL_CPU_DETECT
1815 /* Add also "native" as possible value. */
1816 v.safe_push ("native");
1817 #endif
1818
1713 break; 1819 break;
1714 case OPT_mtune_: 1820 case OPT_mtune_:
1715 for (unsigned i = 0; i < PROCESSOR_max; i++) 1821 for (unsigned i = 0; i < PROCESSOR_max; i++)
1716 v.safe_push (processor_names[i]); 1822 {
1823 const char *name = processor_names[i];
1824 gcc_checking_assert (name != NULL);
1825 v.safe_push (name);
1826 }
1717 break; 1827 break;
1718 default: 1828 default:
1719 break; 1829 break;
1720 } 1830 }
1721 1831