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111
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1 /* IA-32 common hooks.
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145
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2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
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111
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3
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4 This file is part of GCC.
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5
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6 GCC is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 3, or (at your option)
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9 any later version.
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10
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11 GCC is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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15
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16 You should have received a copy of the GNU General Public License
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17 along with GCC; see the file COPYING3. If not see
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18 <http://www.gnu.org/licenses/>. */
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19
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20 #include "config.h"
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21 #include "system.h"
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22 #include "coretypes.h"
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23 #include "diagnostic-core.h"
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24 #include "tm.h"
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25 #include "memmodel.h"
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26 #include "tm_p.h"
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27 #include "common/common-target.h"
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28 #include "common/common-target-def.h"
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29 #include "opts.h"
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30 #include "flags.h"
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31
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32 /* Define a set of ISAs which are available when a given ISA is
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33 enabled. MMX and SSE ISAs are handled separately. */
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34
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35 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
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36 #define OPTION_MASK_ISA_3DNOW_SET \
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37 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
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38 #define OPTION_MASK_ISA_3DNOW_A_SET \
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39 (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
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40
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41 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
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42 #define OPTION_MASK_ISA_SSE2_SET \
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43 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
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44 #define OPTION_MASK_ISA_SSE3_SET \
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45 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
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46 #define OPTION_MASK_ISA_SSSE3_SET \
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47 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
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48 #define OPTION_MASK_ISA_SSE4_1_SET \
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49 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
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50 #define OPTION_MASK_ISA_SSE4_2_SET \
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51 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
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52 #define OPTION_MASK_ISA_AVX_SET \
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53 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
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54 | OPTION_MASK_ISA_XSAVE_SET)
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55 #define OPTION_MASK_ISA_FMA_SET \
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56 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
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57 #define OPTION_MASK_ISA_AVX2_SET \
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58 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
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59 #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
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60 #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
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61 #define OPTION_MASK_ISA_XSAVEOPT_SET \
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131
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62 (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET)
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111
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63 #define OPTION_MASK_ISA_AVX512F_SET \
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64 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
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65 #define OPTION_MASK_ISA_AVX512CD_SET \
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66 (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
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67 #define OPTION_MASK_ISA_AVX512PF_SET \
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68 (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET)
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69 #define OPTION_MASK_ISA_AVX512ER_SET \
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70 (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET)
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71 #define OPTION_MASK_ISA_AVX512DQ_SET \
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72 (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
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73 #define OPTION_MASK_ISA_AVX512BW_SET \
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74 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
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75 #define OPTION_MASK_ISA_AVX512VL_SET \
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76 (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
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77 #define OPTION_MASK_ISA_AVX512IFMA_SET \
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78 (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
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79 #define OPTION_MASK_ISA_AVX512VBMI_SET \
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80 (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
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145
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81 #define OPTION_MASK_ISA2_AVX5124FMAPS_SET OPTION_MASK_ISA2_AVX5124FMAPS
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82 #define OPTION_MASK_ISA2_AVX5124VNNIW_SET OPTION_MASK_ISA2_AVX5124VNNIW
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131
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83 #define OPTION_MASK_ISA_AVX512VBMI2_SET \
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84 (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET)
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85 #define OPTION_MASK_ISA_AVX512VNNI_SET \
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86 (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
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87 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
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88 (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
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89 #define OPTION_MASK_ISA_AVX512BITALG_SET \
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90 (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET)
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145
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91 #define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16
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111
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92 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
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93 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
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94 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
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95 #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
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96 #define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1
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97 #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
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98 #define OPTION_MASK_ISA_XSAVES_SET \
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131
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99 (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET)
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111
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100 #define OPTION_MASK_ISA_XSAVEC_SET \
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131
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101 (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
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111
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102 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
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145
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103 #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT
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111
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104
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105 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
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106 as -msse4.2. */
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107 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
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108
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109 #define OPTION_MASK_ISA_SSE4A_SET \
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110 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
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111 #define OPTION_MASK_ISA_FMA4_SET \
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112 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
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113 | OPTION_MASK_ISA_AVX_SET)
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114 #define OPTION_MASK_ISA_XOP_SET \
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115 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
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116 #define OPTION_MASK_ISA_LWP_SET \
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117 OPTION_MASK_ISA_LWP
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118
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119 /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
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120 #define OPTION_MASK_ISA_AES_SET \
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121 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
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122 #define OPTION_MASK_ISA_SHA_SET \
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123 (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
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124 #define OPTION_MASK_ISA_PCLMUL_SET \
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125 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
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126
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127 #define OPTION_MASK_ISA_ABM_SET \
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128 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
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129
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145
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130 #define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG
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131 #define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD
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132 #define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX
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111
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133 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
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134 #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
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135 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
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136 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
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137 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
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145
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138 #define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16
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111
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139 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
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145
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140 #define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE
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111
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141 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
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142
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143 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
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144 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
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145
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145 #define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE
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111
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146 #define OPTION_MASK_ISA_F16C_SET \
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147 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
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145
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148 #define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX
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149 #define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO
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111
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150 #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
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145
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151 #define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID
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111
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152 #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
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153 #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
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145
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154 #define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES
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131
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155 #define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ
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156 #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
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145
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157 #define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B
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158 #define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG
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159 #define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE
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160 #define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
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111
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161
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162 /* Define a set of ISAs which aren't available when a given ISA is
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163 disabled. MMX and SSE ISAs are handled separately. */
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164
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165 #define OPTION_MASK_ISA_MMX_UNSET \
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166 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
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167 #define OPTION_MASK_ISA_3DNOW_UNSET \
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168 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
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169 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
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170
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171 #define OPTION_MASK_ISA_SSE_UNSET \
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172 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
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173 #define OPTION_MASK_ISA_SSE2_UNSET \
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174 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
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175 #define OPTION_MASK_ISA_SSE3_UNSET \
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176 (OPTION_MASK_ISA_SSE3 \
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177 | OPTION_MASK_ISA_SSSE3_UNSET \
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178 | OPTION_MASK_ISA_SSE4A_UNSET )
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179 #define OPTION_MASK_ISA_SSSE3_UNSET \
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180 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
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181 #define OPTION_MASK_ISA_SSE4_1_UNSET \
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182 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
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183 #define OPTION_MASK_ISA_SSE4_2_UNSET \
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184 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
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185 #define OPTION_MASK_ISA_AVX_UNSET \
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186 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
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187 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
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188 | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_XSAVE_UNSET)
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189 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
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190 #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
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191 #define OPTION_MASK_ISA_XSAVE_UNSET \
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131
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192 (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \
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193 | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET)
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111
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194 #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
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195 #define OPTION_MASK_ISA_AVX2_UNSET \
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196 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
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197 #define OPTION_MASK_ISA_AVX512F_UNSET \
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198 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
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199 | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
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200 | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
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131
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201 | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \
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202 | OPTION_MASK_ISA_AVX512VBMI2_UNSET \
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203 | OPTION_MASK_ISA_AVX512VNNI_UNSET \
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204 | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \
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205 | OPTION_MASK_ISA_AVX512BITALG_UNSET)
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111
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206 #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
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207 #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
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208 #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
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209 #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
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210 #define OPTION_MASK_ISA_AVX512BW_UNSET \
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211 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET)
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212 #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
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213 #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
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214 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
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145
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215 #define OPTION_MASK_ISA2_AVX5124FMAPS_UNSET OPTION_MASK_ISA2_AVX5124FMAPS
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216 #define OPTION_MASK_ISA2_AVX5124VNNIW_UNSET OPTION_MASK_ISA2_AVX5124VNNIW
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131
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217 #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
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218 #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
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111
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219 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
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131
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220 #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
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145
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221 #define OPTION_MASK_ISA2_AVX512BF16_UNSET OPTION_MASK_ISA2_AVX512BF16
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111
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222 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
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223 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
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224 #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
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225 #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
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226 #define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1
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227 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
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228 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
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229 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
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230 #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
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145
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231 #define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX
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232 #define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO
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111
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233 #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
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145
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234 #define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID
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111
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235 #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
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236 #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
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145
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237 #define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES
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131
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238 #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
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239 #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
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145
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240 #define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B
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241 #define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG
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242 #define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE
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243 #define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD
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244 #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT
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111
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245
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246 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
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247 as -mno-sse4.1. */
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248 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
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249
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250 #define OPTION_MASK_ISA_SSE4A_UNSET \
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251 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
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252
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253 #define OPTION_MASK_ISA_FMA4_UNSET \
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254 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
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255 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
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256 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
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257
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258 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
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259 #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
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260 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
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261 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
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145
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262 #define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG
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263 #define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD
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264 #define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX
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111
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265 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
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266 #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
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267 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
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268 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
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269 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
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145
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270 #define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16
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111
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271 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
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145
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272 #define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE
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111
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273 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
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274
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275 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
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276 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
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145
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277 #define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE
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111
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278 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
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279
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280 #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
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281 (OPTION_MASK_ISA_MMX_UNSET \
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131
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282 | OPTION_MASK_ISA_SSE_UNSET)
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283
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284 #define OPTION_MASK_ISA2_AVX512F_UNSET \
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145
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285 (OPTION_MASK_ISA2_AVX512BF16_UNSET \
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286 | OPTION_MASK_ISA2_AVX5124FMAPS_UNSET \
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287 | OPTION_MASK_ISA2_AVX5124VNNIW_UNSET \
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288 | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET)
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131
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289 #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
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290 (OPTION_MASK_ISA2_AVX512F_UNSET)
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291
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145
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292 #define OPTION_MASK_ISA2_AVX512BW_UNSET OPTION_MASK_ISA2_AVX512BF16_UNSET
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293
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131
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294 /* Set 1 << value as value of -malign-FLAG option. */
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295
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296 static void
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297 set_malign_value (const char **flag, unsigned value)
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298 {
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299 char *r = XNEWVEC (char, 6);
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300 sprintf (r, "%d", 1 << value);
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301 *flag = r;
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302 }
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111
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303
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304 /* Implement TARGET_HANDLE_OPTION. */
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305
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306 bool
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307 ix86_handle_option (struct gcc_options *opts,
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308 struct gcc_options *opts_set ATTRIBUTE_UNUSED,
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309 const struct cl_decoded_option *decoded,
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310 location_t loc)
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311 {
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312 size_t code = decoded->opt_index;
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313 int value = decoded->value;
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314
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315 switch (code)
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316 {
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317 case OPT_mgeneral_regs_only:
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318 if (value)
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319 {
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131
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320 /* Disable MMX, SSE and x87 instructions if only
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111
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321 general registers are allowed. */
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322 opts->x_ix86_isa_flags
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323 &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
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131
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324 opts->x_ix86_isa_flags2
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325 &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
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111
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326 opts->x_ix86_isa_flags_explicit
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327 |= OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
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131
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328 opts->x_ix86_isa_flags2_explicit
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329 |= OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
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111
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330
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331 opts->x_target_flags &= ~MASK_80387;
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332 }
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333 else
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334 gcc_unreachable ();
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335 return true;
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336
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337 case OPT_mmmx:
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338 if (value)
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339 {
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340 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
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341 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
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342 }
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343 else
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344 {
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345 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
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346 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
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347 }
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348 return true;
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349
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350 case OPT_m3dnow:
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351 if (value)
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352 {
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353 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
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354 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
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355 }
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356 else
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357 {
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358 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
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359 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
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360 }
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361 return true;
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362
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363 case OPT_m3dnowa:
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364 if (value)
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365 {
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366 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET;
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367 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET;
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368 }
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369 else
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370 {
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371 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET;
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372 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET;
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373 }
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374 return true;
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375
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376 case OPT_msse:
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377 if (value)
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378 {
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379 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
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380 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
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381 }
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382 else
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383 {
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384 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
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385 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
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131
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386 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
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387 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
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|
111
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388 }
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389 return true;
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390
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391 case OPT_msse2:
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392 if (value)
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393 {
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394 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
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395 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
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396 }
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397 else
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398 {
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399 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
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400 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
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|
131
|
401 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
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|
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402 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
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|
111
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403 }
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404 return true;
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405
|
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406 case OPT_msse3:
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|
|
407 if (value)
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|
|
408 {
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|
|
409 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
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410 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
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411 }
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|
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412 else
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|
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413 {
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|
|
414 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
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|
|
415 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
|
|
131
|
416 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
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|
|
417 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
|
|
111
|
418 }
|
|
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419 return true;
|
|
|
420
|
|
|
421 case OPT_mssse3:
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|
|
422 if (value)
|
|
|
423 {
|
|
|
424 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
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|
|
425 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
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|
|
426 }
|
|
|
427 else
|
|
|
428 {
|
|
|
429 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
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|
|
430 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
|
|
131
|
431 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
|
|
|
432 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
|
|
111
|
433 }
|
|
|
434 return true;
|
|
|
435
|
|
|
436 case OPT_msse4_1:
|
|
|
437 if (value)
|
|
|
438 {
|
|
|
439 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
|
|
|
440 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
|
|
|
441 }
|
|
|
442 else
|
|
|
443 {
|
|
|
444 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
|
|
|
445 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
|
|
131
|
446 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
|
|
|
447 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
|
|
111
|
448 }
|
|
|
449 return true;
|
|
|
450
|
|
|
451 case OPT_msse4_2:
|
|
|
452 if (value)
|
|
|
453 {
|
|
|
454 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
|
|
|
455 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
|
|
|
456 }
|
|
|
457 else
|
|
|
458 {
|
|
|
459 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
|
|
|
460 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
|
|
131
|
461 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
|
|
|
462 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
|
|
111
|
463 }
|
|
|
464 return true;
|
|
|
465
|
|
|
466 case OPT_mavx:
|
|
|
467 if (value)
|
|
|
468 {
|
|
|
469 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
|
|
|
470 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
|
|
|
471 }
|
|
|
472 else
|
|
|
473 {
|
|
|
474 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
|
|
|
475 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
|
|
131
|
476 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
|
|
|
477 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
|
|
111
|
478 }
|
|
|
479 return true;
|
|
|
480
|
|
|
481 case OPT_mavx2:
|
|
|
482 if (value)
|
|
|
483 {
|
|
|
484 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
|
|
|
485 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
|
|
|
486 }
|
|
|
487 else
|
|
|
488 {
|
|
|
489 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
|
|
|
490 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
|
|
131
|
491 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
|
|
|
492 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
|
|
111
|
493 }
|
|
|
494 return true;
|
|
|
495
|
|
|
496 case OPT_mavx512f:
|
|
|
497 if (value)
|
|
|
498 {
|
|
|
499 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
|
|
|
500 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
|
|
|
501 }
|
|
|
502 else
|
|
|
503 {
|
|
|
504 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET;
|
|
|
505 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
|
|
131
|
506 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
|
|
|
507 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
|
|
111
|
508 }
|
|
|
509 return true;
|
|
|
510
|
|
|
511 case OPT_mavx512cd:
|
|
|
512 if (value)
|
|
|
513 {
|
|
|
514 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET;
|
|
|
515 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET;
|
|
|
516 }
|
|
|
517 else
|
|
|
518 {
|
|
|
519 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
|
|
|
520 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
|
|
|
521 }
|
|
|
522 return true;
|
|
|
523
|
|
|
524 case OPT_mavx512pf:
|
|
|
525 if (value)
|
|
|
526 {
|
|
|
527 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF_SET;
|
|
|
528 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_SET;
|
|
|
529 }
|
|
|
530 else
|
|
|
531 {
|
|
|
532 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512PF_UNSET;
|
|
|
533 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_UNSET;
|
|
|
534 }
|
|
|
535 return true;
|
|
|
536
|
|
|
537 case OPT_mavx512er:
|
|
|
538 if (value)
|
|
|
539 {
|
|
|
540 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER_SET;
|
|
|
541 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_SET;
|
|
|
542 }
|
|
|
543 else
|
|
|
544 {
|
|
|
545 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512ER_UNSET;
|
|
|
546 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_UNSET;
|
|
|
547 }
|
|
|
548 return true;
|
|
|
549
|
|
|
550 case OPT_mrdpid:
|
|
|
551 if (value)
|
|
|
552 {
|
|
145
|
553 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RDPID_SET;
|
|
|
554 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_SET;
|
|
111
|
555 }
|
|
|
556 else
|
|
|
557 {
|
|
145
|
558 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RDPID_UNSET;
|
|
|
559 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_UNSET;
|
|
111
|
560 }
|
|
|
561 return true;
|
|
|
562
|
|
|
563 case OPT_mgfni:
|
|
|
564 if (value)
|
|
|
565 {
|
|
131
|
566 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET;
|
|
|
567 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET;
|
|
111
|
568 }
|
|
|
569 else
|
|
|
570 {
|
|
131
|
571 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET;
|
|
|
572 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET;
|
|
111
|
573 }
|
|
|
574 return true;
|
|
|
575
|
|
|
576 case OPT_mshstk:
|
|
|
577 if (value)
|
|
|
578 {
|
|
131
|
579 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHSTK_SET;
|
|
|
580 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_SET;
|
|
|
581 }
|
|
|
582 else
|
|
|
583 {
|
|
|
584 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHSTK_UNSET;
|
|
|
585 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_UNSET;
|
|
|
586 }
|
|
|
587 return true;
|
|
|
588
|
|
|
589 case OPT_mvaes:
|
|
|
590 if (value)
|
|
|
591 {
|
|
145
|
592 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_VAES_SET;
|
|
|
593 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_SET;
|
|
131
|
594 }
|
|
|
595 else
|
|
|
596 {
|
|
145
|
597 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_VAES_UNSET;
|
|
|
598 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_UNSET;
|
|
131
|
599 }
|
|
|
600 return true;
|
|
|
601
|
|
|
602 case OPT_mvpclmulqdq:
|
|
|
603 if (value)
|
|
|
604 {
|
|
|
605 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
|
|
|
606 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
|
|
111
|
607 }
|
|
|
608 else
|
|
|
609 {
|
|
131
|
610 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
|
|
|
611 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
|
|
|
612 }
|
|
|
613 return true;
|
|
|
614
|
|
|
615 case OPT_mmovdiri:
|
|
|
616 if (value)
|
|
|
617 {
|
|
|
618 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI_SET;
|
|
|
619 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_SET;
|
|
|
620 }
|
|
|
621 else
|
|
|
622 {
|
|
|
623 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVDIRI_UNSET;
|
|
|
624 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_UNSET;
|
|
|
625 }
|
|
|
626 return true;
|
|
|
627
|
|
|
628 case OPT_mmovdir64b:
|
|
|
629 if (value)
|
|
|
630 {
|
|
145
|
631 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVDIR64B_SET;
|
|
|
632 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_SET;
|
|
131
|
633 }
|
|
|
634 else
|
|
|
635 {
|
|
145
|
636 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVDIR64B_UNSET;
|
|
|
637 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_UNSET;
|
|
131
|
638 }
|
|
|
639 return true;
|
|
|
640
|
|
|
641 case OPT_mcldemote:
|
|
|
642 if (value)
|
|
|
643 {
|
|
145
|
644 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLDEMOTE_SET;
|
|
|
645 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_SET;
|
|
131
|
646 }
|
|
|
647 else
|
|
|
648 {
|
|
145
|
649 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLDEMOTE_UNSET;
|
|
|
650 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_UNSET;
|
|
131
|
651 }
|
|
|
652 return true;
|
|
|
653
|
|
|
654 case OPT_mwaitpkg:
|
|
|
655 if (value)
|
|
|
656 {
|
|
145
|
657 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WAITPKG_SET;
|
|
|
658 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_SET;
|
|
131
|
659 }
|
|
|
660 else
|
|
|
661 {
|
|
145
|
662 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WAITPKG_UNSET;
|
|
|
663 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_UNSET;
|
|
|
664 }
|
|
|
665 return true;
|
|
|
666
|
|
|
667 case OPT_menqcmd:
|
|
|
668 if (value)
|
|
|
669 {
|
|
|
670 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_ENQCMD_SET;
|
|
|
671 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_SET;
|
|
|
672 }
|
|
|
673 else
|
|
|
674 {
|
|
|
675 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_ENQCMD_UNSET;
|
|
|
676 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_UNSET;
|
|
111
|
677 }
|
|
|
678 return true;
|
|
|
679
|
|
|
680 case OPT_mavx5124fmaps:
|
|
|
681 if (value)
|
|
|
682 {
|
|
145
|
683 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124FMAPS_SET;
|
|
|
684 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124FMAPS_SET;
|
|
111
|
685 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
|
|
|
686 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
|
|
|
687 }
|
|
|
688 else
|
|
|
689 {
|
|
145
|
690 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX5124FMAPS_UNSET;
|
|
|
691 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124FMAPS_UNSET;
|
|
111
|
692 }
|
|
|
693 return true;
|
|
|
694
|
|
|
695 case OPT_mavx5124vnniw:
|
|
|
696 if (value)
|
|
|
697 {
|
|
145
|
698 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124VNNIW_SET;
|
|
|
699 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124VNNIW_SET;
|
|
111
|
700 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
|
|
|
701 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
|
|
|
702 }
|
|
|
703 else
|
|
|
704 {
|
|
145
|
705 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX5124VNNIW_UNSET;
|
|
|
706 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124VNNIW_UNSET;
|
|
111
|
707 }
|
|
|
708 return true;
|
|
|
709
|
|
131
|
710 case OPT_mavx512vbmi2:
|
|
|
711 if (value)
|
|
|
712 {
|
|
|
713 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET;
|
|
|
714 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET;
|
|
|
715 }
|
|
|
716 else
|
|
|
717 {
|
|
|
718 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
|
|
|
719 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
|
|
|
720 }
|
|
|
721 return true;
|
|
|
722
|
|
|
723 case OPT_mavx512vnni:
|
|
|
724 if (value)
|
|
|
725 {
|
|
|
726 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET;
|
|
|
727 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET;
|
|
|
728 }
|
|
|
729 else
|
|
|
730 {
|
|
|
731 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
|
|
|
732 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
|
|
|
733 }
|
|
|
734 return true;
|
|
|
735
|
|
111
|
736 case OPT_mavx512vpopcntdq:
|
|
|
737 if (value)
|
|
|
738 {
|
|
131
|
739 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
|
|
|
740 opts->x_ix86_isa_flags_explicit
|
|
|
741 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
|
|
111
|
742 }
|
|
|
743 else
|
|
|
744 {
|
|
131
|
745 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
|
|
|
746 opts->x_ix86_isa_flags_explicit
|
|
|
747 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
|
|
|
748 }
|
|
|
749 return true;
|
|
|
750
|
|
|
751 case OPT_mavx512bitalg:
|
|
|
752 if (value)
|
|
|
753 {
|
|
|
754 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET;
|
|
|
755 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET;
|
|
|
756 }
|
|
|
757 else
|
|
|
758 {
|
|
|
759 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
|
|
|
760 opts->x_ix86_isa_flags_explicit
|
|
|
761 |= OPTION_MASK_ISA_AVX512BITALG_UNSET;
|
|
111
|
762 }
|
|
|
763 return true;
|
|
|
764
|
|
145
|
765 case OPT_mavx512bf16:
|
|
|
766 if (value)
|
|
|
767 {
|
|
|
768 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BF16_SET;
|
|
|
769 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_SET;
|
|
|
770 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
|
|
|
771 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
|
|
|
772 }
|
|
|
773 else
|
|
|
774 {
|
|
|
775 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET;
|
|
|
776 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET;
|
|
|
777 }
|
|
|
778 return true;
|
|
|
779
|
|
111
|
780 case OPT_msgx:
|
|
|
781 if (value)
|
|
|
782 {
|
|
145
|
783 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SGX_SET;
|
|
|
784 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_SET;
|
|
111
|
785 }
|
|
|
786 else
|
|
|
787 {
|
|
145
|
788 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SGX_UNSET;
|
|
|
789 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_UNSET;
|
|
111
|
790 }
|
|
|
791 return true;
|
|
|
792
|
|
131
|
793 case OPT_mpconfig:
|
|
|
794 if (value)
|
|
|
795 {
|
|
145
|
796 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PCONFIG_SET;
|
|
|
797 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_SET;
|
|
131
|
798 }
|
|
|
799 else
|
|
|
800 {
|
|
145
|
801 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PCONFIG_UNSET;
|
|
|
802 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_UNSET;
|
|
131
|
803 }
|
|
|
804 return true;
|
|
|
805
|
|
|
806 case OPT_mwbnoinvd:
|
|
|
807 if (value)
|
|
|
808 {
|
|
145
|
809 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WBNOINVD_SET;
|
|
|
810 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_SET;
|
|
131
|
811 }
|
|
|
812 else
|
|
|
813 {
|
|
145
|
814 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WBNOINVD_UNSET;
|
|
|
815 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_UNSET;
|
|
131
|
816 }
|
|
|
817 return true;
|
|
|
818
|
|
111
|
819 case OPT_mavx512dq:
|
|
|
820 if (value)
|
|
|
821 {
|
|
|
822 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
|
|
|
823 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
|
|
|
824 }
|
|
|
825 else
|
|
|
826 {
|
|
|
827 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
|
|
|
828 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
|
|
|
829 }
|
|
|
830 return true;
|
|
|
831
|
|
|
832 case OPT_mavx512bw:
|
|
|
833 if (value)
|
|
|
834 {
|
|
|
835 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
|
|
|
836 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
|
|
|
837 }
|
|
|
838 else
|
|
|
839 {
|
|
|
840 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET;
|
|
|
841 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
|
|
145
|
842 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET;
|
|
|
843 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET;
|
|
111
|
844 }
|
|
|
845 return true;
|
|
|
846
|
|
|
847 case OPT_mavx512vl:
|
|
|
848 if (value)
|
|
|
849 {
|
|
|
850 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET;
|
|
|
851 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET;
|
|
|
852 }
|
|
|
853 else
|
|
|
854 {
|
|
|
855 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
|
|
|
856 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
|
|
|
857 }
|
|
|
858 return true;
|
|
|
859
|
|
|
860 case OPT_mavx512ifma:
|
|
|
861 if (value)
|
|
|
862 {
|
|
|
863 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET;
|
|
|
864 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET;
|
|
|
865 }
|
|
|
866 else
|
|
|
867 {
|
|
|
868 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
|
|
|
869 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
|
|
|
870 }
|
|
|
871 return true;
|
|
|
872
|
|
|
873 case OPT_mavx512vbmi:
|
|
|
874 if (value)
|
|
|
875 {
|
|
|
876 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET;
|
|
|
877 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET;
|
|
|
878 }
|
|
|
879 else
|
|
|
880 {
|
|
|
881 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
|
|
|
882 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
|
|
|
883 }
|
|
|
884 return true;
|
|
|
885
|
|
145
|
886 case OPT_mavx512vp2intersect:
|
|
|
887 if (value)
|
|
|
888 {
|
|
|
889 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
|
|
|
890 opts->x_ix86_isa_flags2_explicit |=
|
|
|
891 OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
|
|
|
892 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
|
|
|
893 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
|
|
|
894 }
|
|
|
895 else
|
|
|
896 {
|
|
|
897 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
|
|
|
898 opts->x_ix86_isa_flags2_explicit |=
|
|
|
899 OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
|
|
|
900 }
|
|
|
901 return true;
|
|
|
902
|
|
111
|
903 case OPT_mfma:
|
|
|
904 if (value)
|
|
|
905 {
|
|
|
906 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
|
|
|
907 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
|
|
|
908 }
|
|
|
909 else
|
|
|
910 {
|
|
|
911 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
|
|
|
912 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
|
|
|
913 }
|
|
|
914 return true;
|
|
|
915
|
|
|
916 case OPT_mrtm:
|
|
|
917 if (value)
|
|
|
918 {
|
|
|
919 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
|
|
|
920 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
|
|
|
921 }
|
|
|
922 else
|
|
|
923 {
|
|
|
924 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
|
|
|
925 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
|
|
|
926 }
|
|
|
927 return true;
|
|
|
928
|
|
|
929 case OPT_msse4:
|
|
|
930 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
|
|
|
931 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
|
|
|
932 return true;
|
|
|
933
|
|
|
934 case OPT_mno_sse4:
|
|
|
935 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
|
|
|
936 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
|
|
131
|
937 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
|
|
|
938 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
|
|
111
|
939 return true;
|
|
|
940
|
|
|
941 case OPT_msse4a:
|
|
|
942 if (value)
|
|
|
943 {
|
|
|
944 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
|
|
|
945 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
|
|
|
946 }
|
|
|
947 else
|
|
|
948 {
|
|
|
949 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
|
|
|
950 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
|
|
|
951 }
|
|
|
952 return true;
|
|
|
953
|
|
|
954 case OPT_mfma4:
|
|
|
955 if (value)
|
|
|
956 {
|
|
|
957 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
|
|
|
958 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
|
|
|
959 }
|
|
|
960 else
|
|
|
961 {
|
|
|
962 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
|
|
|
963 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
|
|
|
964 }
|
|
|
965 return true;
|
|
|
966
|
|
|
967 case OPT_mxop:
|
|
|
968 if (value)
|
|
|
969 {
|
|
|
970 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
|
|
|
971 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
|
|
|
972 }
|
|
|
973 else
|
|
|
974 {
|
|
|
975 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
|
|
|
976 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
|
|
|
977 }
|
|
|
978 return true;
|
|
|
979
|
|
|
980 case OPT_mlwp:
|
|
|
981 if (value)
|
|
|
982 {
|
|
|
983 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
|
|
|
984 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
|
|
|
985 }
|
|
|
986 else
|
|
|
987 {
|
|
|
988 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
|
|
|
989 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
|
|
|
990 }
|
|
|
991 return true;
|
|
|
992
|
|
|
993 case OPT_mabm:
|
|
|
994 if (value)
|
|
|
995 {
|
|
|
996 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
|
|
|
997 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
|
|
|
998 }
|
|
|
999 else
|
|
|
1000 {
|
|
|
1001 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
|
|
|
1002 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
|
|
|
1003 }
|
|
|
1004 return true;
|
|
|
1005
|
|
|
1006 case OPT_mbmi:
|
|
|
1007 if (value)
|
|
|
1008 {
|
|
|
1009 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET;
|
|
|
1010 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET;
|
|
|
1011 }
|
|
|
1012 else
|
|
|
1013 {
|
|
|
1014 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET;
|
|
|
1015 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET;
|
|
|
1016 }
|
|
|
1017 return true;
|
|
|
1018
|
|
|
1019 case OPT_mbmi2:
|
|
|
1020 if (value)
|
|
|
1021 {
|
|
|
1022 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET;
|
|
|
1023 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET;
|
|
|
1024 }
|
|
|
1025 else
|
|
|
1026 {
|
|
|
1027 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET;
|
|
|
1028 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET;
|
|
|
1029 }
|
|
|
1030 return true;
|
|
|
1031
|
|
|
1032 case OPT_mlzcnt:
|
|
|
1033 if (value)
|
|
|
1034 {
|
|
|
1035 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET;
|
|
|
1036 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET;
|
|
|
1037 }
|
|
|
1038 else
|
|
|
1039 {
|
|
|
1040 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET;
|
|
|
1041 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET;
|
|
|
1042 }
|
|
|
1043 return true;
|
|
|
1044
|
|
|
1045 case OPT_mtbm:
|
|
|
1046 if (value)
|
|
|
1047 {
|
|
|
1048 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET;
|
|
|
1049 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET;
|
|
|
1050 }
|
|
|
1051 else
|
|
|
1052 {
|
|
|
1053 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET;
|
|
|
1054 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET;
|
|
|
1055 }
|
|
|
1056 return true;
|
|
|
1057
|
|
|
1058 case OPT_mpopcnt:
|
|
|
1059 if (value)
|
|
|
1060 {
|
|
|
1061 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
|
|
|
1062 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
|
|
|
1063 }
|
|
|
1064 else
|
|
|
1065 {
|
|
|
1066 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
|
|
|
1067 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
|
|
|
1068 }
|
|
|
1069 return true;
|
|
|
1070
|
|
|
1071 case OPT_msahf:
|
|
|
1072 if (value)
|
|
|
1073 {
|
|
|
1074 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
|
|
|
1075 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
|
|
|
1076 }
|
|
|
1077 else
|
|
|
1078 {
|
|
|
1079 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
|
|
|
1080 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
|
|
|
1081 }
|
|
|
1082 return true;
|
|
|
1083
|
|
|
1084 case OPT_mcx16:
|
|
|
1085 if (value)
|
|
|
1086 {
|
|
145
|
1087 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CX16_SET;
|
|
|
1088 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_SET;
|
|
111
|
1089 }
|
|
|
1090 else
|
|
|
1091 {
|
|
145
|
1092 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CX16_UNSET;
|
|
|
1093 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_UNSET;
|
|
111
|
1094 }
|
|
|
1095 return true;
|
|
|
1096
|
|
|
1097 case OPT_mmovbe:
|
|
|
1098 if (value)
|
|
|
1099 {
|
|
145
|
1100 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVBE_SET;
|
|
|
1101 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_SET;
|
|
111
|
1102 }
|
|
|
1103 else
|
|
|
1104 {
|
|
145
|
1105 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVBE_UNSET;
|
|
|
1106 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_UNSET;
|
|
111
|
1107 }
|
|
|
1108 return true;
|
|
|
1109
|
|
|
1110 case OPT_mcrc32:
|
|
|
1111 if (value)
|
|
|
1112 {
|
|
|
1113 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
|
|
|
1114 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
|
|
|
1115 }
|
|
|
1116 else
|
|
|
1117 {
|
|
|
1118 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
|
|
|
1119 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
|
|
|
1120 }
|
|
|
1121 return true;
|
|
|
1122
|
|
|
1123 case OPT_maes:
|
|
|
1124 if (value)
|
|
|
1125 {
|
|
|
1126 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
|
|
|
1127 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
|
|
|
1128 }
|
|
|
1129 else
|
|
|
1130 {
|
|
|
1131 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
|
|
|
1132 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
|
|
|
1133 }
|
|
|
1134 return true;
|
|
|
1135
|
|
|
1136 case OPT_msha:
|
|
|
1137 if (value)
|
|
|
1138 {
|
|
|
1139 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET;
|
|
|
1140 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET;
|
|
|
1141 }
|
|
|
1142 else
|
|
|
1143 {
|
|
|
1144 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET;
|
|
|
1145 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET;
|
|
|
1146 }
|
|
|
1147 return true;
|
|
|
1148
|
|
|
1149 case OPT_mpclmul:
|
|
|
1150 if (value)
|
|
|
1151 {
|
|
|
1152 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
|
|
|
1153 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
|
|
|
1154 }
|
|
|
1155 else
|
|
|
1156 {
|
|
|
1157 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
|
|
|
1158 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
|
|
|
1159 }
|
|
|
1160 return true;
|
|
|
1161
|
|
|
1162 case OPT_mfsgsbase:
|
|
|
1163 if (value)
|
|
|
1164 {
|
|
|
1165 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET;
|
|
|
1166 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET;
|
|
|
1167 }
|
|
|
1168 else
|
|
|
1169 {
|
|
|
1170 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET;
|
|
|
1171 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET;
|
|
|
1172 }
|
|
|
1173 return true;
|
|
|
1174
|
|
|
1175 case OPT_mrdrnd:
|
|
|
1176 if (value)
|
|
|
1177 {
|
|
|
1178 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET;
|
|
|
1179 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET;
|
|
|
1180 }
|
|
|
1181 else
|
|
|
1182 {
|
|
|
1183 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
|
|
|
1184 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
|
|
|
1185 }
|
|
|
1186 return true;
|
|
|
1187
|
|
145
|
1188 case OPT_mptwrite:
|
|
|
1189 if (value)
|
|
|
1190 {
|
|
|
1191 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PTWRITE_SET;
|
|
|
1192 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_SET;
|
|
|
1193 }
|
|
|
1194 else
|
|
|
1195 {
|
|
|
1196 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PTWRITE_UNSET;
|
|
|
1197 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_UNSET;
|
|
|
1198 }
|
|
|
1199 return true;
|
|
|
1200
|
|
111
|
1201 case OPT_mf16c:
|
|
|
1202 if (value)
|
|
|
1203 {
|
|
|
1204 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
|
|
|
1205 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
|
|
|
1206 }
|
|
|
1207 else
|
|
|
1208 {
|
|
|
1209 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET;
|
|
|
1210 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET;
|
|
|
1211 }
|
|
|
1212 return true;
|
|
|
1213
|
|
|
1214 case OPT_mfxsr:
|
|
|
1215 if (value)
|
|
|
1216 {
|
|
|
1217 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET;
|
|
|
1218 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET;
|
|
|
1219 }
|
|
|
1220 else
|
|
|
1221 {
|
|
|
1222 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET;
|
|
|
1223 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET;
|
|
|
1224 }
|
|
|
1225 return true;
|
|
|
1226
|
|
|
1227 case OPT_mxsave:
|
|
|
1228 if (value)
|
|
|
1229 {
|
|
|
1230 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
|
|
|
1231 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
|
|
|
1232 }
|
|
|
1233 else
|
|
|
1234 {
|
|
|
1235 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET;
|
|
|
1236 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET;
|
|
|
1237 }
|
|
|
1238 return true;
|
|
|
1239
|
|
|
1240 case OPT_mxsaveopt:
|
|
|
1241 if (value)
|
|
|
1242 {
|
|
|
1243 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET;
|
|
|
1244 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET;
|
|
|
1245 }
|
|
|
1246 else
|
|
|
1247 {
|
|
|
1248 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET;
|
|
|
1249 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET;
|
|
|
1250 }
|
|
|
1251 return true;
|
|
|
1252
|
|
|
1253 case OPT_mxsavec:
|
|
|
1254 if (value)
|
|
|
1255 {
|
|
|
1256 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET;
|
|
|
1257 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET;
|
|
|
1258 }
|
|
|
1259 else
|
|
|
1260 {
|
|
|
1261 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET;
|
|
|
1262 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET;
|
|
|
1263 }
|
|
|
1264 return true;
|
|
|
1265
|
|
|
1266 case OPT_mxsaves:
|
|
|
1267 if (value)
|
|
|
1268 {
|
|
|
1269 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET;
|
|
|
1270 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET;
|
|
|
1271 }
|
|
|
1272 else
|
|
|
1273 {
|
|
|
1274 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET;
|
|
|
1275 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET;
|
|
|
1276 }
|
|
|
1277 return true;
|
|
|
1278
|
|
|
1279 case OPT_mrdseed:
|
|
|
1280 if (value)
|
|
|
1281 {
|
|
|
1282 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET;
|
|
|
1283 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET;
|
|
|
1284 }
|
|
|
1285 else
|
|
|
1286 {
|
|
|
1287 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET;
|
|
|
1288 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET;
|
|
|
1289 }
|
|
|
1290 return true;
|
|
|
1291
|
|
|
1292 case OPT_mprfchw:
|
|
|
1293 if (value)
|
|
|
1294 {
|
|
|
1295 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
|
|
|
1296 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
|
|
|
1297 }
|
|
|
1298 else
|
|
|
1299 {
|
|
|
1300 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
|
|
|
1301 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
|
|
|
1302 }
|
|
|
1303 return true;
|
|
|
1304
|
|
|
1305 case OPT_madx:
|
|
|
1306 if (value)
|
|
|
1307 {
|
|
|
1308 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET;
|
|
|
1309 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET;
|
|
|
1310 }
|
|
|
1311 else
|
|
|
1312 {
|
|
|
1313 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET;
|
|
|
1314 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET;
|
|
|
1315 }
|
|
|
1316 return true;
|
|
|
1317
|
|
|
1318 case OPT_mprefetchwt1:
|
|
|
1319 if (value)
|
|
|
1320 {
|
|
|
1321 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1_SET;
|
|
|
1322 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_SET;
|
|
|
1323 }
|
|
|
1324 else
|
|
|
1325 {
|
|
|
1326 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PREFETCHWT1_UNSET;
|
|
|
1327 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_UNSET;
|
|
|
1328 }
|
|
|
1329 return true;
|
|
|
1330
|
|
|
1331 case OPT_mclflushopt:
|
|
|
1332 if (value)
|
|
|
1333 {
|
|
|
1334 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
|
|
|
1335 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
|
|
|
1336 }
|
|
|
1337 else
|
|
|
1338 {
|
|
|
1339 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
|
|
|
1340 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
|
|
|
1341 }
|
|
|
1342 return true;
|
|
|
1343
|
|
|
1344 case OPT_mclwb:
|
|
|
1345 if (value)
|
|
|
1346 {
|
|
|
1347 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET;
|
|
|
1348 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET;
|
|
|
1349 }
|
|
|
1350 else
|
|
|
1351 {
|
|
|
1352 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET;
|
|
|
1353 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET;
|
|
|
1354 }
|
|
|
1355 return true;
|
|
|
1356
|
|
|
1357 case OPT_mmwaitx:
|
|
|
1358 if (value)
|
|
|
1359 {
|
|
145
|
1360 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAITX_SET;
|
|
|
1361 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_SET;
|
|
111
|
1362 }
|
|
|
1363 else
|
|
|
1364 {
|
|
145
|
1365 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAITX_UNSET;
|
|
|
1366 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_UNSET;
|
|
111
|
1367 }
|
|
|
1368 return true;
|
|
|
1369
|
|
|
1370 case OPT_mclzero:
|
|
|
1371 if (value)
|
|
|
1372 {
|
|
145
|
1373 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLZERO_SET;
|
|
|
1374 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_SET;
|
|
111
|
1375 }
|
|
|
1376 else
|
|
|
1377 {
|
|
145
|
1378 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLZERO_UNSET;
|
|
|
1379 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_UNSET;
|
|
111
|
1380 }
|
|
|
1381 return true;
|
|
|
1382
|
|
|
1383 case OPT_mpku:
|
|
|
1384 if (value)
|
|
|
1385 {
|
|
|
1386 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET;
|
|
|
1387 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET;
|
|
|
1388 }
|
|
|
1389 else
|
|
|
1390 {
|
|
|
1391 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET;
|
|
|
1392 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET;
|
|
|
1393 }
|
|
|
1394 return true;
|
|
|
1395
|
|
|
1396
|
|
|
1397 case OPT_malign_loops_:
|
|
145
|
1398 warning_at (loc, 0, "%<-malign-loops%> is obsolete, "
|
|
|
1399 "use %<-falign-loops%>");
|
|
111
|
1400 if (value > MAX_CODE_ALIGN)
|
|
145
|
1401 error_at (loc, "%<-malign-loops=%d%> is not between 0 and %d",
|
|
111
|
1402 value, MAX_CODE_ALIGN);
|
|
|
1403 else
|
|
131
|
1404 set_malign_value (&opts->x_str_align_loops, value);
|
|
111
|
1405 return true;
|
|
|
1406
|
|
|
1407 case OPT_malign_jumps_:
|
|
145
|
1408 warning_at (loc, 0, "%<-malign-jumps%> is obsolete, "
|
|
|
1409 "use %<-falign-jumps%>");
|
|
111
|
1410 if (value > MAX_CODE_ALIGN)
|
|
145
|
1411 error_at (loc, "%<-malign-jumps=%d%> is not between 0 and %d",
|
|
111
|
1412 value, MAX_CODE_ALIGN);
|
|
|
1413 else
|
|
131
|
1414 set_malign_value (&opts->x_str_align_jumps, value);
|
|
111
|
1415 return true;
|
|
|
1416
|
|
|
1417 case OPT_malign_functions_:
|
|
|
1418 warning_at (loc, 0,
|
|
145
|
1419 "%<-malign-functions%> is obsolete, "
|
|
|
1420 "use %<-falign-functions%>");
|
|
111
|
1421 if (value > MAX_CODE_ALIGN)
|
|
145
|
1422 error_at (loc, "%<-malign-functions=%d%> is not between 0 and %d",
|
|
111
|
1423 value, MAX_CODE_ALIGN);
|
|
|
1424 else
|
|
131
|
1425 set_malign_value (&opts->x_str_align_functions, value);
|
|
111
|
1426 return true;
|
|
|
1427
|
|
|
1428 case OPT_mbranch_cost_:
|
|
|
1429 if (value > 5)
|
|
|
1430 {
|
|
145
|
1431 error_at (loc, "%<-mbranch-cost=%d%> is not between 0 and 5", value);
|
|
111
|
1432 opts->x_ix86_branch_cost = 5;
|
|
|
1433 }
|
|
|
1434 return true;
|
|
|
1435
|
|
|
1436 default:
|
|
|
1437 return true;
|
|
|
1438 }
|
|
|
1439 }
|
|
|
1440
|
|
|
1441 static const struct default_options ix86_option_optimization_table[] =
|
|
|
1442 {
|
|
|
1443 /* Enable redundant extension instructions removal at -O2 and higher. */
|
|
|
1444 { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
|
|
|
1445 /* Enable function splitting at -O2 and higher. */
|
|
|
1446 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 },
|
|
|
1447 /* The STC algorithm produces the smallest code at -Os, for x86. */
|
|
|
1448 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_algorithm_, NULL,
|
|
|
1449 REORDER_BLOCKS_ALGORITHM_STC },
|
|
|
1450 /* Turn off -fschedule-insns by default. It tends to make the
|
|
|
1451 problem with not enough registers even worse. */
|
|
|
1452 { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
|
|
|
1453
|
|
|
1454 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
|
|
|
1455 SUBTARGET_OPTIMIZATION_OPTIONS,
|
|
|
1456 #endif
|
|
|
1457 { OPT_LEVELS_NONE, 0, NULL, 0 }
|
|
|
1458 };
|
|
|
1459
|
|
|
1460 /* Implement TARGET_OPTION_INIT_STRUCT. */
|
|
|
1461
|
|
|
1462 static void
|
|
|
1463 ix86_option_init_struct (struct gcc_options *opts)
|
|
|
1464 {
|
|
|
1465 if (TARGET_MACHO)
|
|
|
1466 /* The Darwin libraries never set errno, so we might as well
|
|
|
1467 avoid calling them when that's the only reason we would. */
|
|
|
1468 opts->x_flag_errno_math = 0;
|
|
|
1469
|
|
|
1470 opts->x_flag_pcc_struct_return = 2;
|
|
|
1471 opts->x_flag_asynchronous_unwind_tables = 2;
|
|
|
1472 }
|
|
|
1473
|
|
|
1474 /* On the x86 -fsplit-stack and -fstack-protector both use the same
|
|
145
|
1475 field in the TCB, so they cannot be used together. */
|
|
111
|
1476
|
|
|
1477 static bool
|
|
|
1478 ix86_supports_split_stack (bool report ATTRIBUTE_UNUSED,
|
|
|
1479 struct gcc_options *opts ATTRIBUTE_UNUSED)
|
|
|
1480 {
|
|
|
1481 bool ret = true;
|
|
|
1482
|
|
|
1483 #ifndef TARGET_THREAD_SPLIT_STACK_OFFSET
|
|
|
1484 if (report)
|
|
|
1485 error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
|
|
|
1486 ret = false;
|
|
|
1487 #else
|
|
|
1488 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
|
|
|
1489 {
|
|
|
1490 if (report)
|
|
|
1491 error ("%<-fsplit-stack%> requires "
|
|
|
1492 "assembler support for CFI directives");
|
|
|
1493 ret = false;
|
|
|
1494 }
|
|
|
1495 #endif
|
|
|
1496
|
|
|
1497 return ret;
|
|
|
1498 }
|
|
|
1499
|
|
|
1500 /* Implement TARGET_EXCEPT_UNWIND_INFO. */
|
|
|
1501
|
|
|
1502 static enum unwind_info_type
|
|
|
1503 i386_except_unwind_info (struct gcc_options *opts)
|
|
|
1504 {
|
|
|
1505 /* Honor the --enable-sjlj-exceptions configure switch. */
|
|
|
1506 #ifdef CONFIG_SJLJ_EXCEPTIONS
|
|
|
1507 if (CONFIG_SJLJ_EXCEPTIONS)
|
|
|
1508 return UI_SJLJ;
|
|
|
1509 #endif
|
|
|
1510
|
|
|
1511 /* On windows 64, prefer SEH exceptions over anything else. */
|
|
|
1512 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables)
|
|
|
1513 return UI_SEH;
|
|
|
1514
|
|
|
1515 if (DWARF2_UNWIND_INFO)
|
|
|
1516 return UI_DWARF2;
|
|
|
1517
|
|
|
1518 return UI_SJLJ;
|
|
|
1519 }
|
|
|
1520
|
|
|
1521 #undef TARGET_EXCEPT_UNWIND_INFO
|
|
|
1522 #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info
|
|
|
1523
|
|
|
1524 #undef TARGET_DEFAULT_TARGET_FLAGS
|
|
|
1525 #define TARGET_DEFAULT_TARGET_FLAGS \
|
|
|
1526 (TARGET_DEFAULT \
|
|
|
1527 | TARGET_SUBTARGET_DEFAULT \
|
|
|
1528 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
|
|
|
1529
|
|
|
1530 #undef TARGET_HANDLE_OPTION
|
|
|
1531 #define TARGET_HANDLE_OPTION ix86_handle_option
|
|
|
1532
|
|
|
1533 #undef TARGET_OPTION_OPTIMIZATION_TABLE
|
|
|
1534 #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
|
|
|
1535 #undef TARGET_OPTION_INIT_STRUCT
|
|
|
1536 #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
|
|
|
1537
|
|
|
1538 #undef TARGET_SUPPORTS_SPLIT_STACK
|
|
|
1539 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
|
|
|
1540
|
|
131
|
1541 /* This table must be in sync with enum processor_type in i386.h. */
|
|
145
|
1542 const char *const processor_names[] =
|
|
131
|
1543 {
|
|
|
1544 "generic",
|
|
|
1545 "i386",
|
|
|
1546 "i486",
|
|
|
1547 "pentium",
|
|
|
1548 "lakemont",
|
|
|
1549 "pentiumpro",
|
|
|
1550 "pentium4",
|
|
|
1551 "nocona",
|
|
|
1552 "core2",
|
|
|
1553 "nehalem",
|
|
|
1554 "sandybridge",
|
|
|
1555 "haswell",
|
|
|
1556 "bonnell",
|
|
|
1557 "silvermont",
|
|
|
1558 "goldmont",
|
|
|
1559 "goldmont-plus",
|
|
|
1560 "tremont",
|
|
|
1561 "knl",
|
|
|
1562 "knm",
|
|
|
1563 "skylake",
|
|
|
1564 "skylake-avx512",
|
|
|
1565 "cannonlake",
|
|
|
1566 "icelake-client",
|
|
|
1567 "icelake-server",
|
|
145
|
1568 "cascadelake",
|
|
|
1569 "tigerlake",
|
|
|
1570 "cooperlake",
|
|
131
|
1571 "intel",
|
|
|
1572 "geode",
|
|
|
1573 "k6",
|
|
|
1574 "athlon",
|
|
|
1575 "k8",
|
|
|
1576 "amdfam10",
|
|
|
1577 "bdver1",
|
|
|
1578 "bdver2",
|
|
|
1579 "bdver3",
|
|
|
1580 "bdver4",
|
|
|
1581 "btver1",
|
|
|
1582 "btver2",
|
|
145
|
1583 "znver1",
|
|
|
1584 "znver2"
|
|
131
|
1585 };
|
|
|
1586
|
|
145
|
1587 /* Guarantee that the array is aligned with enum processor_type. */
|
|
|
1588 STATIC_ASSERT (ARRAY_SIZE (processor_names) == PROCESSOR_max);
|
|
|
1589
|
|
131
|
1590 const pta processor_alias_table[] =
|
|
|
1591 {
|
|
|
1592 {"i386", PROCESSOR_I386, CPU_NONE, 0},
|
|
|
1593 {"i486", PROCESSOR_I486, CPU_NONE, 0},
|
|
|
1594 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
|
|
|
1595 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
|
|
|
1596 {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
|
|
|
1597 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
|
|
|
1598 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
|
|
|
1599 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
|
|
|
1600 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
|
|
|
1601 {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
|
|
|
1602 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
|
|
|
1603 PTA_MMX | PTA_SSE | PTA_FXSR},
|
|
|
1604 {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
|
|
|
1605 PTA_MMX | PTA_SSE | PTA_FXSR},
|
|
|
1606 {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
|
|
|
1607 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
|
|
|
1608 {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
|
|
|
1609 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
|
|
|
1610 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
|
|
|
1611 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
|
|
|
1612 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
|
|
|
1613 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
|
|
|
1614 PTA_MMX | PTA_SSE | PTA_FXSR},
|
|
|
1615 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
|
|
|
1616 PTA_MMX | PTA_SSE | PTA_FXSR},
|
|
|
1617 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
|
|
|
1618 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
|
|
|
1619 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
|
|
145
|
1620 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
|
|
131
|
1621 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
|
|
|
1622 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
|
|
|
1623 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
|
|
|
1624 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
|
|
|
1625 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
|
|
|
1626 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
|
|
|
1627 | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
|
|
|
1628 {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
|
|
|
1629 {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
|
|
|
1630 {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
|
|
|
1631 {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
|
|
|
1632 {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
|
|
|
1633 PTA_SANDYBRIDGE},
|
|
|
1634 {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
|
|
|
1635 PTA_SANDYBRIDGE},
|
|
|
1636 {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
|
|
|
1637 PTA_IVYBRIDGE},
|
|
|
1638 {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
|
|
|
1639 PTA_IVYBRIDGE},
|
|
|
1640 {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
|
|
|
1641 {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
|
|
|
1642 {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
|
|
|
1643 {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
|
|
|
1644 {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
|
|
|
1645 PTA_SKYLAKE_AVX512},
|
|
|
1646 {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
|
|
|
1647 {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
|
|
|
1648 PTA_ICELAKE_CLIENT},
|
|
|
1649 {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
|
|
|
1650 PTA_ICELAKE_SERVER},
|
|
145
|
1651 {"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL,
|
|
|
1652 PTA_CASCADELAKE},
|
|
|
1653 {"tigerlake", PROCESSOR_TIGERLAKE, CPU_HASWELL, PTA_TIGERLAKE},
|
|
|
1654 {"cooperlake", PROCESSOR_COOPERLAKE, CPU_HASWELL, PTA_COOPERLAKE},
|
|
131
|
1655 {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
|
|
|
1656 {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
|
|
|
1657 {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
|
|
|
1658 {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
|
|
|
1659 {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
|
|
|
1660 {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
|
|
|
1661 {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
|
|
|
1662 {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
|
|
|
1663 {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
|
|
|
1664 {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
|
|
|
1665 {"geode", PROCESSOR_GEODE, CPU_GEODE,
|
|
|
1666 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
|
|
|
1667 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
|
|
|
1668 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
|
|
|
1669 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
|
|
|
1670 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
|
|
|
1671 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
|
|
|
1672 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
|
|
|
1673 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
|
|
|
1674 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
|
|
|
1675 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
|
|
|
1676 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
|
|
|
1677 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
|
|
|
1678 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
|
|
|
1679 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
|
|
|
1680 {"x86-64", PROCESSOR_K8, CPU_K8,
|
|
|
1681 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
|
|
|
1682 {"eden-x2", PROCESSOR_K8, CPU_K8,
|
|
|
1683 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
|
|
|
1684 {"nano", PROCESSOR_K8, CPU_K8,
|
|
|
1685 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
|
|
|
1686 | PTA_SSSE3 | PTA_FXSR},
|
|
|
1687 {"nano-1000", PROCESSOR_K8, CPU_K8,
|
|
|
1688 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
|
|
|
1689 | PTA_SSSE3 | PTA_FXSR},
|
|
|
1690 {"nano-2000", PROCESSOR_K8, CPU_K8,
|
|
|
1691 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
|
|
|
1692 | PTA_SSSE3 | PTA_FXSR},
|
|
|
1693 {"nano-3000", PROCESSOR_K8, CPU_K8,
|
|
|
1694 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
|
|
|
1695 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
|
|
|
1696 {"nano-x2", PROCESSOR_K8, CPU_K8,
|
|
|
1697 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
|
|
|
1698 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
|
|
|
1699 {"eden-x4", PROCESSOR_K8, CPU_K8,
|
|
|
1700 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
|
|
|
1701 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
|
|
|
1702 {"nano-x4", PROCESSOR_K8, CPU_K8,
|
|
|
1703 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
|
|
|
1704 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
|
|
|
1705 {"k8", PROCESSOR_K8, CPU_K8,
|
|
|
1706 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
|
|
|
1707 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
|
|
|
1708 {"k8-sse3", PROCESSOR_K8, CPU_K8,
|
|
|
1709 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
|
|
|
1710 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
|
|
|
1711 {"opteron", PROCESSOR_K8, CPU_K8,
|
|
|
1712 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
|
|
|
1713 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
|
|
|
1714 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
|
|
|
1715 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
|
|
|
1716 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
|
|
|
1717 {"athlon64", PROCESSOR_K8, CPU_K8,
|
|
|
1718 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
|
|
|
1719 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
|
|
|
1720 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
|
|
|
1721 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
|
|
|
1722 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
|
|
|
1723 {"athlon-fx", PROCESSOR_K8, CPU_K8,
|
|
|
1724 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
|
|
|
1725 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
|
|
|
1726 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
|
|
|
1727 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
|
|
|
1728 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
|
|
|
1729 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
|
|
|
1730 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
|
|
|
1731 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
|
|
|
1732 {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
|
|
|
1733 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
|
|
|
1734 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
|
|
|
1735 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
|
|
|
1736 | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
|
|
|
1737 {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
|
|
|
1738 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
|
|
|
1739 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
|
|
|
1740 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
|
|
|
1741 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
|
|
|
1742 | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
|
|
|
1743 {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
|
|
|
1744 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
|
|
|
1745 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
|
|
|
1746 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
|
|
|
1747 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
|
|
|
1748 | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
|
|
|
1749 | PTA_XSAVEOPT | PTA_FSGSBASE},
|
|
|
1750 {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
|
|
|
1751 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
|
|
|
1752 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
|
|
|
1753 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
|
|
|
1754 | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
|
|
|
1755 | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
|
|
|
1756 | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
|
|
|
1757 | PTA_MOVBE | PTA_MWAITX},
|
|
|
1758 {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
|
|
|
1759 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
|
|
|
1760 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
|
|
|
1761 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
|
|
|
1762 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
|
|
|
1763 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
|
|
|
1764 | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
|
|
|
1765 | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
|
|
|
1766 | PTA_SHA | PTA_LZCNT | PTA_POPCNT},
|
|
145
|
1767 {"znver2", PROCESSOR_ZNVER2, CPU_ZNVER2,
|
|
|
1768 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
|
|
|
1769 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
|
|
|
1770 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
|
|
|
1771 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
|
|
|
1772 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
|
|
|
1773 | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
|
|
|
1774 | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
|
|
|
1775 | PTA_SHA | PTA_LZCNT | PTA_POPCNT | PTA_CLWB | PTA_RDPID
|
|
|
1776 | PTA_WBNOINVD},
|
|
131
|
1777 {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
|
|
145
|
1778 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
|
|
|
1779 | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_PRFCHW
|
|
131
|
1780 | PTA_FXSR | PTA_XSAVE},
|
|
|
1781 {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
|
|
145
|
1782 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
|
|
|
1783 | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_SSE4_1
|
|
131
|
1784 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
|
|
|
1785 | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
|
|
|
1786 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
|
|
|
1787
|
|
|
1788 {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
|
|
|
1789 PTA_64BIT
|
|
|
1790 | PTA_HLE /* flags are only used for -march switch. */ },
|
|
|
1791 };
|
|
|
1792
|
|
|
1793 int const pta_size = ARRAY_SIZE (processor_alias_table);
|
|
|
1794
|
|
|
1795 /* Provide valid option values for -march and -mtune options. */
|
|
|
1796
|
|
|
1797 vec<const char *>
|
|
|
1798 ix86_get_valid_option_values (int option_code,
|
|
|
1799 const char *prefix ATTRIBUTE_UNUSED)
|
|
|
1800 {
|
|
|
1801 vec<const char *> v;
|
|
|
1802 v.create (0);
|
|
|
1803 opt_code opt = (opt_code) option_code;
|
|
|
1804
|
|
|
1805 switch (opt)
|
|
|
1806 {
|
|
|
1807 case OPT_march_:
|
|
|
1808 for (unsigned i = 0; i < pta_size; i++)
|
|
145
|
1809 {
|
|
|
1810 const char *name = processor_alias_table[i].name;
|
|
|
1811 gcc_checking_assert (name != NULL);
|
|
|
1812 v.safe_push (name);
|
|
|
1813 }
|
|
|
1814 #ifdef HAVE_LOCAL_CPU_DETECT
|
|
|
1815 /* Add also "native" as possible value. */
|
|
|
1816 v.safe_push ("native");
|
|
|
1817 #endif
|
|
|
1818
|
|
131
|
1819 break;
|
|
|
1820 case OPT_mtune_:
|
|
|
1821 for (unsigned i = 0; i < PROCESSOR_max; i++)
|
|
145
|
1822 {
|
|
|
1823 const char *name = processor_names[i];
|
|
|
1824 gcc_checking_assert (name != NULL);
|
|
|
1825 v.safe_push (name);
|
|
|
1826 }
|
|
131
|
1827 break;
|
|
|
1828 default:
|
|
|
1829 break;
|
|
|
1830 }
|
|
|
1831
|
|
|
1832 return v;
|
|
|
1833 }
|
|
|
1834
|
|
|
1835 #undef TARGET_GET_VALID_OPTION_VALUES
|
|
|
1836 #define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
|
|
|
1837
|
|
111
|
1838 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
|
