Mercurial > hg > CbC > CbC_gcc
diff gcc/common/config/i386/i386-common.c @ 145:1830386684a0
gcc-9.2.0
| author | anatofuz |
|---|---|
| date | Thu, 13 Feb 2020 11:34:05 +0900 |
| parents | 84e7813d76e9 |
| children |
line wrap: on
line diff
--- a/gcc/common/config/i386/i386-common.c Thu Oct 25 07:37:49 2018 +0900 +++ b/gcc/common/config/i386/i386-common.c Thu Feb 13 11:34:05 2020 +0900 @@ -1,5 +1,5 @@ /* IA-32 common hooks. - Copyright (C) 1988-2018 Free Software Foundation, Inc. + Copyright (C) 1988-2020 Free Software Foundation, Inc. This file is part of GCC. @@ -78,8 +78,8 @@ (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET) #define OPTION_MASK_ISA_AVX512VBMI_SET \ (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET) -#define OPTION_MASK_ISA_AVX5124FMAPS_SET OPTION_MASK_ISA_AVX5124FMAPS -#define OPTION_MASK_ISA_AVX5124VNNIW_SET OPTION_MASK_ISA_AVX5124VNNIW +#define OPTION_MASK_ISA2_AVX5124FMAPS_SET OPTION_MASK_ISA2_AVX5124FMAPS +#define OPTION_MASK_ISA2_AVX5124VNNIW_SET OPTION_MASK_ISA2_AVX5124VNNIW #define OPTION_MASK_ISA_AVX512VBMI2_SET \ (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET) #define OPTION_MASK_ISA_AVX512VNNI_SET \ @@ -88,6 +88,7 @@ (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET) #define OPTION_MASK_ISA_AVX512BITALG_SET \ (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED @@ -99,6 +100,7 @@ #define OPTION_MASK_ISA_XSAVEC_SET \ (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET) #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB +#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same as -msse4.2. */ @@ -125,35 +127,37 @@ #define OPTION_MASK_ISA_ABM_SET \ (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT) -#define OPTION_MASK_ISA_PCONFIG_SET OPTION_MASK_ISA_PCONFIG -#define OPTION_MASK_ISA_WBNOINVD_SET OPTION_MASK_ISA_WBNOINVD -#define OPTION_MASK_ISA_SGX_SET OPTION_MASK_ISA_SGX +#define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG +#define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD +#define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT -#define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16 +#define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF -#define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE +#define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND +#define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE #define OPTION_MASK_ISA_F16C_SET \ (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET) -#define OPTION_MASK_ISA_MWAITX_SET OPTION_MASK_ISA_MWAITX -#define OPTION_MASK_ISA_CLZERO_SET OPTION_MASK_ISA_CLZERO +#define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX +#define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU -#define OPTION_MASK_ISA_RDPID_SET OPTION_MASK_ISA_RDPID +#define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK -#define OPTION_MASK_ISA_VAES_SET OPTION_MASK_ISA_VAES +#define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES #define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI -#define OPTION_MASK_ISA_MOVDIR64B_SET OPTION_MASK_ISA_MOVDIR64B -#define OPTION_MASK_ISA_WAITPKG_SET OPTION_MASK_ISA_WAITPKG -#define OPTION_MASK_ISA_CLDEMOTE_SET OPTION_MASK_ISA_CLDEMOTE +#define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B +#define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG +#define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE +#define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD /* Define a set of ISAs which aren't available when a given ISA is disabled. MMX and SSE ISAs are handled separately. */ @@ -208,12 +212,13 @@ #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI -#define OPTION_MASK_ISA_AVX5124FMAPS_UNSET OPTION_MASK_ISA_AVX5124FMAPS -#define OPTION_MASK_ISA_AVX5124VNNIW_UNSET OPTION_MASK_ISA_AVX5124VNNIW +#define OPTION_MASK_ISA2_AVX5124FMAPS_UNSET OPTION_MASK_ISA2_AVX5124FMAPS +#define OPTION_MASK_ISA2_AVX5124VNNIW_UNSET OPTION_MASK_ISA2_AVX5124VNNIW #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2 #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG +#define OPTION_MASK_ISA2_AVX512BF16_UNSET OPTION_MASK_ISA2_AVX512BF16 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED @@ -223,18 +228,20 @@ #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB -#define OPTION_MASK_ISA_MWAITX_UNSET OPTION_MASK_ISA_MWAITX -#define OPTION_MASK_ISA_CLZERO_UNSET OPTION_MASK_ISA_CLZERO +#define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX +#define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU -#define OPTION_MASK_ISA_RDPID_UNSET OPTION_MASK_ISA_RDPID +#define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK -#define OPTION_MASK_ISA_VAES_UNSET OPTION_MASK_ISA_VAES +#define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI -#define OPTION_MASK_ISA_MOVDIR64B_UNSET OPTION_MASK_ISA_MOVDIR64B -#define OPTION_MASK_ISA_WAITPKG_UNSET OPTION_MASK_ISA_WAITPKG -#define OPTION_MASK_ISA_CLDEMOTE_UNSET OPTION_MASK_ISA_CLDEMOTE +#define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B +#define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG +#define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE +#define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD +#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -252,21 +259,22 @@ #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM -#define OPTION_MASK_ISA_PCONFIG_UNSET OPTION_MASK_ISA_PCONFIG -#define OPTION_MASK_ISA_WBNOINVD_UNSET OPTION_MASK_ISA_WBNOINVD -#define OPTION_MASK_ISA_SGX_UNSET OPTION_MASK_ISA_SGX +#define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG +#define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD +#define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT -#define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16 +#define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF -#define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE +#define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND +#define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \ @@ -274,10 +282,15 @@ | OPTION_MASK_ISA_SSE_UNSET) #define OPTION_MASK_ISA2_AVX512F_UNSET \ - (OPTION_MASK_ISA_AVX5124FMAPS_UNSET | OPTION_MASK_ISA_AVX5124VNNIW_UNSET) + (OPTION_MASK_ISA2_AVX512BF16_UNSET \ + | OPTION_MASK_ISA2_AVX5124FMAPS_UNSET \ + | OPTION_MASK_ISA2_AVX5124VNNIW_UNSET \ + | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET) #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ (OPTION_MASK_ISA2_AVX512F_UNSET) +#define OPTION_MASK_ISA2_AVX512BW_UNSET OPTION_MASK_ISA2_AVX512BF16_UNSET + /* Set 1 << value as value of -malign-FLAG option. */ static void @@ -537,13 +550,13 @@ case OPT_mrdpid: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RDPID_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_RDPID_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RDPID_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_UNSET; } return true; @@ -576,13 +589,13 @@ case OPT_mvaes: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_VAES_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_VAES_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_VAES_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_VAES_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_UNSET; } return true; @@ -615,69 +628,82 @@ case OPT_mmovdir64b: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVDIR64B_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVDIR64B_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVDIR64B_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVDIR64B_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_UNSET; } return true; case OPT_mcldemote: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLDEMOTE_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLDEMOTE_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLDEMOTE_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CLDEMOTE_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLDEMOTE_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLDEMOTE_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_UNSET; } return true; case OPT_mwaitpkg: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WAITPKG_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WAITPKG_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WAITPKG_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_WAITPKG_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WAITPKG_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WAITPKG_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_UNSET; + } + return true; + + case OPT_menqcmd: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_ENQCMD_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_ENQCMD_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_UNSET; } return true; case OPT_mavx5124fmaps: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124FMAPS_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124FMAPS_SET; opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124FMAPS_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX5124FMAPS_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124FMAPS_UNSET; } return true; case OPT_mavx5124vnniw: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124VNNIW_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124VNNIW_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124VNNIW_SET; opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124VNNIW_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX5124VNNIW_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124VNNIW_UNSET; } return true; @@ -736,42 +762,57 @@ } return true; + case OPT_mavx512bf16: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BF16_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_SET; + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET; + } + return true; + case OPT_msgx: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SGX_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_SGX_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SGX_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_UNSET; } return true; case OPT_mpconfig: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PCONFIG_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PCONFIG_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_PCONFIG_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PCONFIG_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_UNSET; } return true; case OPT_mwbnoinvd: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WBNOINVD_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WBNOINVD_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_WBNOINVD_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WBNOINVD_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_UNSET; } return true; @@ -798,6 +839,8 @@ { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET; } return true; @@ -840,6 +883,23 @@ } return true; + case OPT_mavx512vp2intersect: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET; + opts->x_ix86_isa_flags2_explicit |= + OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET; + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET; + opts->x_ix86_isa_flags2_explicit |= + OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET; + } + return true; + case OPT_mfma: if (value) { @@ -1024,26 +1084,26 @@ case OPT_mcx16: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CX16_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CX16_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CX16_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CX16_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_UNSET; } return true; case OPT_mmovbe: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVBE_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVBE_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVBE_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVBE_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_UNSET; } return true; @@ -1125,6 +1185,19 @@ } return true; + case OPT_mptwrite: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PTWRITE_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PTWRITE_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_UNSET; + } + return true; + case OPT_mf16c: if (value) { @@ -1284,26 +1357,26 @@ case OPT_mmwaitx: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MWAITX_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAITX_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MWAITX_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAITX_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_UNSET; } return true; case OPT_mclzero: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLZERO_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLZERO_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CLZERO_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLZERO_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_UNSET; } return true; @@ -1322,18 +1395,20 @@ case OPT_malign_loops_: - warning_at (loc, 0, "-malign-loops is obsolete, use -falign-loops"); + warning_at (loc, 0, "%<-malign-loops%> is obsolete, " + "use %<-falign-loops%>"); if (value > MAX_CODE_ALIGN) - error_at (loc, "-malign-loops=%d is not between 0 and %d", + error_at (loc, "%<-malign-loops=%d%> is not between 0 and %d", value, MAX_CODE_ALIGN); else set_malign_value (&opts->x_str_align_loops, value); return true; case OPT_malign_jumps_: - warning_at (loc, 0, "-malign-jumps is obsolete, use -falign-jumps"); + warning_at (loc, 0, "%<-malign-jumps%> is obsolete, " + "use %<-falign-jumps%>"); if (value > MAX_CODE_ALIGN) - error_at (loc, "-malign-jumps=%d is not between 0 and %d", + error_at (loc, "%<-malign-jumps=%d%> is not between 0 and %d", value, MAX_CODE_ALIGN); else set_malign_value (&opts->x_str_align_jumps, value); @@ -1341,9 +1416,10 @@ case OPT_malign_functions_: warning_at (loc, 0, - "-malign-functions is obsolete, use -falign-functions"); + "%<-malign-functions%> is obsolete, " + "use %<-falign-functions%>"); if (value > MAX_CODE_ALIGN) - error_at (loc, "-malign-functions=%d is not between 0 and %d", + error_at (loc, "%<-malign-functions=%d%> is not between 0 and %d", value, MAX_CODE_ALIGN); else set_malign_value (&opts->x_str_align_functions, value); @@ -1352,7 +1428,7 @@ case OPT_mbranch_cost_: if (value > 5) { - error_at (loc, "-mbranch-cost=%d is not between 0 and 5", value); + error_at (loc, "%<-mbranch-cost=%d%> is not between 0 and 5", value); opts->x_ix86_branch_cost = 5; } return true; @@ -1396,7 +1472,7 @@ } /* On the x86 -fsplit-stack and -fstack-protector both use the same - field in the TCB, so they can not be used together. */ + field in the TCB, so they cannot be used together. */ static bool ix86_supports_split_stack (bool report ATTRIBUTE_UNUSED, @@ -1463,7 +1539,7 @@ #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack /* This table must be in sync with enum processor_type in i386.h. */ -const char *const processor_names[PROCESSOR_max] = +const char *const processor_names[] = { "generic", "i386", @@ -1489,6 +1565,9 @@ "cannonlake", "icelake-client", "icelake-server", + "cascadelake", + "tigerlake", + "cooperlake", "intel", "geode", "k6", @@ -1501,9 +1580,13 @@ "bdver4", "btver1", "btver2", - "znver1" + "znver1", + "znver2" }; +/* Guarantee that the array is aligned with enum processor_type. */ +STATIC_ASSERT (ARRAY_SIZE (processor_names) == PROCESSOR_max); + const pta processor_alias_table[] = { {"i386", PROCESSOR_I386, CPU_NONE, 0}, @@ -1534,7 +1617,7 @@ {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR}, {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE, - PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR}, + PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR}, {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE, PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR}, {"prescott", PROCESSOR_NOCONA, CPU_NONE, @@ -1565,6 +1648,10 @@ PTA_ICELAKE_CLIENT}, {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL, PTA_ICELAKE_SERVER}, + {"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL, + PTA_CASCADELAKE}, + {"tigerlake", PROCESSOR_TIGERLAKE, CPU_HASWELL, PTA_TIGERLAKE}, + {"cooperlake", PROCESSOR_COOPERLAKE, CPU_HASWELL, PTA_COOPERLAKE}, {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL}, {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL}, {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT}, @@ -1677,13 +1764,23 @@ | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES | PTA_SHA | PTA_LZCNT | PTA_POPCNT}, + {"znver2", PROCESSOR_ZNVER2, CPU_ZNVER2, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 + | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2 + | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW + | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE + | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED + | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES + | PTA_SHA | PTA_LZCNT | PTA_POPCNT | PTA_CLWB | PTA_RDPID + | PTA_WBNOINVD}, {"btver1", PROCESSOR_BTVER1, CPU_GENERIC, - PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 - | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE}, {"btver2", PROCESSOR_BTVER2, CPU_BTVER2, - PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 - | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1 + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT}, @@ -1709,11 +1806,24 @@ { case OPT_march_: for (unsigned i = 0; i < pta_size; i++) - v.safe_push (processor_alias_table[i].name); + { + const char *name = processor_alias_table[i].name; + gcc_checking_assert (name != NULL); + v.safe_push (name); + } +#ifdef HAVE_LOCAL_CPU_DETECT + /* Add also "native" as possible value. */ + v.safe_push ("native"); +#endif + break; case OPT_mtune_: for (unsigned i = 0; i < PROCESSOR_max; i++) - v.safe_push (processor_names[i]); + { + const char *name = processor_names[i]; + gcc_checking_assert (name != NULL); + v.safe_push (name); + } break; default: break;