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comparison gcc/config/arm/vec-common.md @ 145:1830386684a0

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gcc-9.2.0
author anatofuz
date Thu, 13 Feb 2020 11:34:05 +0900
parents 84e7813d76e9
children
comparison
equal deleted inserted replaced
131:84e7813d76e9 145:1830386684a0
1 ;; Machine Description for shared bits common to IWMMXT and Neon. 1 ;; Machine Description for shared bits common to IWMMXT and Neon.
2 ;; Copyright (C) 2006-2018 Free Software Foundation, Inc. 2 ;; Copyright (C) 2006-2020 Free Software Foundation, Inc.
3 ;; Written by CodeSourcery. 3 ;; Written by CodeSourcery.
4 ;; 4 ;;
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 ;; 6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it 7 ;; GCC is free software; you can redistribute it and/or modify it
19 ;; <http://www.gnu.org/licenses/>. 19 ;; <http://www.gnu.org/licenses/>.
20 20
21 ;; Vector Moves 21 ;; Vector Moves
22 22
23 (define_expand "mov<mode>" 23 (define_expand "mov<mode>"
24 [(set (match_operand:VALL 0 "nonimmediate_operand" "") 24 [(set (match_operand:VALL 0 "nonimmediate_operand")
25 (match_operand:VALL 1 "general_operand" ""))] 25 (match_operand:VALL 1 "general_operand"))]
26 "TARGET_NEON 26 "TARGET_NEON
27 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" 27 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
28 { 28 {
29 gcc_checking_assert (aligned_operand (operands[0], <MODE>mode));
30 gcc_checking_assert (aligned_operand (operands[1], <MODE>mode));
29 if (can_create_pseudo_p ()) 31 if (can_create_pseudo_p ())
30 { 32 {
31 if (!REG_P (operands[0])) 33 if (!REG_P (operands[0]))
32 operands[1] = force_reg (<MODE>mode, operands[1]); 34 operands[1] = force_reg (<MODE>mode, operands[1]);
33 else if (TARGET_NEON && CONSTANT_P (operands[1])) 35 else if (TARGET_NEON && CONSTANT_P (operands[1]))
40 42
41 ;; Vector arithmetic. Expanders are blank, then unnamed insns implement 43 ;; Vector arithmetic. Expanders are blank, then unnamed insns implement
42 ;; patterns separately for IWMMXT and Neon. 44 ;; patterns separately for IWMMXT and Neon.
43 45
44 (define_expand "add<mode>3" 46 (define_expand "add<mode>3"
45 [(set (match_operand:VALL 0 "s_register_operand" "") 47 [(set (match_operand:VALL 0 "s_register_operand")
46 (plus:VALL (match_operand:VALL 1 "s_register_operand" "") 48 (plus:VALL (match_operand:VALL 1 "s_register_operand")
47 (match_operand:VALL 2 "s_register_operand" "")))] 49 (match_operand:VALL 2 "s_register_operand")))]
48 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) 50 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
49 || flag_unsafe_math_optimizations)) 51 || flag_unsafe_math_optimizations))
50 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" 52 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
51 { 53 {
52 }) 54 })
53 55
54 (define_expand "sub<mode>3" 56 (define_expand "sub<mode>3"
55 [(set (match_operand:VALL 0 "s_register_operand" "") 57 [(set (match_operand:VALL 0 "s_register_operand")
56 (minus:VALL (match_operand:VALL 1 "s_register_operand" "") 58 (minus:VALL (match_operand:VALL 1 "s_register_operand")
57 (match_operand:VALL 2 "s_register_operand" "")))] 59 (match_operand:VALL 2 "s_register_operand")))]
58 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) 60 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
59 || flag_unsafe_math_optimizations)) 61 || flag_unsafe_math_optimizations))
60 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" 62 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
61 { 63 {
62 }) 64 })
63 65
64 (define_expand "mul<mode>3" 66 (define_expand "mul<mode>3"
65 [(set (match_operand:VALLW 0 "s_register_operand" "") 67 [(set (match_operand:VALLW 0 "s_register_operand")
66 (mult:VALLW (match_operand:VALLW 1 "s_register_operand" "") 68 (mult:VALLW (match_operand:VALLW 1 "s_register_operand")
67 (match_operand:VALLW 2 "s_register_operand" "")))] 69 (match_operand:VALLW 2 "s_register_operand")))]
68 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) 70 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
69 || flag_unsafe_math_optimizations)) 71 || flag_unsafe_math_optimizations))
70 || (<MODE>mode == V4HImode && TARGET_REALLY_IWMMXT)" 72 || (<MODE>mode == V4HImode && TARGET_REALLY_IWMMXT)"
71 { 73 {
72 }) 74 })
73 75
74 (define_expand "smin<mode>3" 76 (define_expand "smin<mode>3"
75 [(set (match_operand:VALLW 0 "s_register_operand" "") 77 [(set (match_operand:VALLW 0 "s_register_operand")
76 (smin:VALLW (match_operand:VALLW 1 "s_register_operand" "") 78 (smin:VALLW (match_operand:VALLW 1 "s_register_operand")
77 (match_operand:VALLW 2 "s_register_operand" "")))] 79 (match_operand:VALLW 2 "s_register_operand")))]
78 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) 80 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
79 || flag_unsafe_math_optimizations)) 81 || flag_unsafe_math_optimizations))
80 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" 82 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
81 { 83 {
82 }) 84 })
83 85
84 (define_expand "umin<mode>3" 86 (define_expand "umin<mode>3"
85 [(set (match_operand:VINTW 0 "s_register_operand" "") 87 [(set (match_operand:VINTW 0 "s_register_operand")
86 (umin:VINTW (match_operand:VINTW 1 "s_register_operand" "") 88 (umin:VINTW (match_operand:VINTW 1 "s_register_operand")
87 (match_operand:VINTW 2 "s_register_operand" "")))] 89 (match_operand:VINTW 2 "s_register_operand")))]
88 "TARGET_NEON 90 "TARGET_NEON
89 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" 91 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
90 { 92 {
91 }) 93 })
92 94
93 (define_expand "smax<mode>3" 95 (define_expand "smax<mode>3"
94 [(set (match_operand:VALLW 0 "s_register_operand" "") 96 [(set (match_operand:VALLW 0 "s_register_operand")
95 (smax:VALLW (match_operand:VALLW 1 "s_register_operand" "") 97 (smax:VALLW (match_operand:VALLW 1 "s_register_operand")
96 (match_operand:VALLW 2 "s_register_operand" "")))] 98 (match_operand:VALLW 2 "s_register_operand")))]
97 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) 99 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
98 || flag_unsafe_math_optimizations)) 100 || flag_unsafe_math_optimizations))
99 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" 101 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
100 { 102 {
101 }) 103 })
102 104
103 (define_expand "umax<mode>3" 105 (define_expand "umax<mode>3"
104 [(set (match_operand:VINTW 0 "s_register_operand" "") 106 [(set (match_operand:VINTW 0 "s_register_operand")
105 (umax:VINTW (match_operand:VINTW 1 "s_register_operand" "") 107 (umax:VINTW (match_operand:VINTW 1 "s_register_operand")
106 (match_operand:VINTW 2 "s_register_operand" "")))] 108 (match_operand:VINTW 2 "s_register_operand")))]
107 "TARGET_NEON 109 "TARGET_NEON
108 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" 110 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
109 { 111 {
110 }) 112 })
111 113
112 (define_expand "vec_perm<mode>" 114 (define_expand "vec_perm<mode>"
113 [(match_operand:VE 0 "s_register_operand" "") 115 [(match_operand:VE 0 "s_register_operand")
114 (match_operand:VE 1 "s_register_operand" "") 116 (match_operand:VE 1 "s_register_operand")
115 (match_operand:VE 2 "s_register_operand" "") 117 (match_operand:VE 2 "s_register_operand")
116 (match_operand:VE 3 "s_register_operand" "")] 118 (match_operand:VE 3 "s_register_operand")]
117 "TARGET_NEON && !BYTES_BIG_ENDIAN" 119 "TARGET_NEON && !BYTES_BIG_ENDIAN"
118 { 120 {
119 arm_expand_vec_perm (operands[0], operands[1], operands[2], operands[3]); 121 arm_expand_vec_perm (operands[0], operands[1], operands[2], operands[3]);
120 DONE; 122 DONE;
121 }) 123 })