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diff gcc/config/arm/vec-common.md @ 145:1830386684a0

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gcc-9.2.0
author anatofuz
date Thu, 13 Feb 2020 11:34:05 +0900
parents 84e7813d76e9
children
line wrap: on
line diff
--- a/gcc/config/arm/vec-common.md	Thu Oct 25 07:37:49 2018 +0900
+++ b/gcc/config/arm/vec-common.md	Thu Feb 13 11:34:05 2020 +0900
@@ -1,5 +1,5 @@
 ;; Machine Description for shared bits common to IWMMXT and Neon.
-;; Copyright (C) 2006-2018 Free Software Foundation, Inc.
+;; Copyright (C) 2006-2020 Free Software Foundation, Inc.
 ;; Written by CodeSourcery.
 ;;
 ;; This file is part of GCC.
@@ -21,11 +21,13 @@
 ;; Vector Moves
 
 (define_expand "mov<mode>"
-  [(set (match_operand:VALL 0 "nonimmediate_operand" "")
-	(match_operand:VALL 1 "general_operand" ""))]
+  [(set (match_operand:VALL 0 "nonimmediate_operand")
+	(match_operand:VALL 1 "general_operand"))]
   "TARGET_NEON
    || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
 {
+  gcc_checking_assert (aligned_operand (operands[0], <MODE>mode));
+  gcc_checking_assert (aligned_operand (operands[1], <MODE>mode));
   if (can_create_pseudo_p ())
     {
       if (!REG_P (operands[0]))
@@ -42,9 +44,9 @@
 ;; patterns separately for IWMMXT and Neon.
 
 (define_expand "add<mode>3"
-  [(set (match_operand:VALL 0 "s_register_operand" "")
-        (plus:VALL (match_operand:VALL 1 "s_register_operand" "")
-                   (match_operand:VALL 2 "s_register_operand" "")))]
+  [(set (match_operand:VALL 0 "s_register_operand")
+        (plus:VALL (match_operand:VALL 1 "s_register_operand")
+                   (match_operand:VALL 2 "s_register_operand")))]
   "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
 		    || flag_unsafe_math_optimizations))
    || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
@@ -52,9 +54,9 @@
 })
 
 (define_expand "sub<mode>3"
-  [(set (match_operand:VALL 0 "s_register_operand" "")
-        (minus:VALL (match_operand:VALL 1 "s_register_operand" "")
-                    (match_operand:VALL 2 "s_register_operand" "")))]
+  [(set (match_operand:VALL 0 "s_register_operand")
+        (minus:VALL (match_operand:VALL 1 "s_register_operand")
+                    (match_operand:VALL 2 "s_register_operand")))]
   "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
 		    || flag_unsafe_math_optimizations))
    || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
@@ -62,9 +64,9 @@
 })
 
 (define_expand "mul<mode>3"
-  [(set (match_operand:VALLW 0 "s_register_operand" "")
-        (mult:VALLW (match_operand:VALLW 1 "s_register_operand" "")
-		    (match_operand:VALLW 2 "s_register_operand" "")))]
+  [(set (match_operand:VALLW 0 "s_register_operand")
+        (mult:VALLW (match_operand:VALLW 1 "s_register_operand")
+		    (match_operand:VALLW 2 "s_register_operand")))]
   "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
 		    || flag_unsafe_math_optimizations))
    || (<MODE>mode == V4HImode && TARGET_REALLY_IWMMXT)"
@@ -72,9 +74,9 @@
 })
 
 (define_expand "smin<mode>3"
-  [(set (match_operand:VALLW 0 "s_register_operand" "")
-	(smin:VALLW (match_operand:VALLW 1 "s_register_operand" "")
-		    (match_operand:VALLW 2 "s_register_operand" "")))]
+  [(set (match_operand:VALLW 0 "s_register_operand")
+	(smin:VALLW (match_operand:VALLW 1 "s_register_operand")
+		    (match_operand:VALLW 2 "s_register_operand")))]
   "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
 		    || flag_unsafe_math_optimizations))
    || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
@@ -82,18 +84,18 @@
 })
 
 (define_expand "umin<mode>3"
-  [(set (match_operand:VINTW 0 "s_register_operand" "")
-	(umin:VINTW (match_operand:VINTW 1 "s_register_operand" "")
-		    (match_operand:VINTW 2 "s_register_operand" "")))]
+  [(set (match_operand:VINTW 0 "s_register_operand")
+	(umin:VINTW (match_operand:VINTW 1 "s_register_operand")
+		    (match_operand:VINTW 2 "s_register_operand")))]
   "TARGET_NEON
    || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
 {
 })
 
 (define_expand "smax<mode>3"
-  [(set (match_operand:VALLW 0 "s_register_operand" "")
-	(smax:VALLW (match_operand:VALLW 1 "s_register_operand" "")
-		    (match_operand:VALLW 2 "s_register_operand" "")))]
+  [(set (match_operand:VALLW 0 "s_register_operand")
+	(smax:VALLW (match_operand:VALLW 1 "s_register_operand")
+		    (match_operand:VALLW 2 "s_register_operand")))]
   "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
 		    || flag_unsafe_math_optimizations))
    || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
@@ -101,19 +103,19 @@
 })
 
 (define_expand "umax<mode>3"
-  [(set (match_operand:VINTW 0 "s_register_operand" "")
-	(umax:VINTW (match_operand:VINTW 1 "s_register_operand" "")
-		    (match_operand:VINTW 2 "s_register_operand" "")))]
+  [(set (match_operand:VINTW 0 "s_register_operand")
+	(umax:VINTW (match_operand:VINTW 1 "s_register_operand")
+		    (match_operand:VINTW 2 "s_register_operand")))]
   "TARGET_NEON
    || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
 {
 })
 
 (define_expand "vec_perm<mode>"
-  [(match_operand:VE 0 "s_register_operand" "")
-   (match_operand:VE 1 "s_register_operand" "")
-   (match_operand:VE 2 "s_register_operand" "")
-   (match_operand:VE 3 "s_register_operand" "")]
+  [(match_operand:VE 0 "s_register_operand")
+   (match_operand:VE 1 "s_register_operand")
+   (match_operand:VE 2 "s_register_operand")
+   (match_operand:VE 3 "s_register_operand")]
   "TARGET_NEON && !BYTES_BIG_ENDIAN"
 {
   arm_expand_vec_perm (operands[0], operands[1], operands[2], operands[3]);