Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/arm/vec-common.md @ 145:1830386684a0
gcc-9.2.0
| author | anatofuz |
|---|---|
| date | Thu, 13 Feb 2020 11:34:05 +0900 |
| parents | 84e7813d76e9 |
| children |
| rev | line source |
|---|---|
| 0 | 1 ;; Machine Description for shared bits common to IWMMXT and Neon. |
| 145 | 2 ;; Copyright (C) 2006-2020 Free Software Foundation, Inc. |
| 0 | 3 ;; Written by CodeSourcery. |
| 4 ;; | |
| 5 ;; This file is part of GCC. | |
| 6 ;; | |
| 7 ;; GCC is free software; you can redistribute it and/or modify it | |
| 8 ;; under the terms of the GNU General Public License as published by | |
| 9 ;; the Free Software Foundation; either version 3, or (at your option) | |
| 10 ;; any later version. | |
| 11 ;; | |
| 12 ;; GCC is distributed in the hope that it will be useful, but | |
| 13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 15 ;; General Public License for more details. | |
| 16 ;; | |
| 17 ;; You should have received a copy of the GNU General Public License | |
| 18 ;; along with GCC; see the file COPYING3. If not see | |
| 19 ;; <http://www.gnu.org/licenses/>. | |
| 20 | |
| 21 ;; Vector Moves | |
| 22 | |
| 23 (define_expand "mov<mode>" | |
| 145 | 24 [(set (match_operand:VALL 0 "nonimmediate_operand") |
| 25 (match_operand:VALL 1 "general_operand"))] | |
| 0 | 26 "TARGET_NEON |
| 27 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" | |
| 28 { | |
| 145 | 29 gcc_checking_assert (aligned_operand (operands[0], <MODE>mode)); |
| 30 gcc_checking_assert (aligned_operand (operands[1], <MODE>mode)); | |
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31 if (can_create_pseudo_p ()) |
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32 { |
| 111 | 33 if (!REG_P (operands[0])) |
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34 operands[1] = force_reg (<MODE>mode, operands[1]); |
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35 else if (TARGET_NEON && CONSTANT_P (operands[1])) |
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36 { |
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37 operands[1] = neon_make_constant (operands[1]); |
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38 gcc_assert (operands[1] != NULL_RTX); |
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39 } |
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40 } |
| 0 | 41 }) |
| 42 | |
| 43 ;; Vector arithmetic. Expanders are blank, then unnamed insns implement | |
| 44 ;; patterns separately for IWMMXT and Neon. | |
| 45 | |
| 46 (define_expand "add<mode>3" | |
| 145 | 47 [(set (match_operand:VALL 0 "s_register_operand") |
| 48 (plus:VALL (match_operand:VALL 1 "s_register_operand") | |
| 49 (match_operand:VALL 2 "s_register_operand")))] | |
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50 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) |
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51 || flag_unsafe_math_optimizations)) |
| 0 | 52 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" |
| 53 { | |
| 54 }) | |
| 55 | |
| 56 (define_expand "sub<mode>3" | |
| 145 | 57 [(set (match_operand:VALL 0 "s_register_operand") |
| 58 (minus:VALL (match_operand:VALL 1 "s_register_operand") | |
| 59 (match_operand:VALL 2 "s_register_operand")))] | |
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60 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) |
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61 || flag_unsafe_math_optimizations)) |
| 0 | 62 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" |
| 63 { | |
| 64 }) | |
| 65 | |
| 66 (define_expand "mul<mode>3" | |
| 145 | 67 [(set (match_operand:VALLW 0 "s_register_operand") |
| 68 (mult:VALLW (match_operand:VALLW 1 "s_register_operand") | |
| 69 (match_operand:VALLW 2 "s_register_operand")))] | |
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parents:
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70 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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71 || flag_unsafe_math_optimizations)) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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72 || (<MODE>mode == V4HImode && TARGET_REALLY_IWMMXT)" |
| 0 | 73 { |
| 74 }) | |
| 75 | |
| 76 (define_expand "smin<mode>3" | |
| 145 | 77 [(set (match_operand:VALLW 0 "s_register_operand") |
| 78 (smin:VALLW (match_operand:VALLW 1 "s_register_operand") | |
| 79 (match_operand:VALLW 2 "s_register_operand")))] | |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
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80 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) |
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f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
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81 || flag_unsafe_math_optimizations)) |
| 0 | 82 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" |
| 83 { | |
| 84 }) | |
| 85 | |
| 86 (define_expand "umin<mode>3" | |
| 145 | 87 [(set (match_operand:VINTW 0 "s_register_operand") |
| 88 (umin:VINTW (match_operand:VINTW 1 "s_register_operand") | |
| 89 (match_operand:VINTW 2 "s_register_operand")))] | |
| 0 | 90 "TARGET_NEON |
| 91 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" | |
| 92 { | |
| 93 }) | |
| 94 | |
| 95 (define_expand "smax<mode>3" | |
| 145 | 96 [(set (match_operand:VALLW 0 "s_register_operand") |
| 97 (smax:VALLW (match_operand:VALLW 1 "s_register_operand") | |
| 98 (match_operand:VALLW 2 "s_register_operand")))] | |
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67
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
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99 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
100 || flag_unsafe_math_optimizations)) |
| 0 | 101 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" |
| 102 { | |
| 103 }) | |
| 104 | |
| 105 (define_expand "umax<mode>3" | |
| 145 | 106 [(set (match_operand:VINTW 0 "s_register_operand") |
| 107 (umax:VINTW (match_operand:VINTW 1 "s_register_operand") | |
| 108 (match_operand:VINTW 2 "s_register_operand")))] | |
| 0 | 109 "TARGET_NEON |
| 110 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" | |
| 111 { | |
| 112 }) | |
| 111 | 113 |
| 114 (define_expand "vec_perm<mode>" | |
| 145 | 115 [(match_operand:VE 0 "s_register_operand") |
| 116 (match_operand:VE 1 "s_register_operand") | |
| 117 (match_operand:VE 2 "s_register_operand") | |
| 118 (match_operand:VE 3 "s_register_operand")] | |
| 111 | 119 "TARGET_NEON && !BYTES_BIG_ENDIAN" |
| 120 { | |
| 121 arm_expand_vec_perm (operands[0], operands[1], operands[2], operands[3]); | |
| 122 DONE; | |
| 123 }) |