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comparison gcc/config/rs6000/dfp.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
comparison
equal deleted inserted replaced
111:04ced10e8804 131:84e7813d76e9
1 ;; Decimal Floating Point (DFP) patterns. 1 ;; Decimal Floating Point (DFP) patterns.
2 ;; Copyright (C) 2007-2017 Free Software Foundation, Inc. 2 ;; Copyright (C) 2007-2018 Free Software Foundation, Inc.
3 ;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner 3 ;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner
4 ;; (bergner@vnet.ibm.com). 4 ;; (bergner@vnet.ibm.com).
5 5
6 ;; This file is part of GCC. 6 ;; This file is part of GCC.
7 7
35 UNSPEC_MOVSD_STORE))] 35 UNSPEC_MOVSD_STORE))]
36 "(gpc_reg_operand (operands[0], DDmode) 36 "(gpc_reg_operand (operands[0], DDmode)
37 || gpc_reg_operand (operands[1], SDmode)) 37 || gpc_reg_operand (operands[1], SDmode))
38 && TARGET_HARD_FLOAT" 38 && TARGET_HARD_FLOAT"
39 "stfd%U0%X0 %1,%0" 39 "stfd%U0%X0 %1,%0"
40 [(set_attr "type" "fpstore") 40 [(set_attr "type" "fpstore")])
41 (set_attr "length" "4")])
42 41
43 (define_insn "movsd_load" 42 (define_insn "movsd_load"
44 [(set (match_operand:SD 0 "nonimmediate_operand" "=f") 43 [(set (match_operand:SD 0 "nonimmediate_operand" "=f")
45 (unspec:SD [(match_operand:DD 1 "input_operand" "m")] 44 (unspec:SD [(match_operand:DD 1 "input_operand" "m")]
46 UNSPEC_MOVSD_LOAD))] 45 UNSPEC_MOVSD_LOAD))]
47 "(gpc_reg_operand (operands[0], SDmode) 46 "(gpc_reg_operand (operands[0], SDmode)
48 || gpc_reg_operand (operands[1], DDmode)) 47 || gpc_reg_operand (operands[1], DDmode))
49 && TARGET_HARD_FLOAT" 48 && TARGET_HARD_FLOAT"
50 "lfd%U1%X1 %0,%1" 49 "lfd%U1%X1 %0,%1"
51 [(set_attr "type" "fpload") 50 [(set_attr "type" "fpload")])
52 (set_attr "length" "4")])
53 51
54 ;; Hardware support for decimal floating point operations. 52 ;; Hardware support for decimal floating point operations.
55 53
56 (define_insn "extendsddd2" 54 (define_insn "extendsddd2"
57 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") 55 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
342 340
343 (define_expand "dfptstsfi_<code>_<mode>" 341 (define_expand "dfptstsfi_<code>_<mode>"
344 [(set (match_dup 3) 342 [(set (match_dup 3)
345 (compare:CCFP 343 (compare:CCFP
346 (unspec:D64_D128 344 (unspec:D64_D128
347 [(match_operand:SI 1 "const_int_operand" "n") 345 [(match_operand:SI 1 "const_int_operand")
348 (match_operand:D64_D128 2 "gpc_reg_operand" "d")] 346 (match_operand:D64_D128 2 "gpc_reg_operand")]
349 UNSPEC_DTSTSFI) 347 UNSPEC_DTSTSFI)
350 (match_dup 4))) 348 (match_dup 4)))
351 (set (match_operand:SI 0 "register_operand" "") 349 (set (match_operand:SI 0 "register_operand")
352 (DFP_TEST:SI (match_dup 3) 350 (DFP_TEST:SI (match_dup 3)
353 (const_int 0))) 351 (const_int 0)))
354 ] 352 ]
355 "TARGET_P9_MISC" 353 "TARGET_P9_MISC"
356 { 354 {