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comparison gcc/config/mips/mips.h @ 63:b7f97abdc517 gcc-4.6-20100522

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update gcc from gcc-4.5.0 to gcc-4.6
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Mon, 24 May 2010 12:47:05 +0900
parents 77e2b8dfacca
children f6334be47118
comparison
equal deleted inserted replaced
56:3c8a44c06a95 63:b7f97abdc517
1 /* Definitions of target machine for GNU compiler. MIPS version. 1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998 2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc. 4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr). 5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org). 6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and 7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com). 8 Brendan Eich (brendan@microunity.com).
226 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64). 226 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
227 We therefore disable GP-relative switch tables for n64 on IRIX targets. */ 227 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
228 #define TARGET_GPWORD \ 228 #define TARGET_GPWORD \
229 (TARGET_ABICALLS \ 229 (TARGET_ABICALLS \
230 && !TARGET_ABSOLUTE_ABICALLS \ 230 && !TARGET_ABSOLUTE_ABICALLS \
231 && !(mips_abi == ABI_64 && TARGET_IRIX)) 231 && !(mips_abi == ABI_64 && TARGET_IRIX6))
232 232
233 /* True if the output must have a writable .eh_frame. 233 /* True if the output must have a writable .eh_frame.
234 See ASM_PREFERRED_EH_DATA_FORMAT for details. */ 234 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
235 #ifdef HAVE_LD_PERSONALITY_RELAXATION 235 #ifdef HAVE_LD_PERSONALITY_RELAXATION
236 #define TARGET_WRITABLE_EH_FRAME 0 236 #define TARGET_WRITABLE_EH_FRAME 0
367 stores prior to and following the SC, only about the SC itself and 367 stores prior to and following the SC, only about the SC itself and
368 those loads and stores follow it. */ 368 those loads and stores follow it. */
369 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON) 369 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON)
370 370
371 /* IRIX specific stuff. */ 371 /* IRIX specific stuff. */
372 #define TARGET_IRIX 0
373 #define TARGET_IRIX6 0 372 #define TARGET_IRIX6 0
374 373
375 /* Define preprocessor macros for the -march and -mtune options. 374 /* Define preprocessor macros for the -march and -mtune options.
376 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected 375 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
377 processor. If INFO's canonical name is "foo", define PREFIX to 376 processor. If INFO's canonical name is "foo", define PREFIX to
394 /* Target CPU builtins. */ 393 /* Target CPU builtins. */
395 #define TARGET_CPU_CPP_BUILTINS() \ 394 #define TARGET_CPU_CPP_BUILTINS() \
396 do \ 395 do \
397 { \ 396 { \
398 /* Everyone but IRIX defines this to mips. */ \ 397 /* Everyone but IRIX defines this to mips. */ \
399 if (!TARGET_IRIX) \ 398 if (!TARGET_IRIX6) \
400 builtin_assert ("machine=mips"); \ 399 builtin_assert ("machine=mips"); \
401 \ 400 \
402 builtin_assert ("cpu=mips"); \ 401 builtin_assert ("cpu=mips"); \
403 builtin_define ("__mips__"); \ 402 builtin_define ("__mips__"); \
404 builtin_define ("_mips"); \ 403 builtin_define ("_mips"); \
414 builtin_define ("mips"); \ 413 builtin_define ("mips"); \
415 \ 414 \
416 if (TARGET_64BIT) \ 415 if (TARGET_64BIT) \
417 builtin_define ("__mips64"); \ 416 builtin_define ("__mips64"); \
418 \ 417 \
419 if (!TARGET_IRIX) \ 418 if (!TARGET_IRIX6) \
420 { \ 419 { \
421 /* Treat _R3000 and _R4000 like register-size \ 420 /* Treat _R3000 and _R4000 like register-size \
422 defines, which is how they've historically \ 421 defines, which is how they've historically \
423 been used. */ \ 422 been used. */ \
424 if (TARGET_64BIT) \ 423 if (TARGET_64BIT) \
535 builtin_define_with_int_value ("_MIPS_FPSET", \ 534 builtin_define_with_int_value ("_MIPS_FPSET", \
536 32 / MAX_FPRS_PER_FMT); \ 535 32 / MAX_FPRS_PER_FMT); \
537 \ 536 \
538 /* These defines reflect the ABI in use, not whether the \ 537 /* These defines reflect the ABI in use, not whether the \
539 FPU is directly accessible. */ \ 538 FPU is directly accessible. */ \
540 if (TARGET_HARD_FLOAT_ABI) \ 539 if (TARGET_NO_FLOAT) \
540 builtin_define ("__mips_no_float"); \
541 else if (TARGET_HARD_FLOAT_ABI) \
541 builtin_define ("__mips_hard_float"); \ 542 builtin_define ("__mips_hard_float"); \
542 else \ 543 else \
543 builtin_define ("__mips_soft_float"); \ 544 builtin_define ("__mips_soft_float"); \
544 \ 545 \
545 if (TARGET_SINGLE_FLOAT) \ 546 if (TARGET_SINGLE_FLOAT) \
2004 factor or added to another register (as well as added to a 2005 factor or added to another register (as well as added to a
2005 displacement). */ 2006 displacement). */
2006 2007
2007 #define INDEX_REG_CLASS NO_REGS 2008 #define INDEX_REG_CLASS NO_REGS
2008 2009
2009 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2010 registers explicitly used in the rtl to be used as spill registers
2011 but prevents the compiler from extending the lifetime of these
2012 registers. */
2013
2014 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2015
2016 /* We generally want to put call-clobbered registers ahead of 2010 /* We generally want to put call-clobbered registers ahead of
2017 call-saved ones. (IRA expects this.) */ 2011 call-saved ones. (IRA expects this.) */
2018 2012
2019 #define REG_ALLOC_ORDER \ 2013 #define REG_ALLOC_ORDER \
2020 { /* Accumulator registers. When GPRs and accumulators have equal \ 2014 { /* Accumulator registers. When GPRs and accumulators have equal \
2057 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \ 2051 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2058 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \ 2052 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2059 182,183,184,185,186,187 \ 2053 182,183,184,185,186,187 \
2060 } 2054 }
2061 2055
2062 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 2056 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
2063 to be rearranged based on a particular function. On the mips16, we 2057 to be rearranged based on a particular function. On the mips16, we
2064 want to allocate $24 (T_REG) before other registers for 2058 want to allocate $24 (T_REG) before other registers for
2065 instructions for which it is possible. */ 2059 instructions for which it is possible. */
2066 2060
2067 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc () 2061 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
2068 2062
2069 /* True if VALUE is an unsigned 6-bit number. */ 2063 /* True if VALUE is an unsigned 6-bit number. */
2070 2064
2071 #define UIMM6_OPERAND(VALUE) \ 2065 #define UIMM6_OPERAND(VALUE) \
2072 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0) 2066 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)