Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/pa/pa64-regs.h @ 67:f6334be47118

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents a06113de4d67
children 04ced10e8804
comparison
equal deleted inserted replaced
65:65488c3d617d 67:f6334be47118
1 /* Configuration for GCC-compiler for PA-RISC. 1 /* Configuration for GCC-compiler for PA-RISC.
2 Copyright (C) 1999, 2000, 2003, 2004, 2007, 2008 2 Copyright (C) 1999, 2000, 2003, 2004, 2007, 2008, 2010
3 Free Software Foundation, Inc. 3 Free Software Foundation, Inc.
4 4
5 This file is part of GCC. 5 This file is part of GCC.
6 6
7 GCC is free software; you can redistribute it and/or modify 7 GCC is free software; you can redistribute it and/or modify
36 Due to limitations within GCC itself, we do not expose the left/right 36 Due to limitations within GCC itself, we do not expose the left/right
37 half addressability when in wide mode. This is not a major performance 37 half addressability when in wide mode. This is not a major performance
38 issue as using the halves independently triggers false dependency stalls 38 issue as using the halves independently triggers false dependency stalls
39 anyway. */ 39 anyway. */
40 40
41 #define FIRST_PSEUDO_REGISTER 61 /* 32 general regs + 28 fp regs + 41 #define FIRST_PSEUDO_REGISTER 62 /* 32 general regs + 28 fp regs +
42 + 1 shift reg */ 42 + 1 shift reg + frame pointer */
43 43
44 /* 1 for registers that have pervasive standard uses 44 /* 1 for registers that have pervasive standard uses
45 and are not available for the register allocator. 45 and are not available for the register allocator.
46 46
47 On the HP-PA, these are: 47 On the HP-PA, these are:
77 /* fp registers */ \ 77 /* fp registers */ \
78 0, 0, 0, 0, 0, 0, 0, 0, \ 78 0, 0, 0, 0, 0, 0, 0, 0, \
79 0, 0, 0, 0, 0, 0, 0, 0, \ 79 0, 0, 0, 0, 0, 0, 0, 0, \
80 0, 0, 0, 0, 0, 0, 0, 0, \ 80 0, 0, 0, 0, 0, 0, 0, 0, \
81 0, 0, 0, 0, \ 81 0, 0, 0, 0, \
82 /* shift register */ \ 82 /* shift register and soft frame pointer */ \
83 0} 83 0, 1}
84 84
85 /* 1 for registers not available across function calls. 85 /* 1 for registers not available across function calls.
86 These must include the FIXED_REGISTERS and also any 86 These must include the FIXED_REGISTERS and also any
87 registers that can be used without being saved. 87 registers that can be used without being saved.
88 The latter must include the registers where values are returned 88 The latter must include the registers where values are returned
96 /* fp registers */ \ 96 /* fp registers */ \
97 1, 1, 1, 1, 1, 1, 1, 1, \ 97 1, 1, 1, 1, 1, 1, 1, 1, \
98 0, 0, 0, 0, 0, 0, 0, 0, \ 98 0, 0, 0, 0, 0, 0, 0, 0, \
99 0, 0, 1, 1, 1, 1, 1, 1, \ 99 0, 0, 1, 1, 1, 1, 1, 1, \
100 1, 1, 1, 1, \ 100 1, 1, 1, 1, \
101 /* shift register */ \ 101 /* shift register and soft frame pointer */ \
102 1} 102 1, 1}
103
104 #define CONDITIONAL_REGISTER_USAGE \
105 { \
106 int i; \
107 if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\
108 { \
109 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)\
110 fixed_regs[i] = call_used_regs[i] = 1; \
111 } \
112 if (flag_pic) \
113 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
114 }
115 103
116 /* Allocate the call used registers first. This should minimize 104 /* Allocate the call used registers first. This should minimize
117 the number of registers that need to be saved (as call used 105 the number of registers that need to be saved (as call used
118 registers will generally not be allocated across a call). 106 registers will generally not be allocated across a call).
119 107
135 48, 49, \ 123 48, 49, \
136 /* callee-saved general regs. */ \ 124 /* callee-saved general regs. */ \
137 3, 4, 5, 6, 7, 8, 9, 10, \ 125 3, 4, 5, 6, 7, 8, 9, 10, \
138 11, 12, 13, 14, 15, 16, 17, 18, \ 126 11, 12, 13, 14, 15, 16, 17, 18, \
139 /* special registers. */ \ 127 /* special registers. */ \
140 1, 27, 30, 0, 60} 128 1, 27, 30, 0, 60, 61}
141 129
142 130
143 /* Return number of consecutive hard regs needed starting at reg REGNO 131 /* Return number of consecutive hard regs needed starting at reg REGNO
144 to hold something of mode MODE. 132 to hold something of mode MODE.
145 This is ordinarily the length in words of a value of mode MODE 133 This is ordinarily the length in words of a value of mode MODE
233 is in no class. */ 221 is in no class. */
234 222
235 #define REG_CLASS_CONTENTS \ 223 #define REG_CLASS_CONTENTS \
236 {{0x00000000, 0x00000000}, /* NO_REGS */ \ 224 {{0x00000000, 0x00000000}, /* NO_REGS */ \
237 {0x00000002, 0x00000000}, /* R1_REGS */ \ 225 {0x00000002, 0x00000000}, /* R1_REGS */ \
238 {0xfffffffe, 0x00000000}, /* GENERAL_REGS */ \ 226 {0xfffffffe, 0x20000000}, /* GENERAL_REGS */ \
239 {0x00000000, 0x00000000}, /* FPUPPER_REGS */ \ 227 {0x00000000, 0x00000000}, /* FPUPPER_REGS */ \
240 {0x00000000, 0x0fffffff}, /* FP_REGS */ \ 228 {0x00000000, 0x0fffffff}, /* FP_REGS */ \
241 {0xfffffffe, 0x0fffffff}, /* GENERAL_OR_FP_REGS */ \ 229 {0xfffffffe, 0x2fffffff}, /* GENERAL_OR_FP_REGS */ \
242 {0x00000000, 0x10000000}, /* SHIFT_REGS */ \ 230 {0x00000000, 0x10000000}, /* SHIFT_REGS */ \
243 {0xfffffffe, 0x1fffffff}} /* ALL_REGS */ 231 {0xfffffffe, 0x3fffffff}} /* ALL_REGS */
244 232
245 /* The following macro defines cover classes for Integrated Register 233 /* The following macro defines cover classes for Integrated Register
246 Allocator. Cover classes is a set of non-intersected register 234 Allocator. Cover classes is a set of non-intersected register
247 classes covering all hard registers used for register allocation 235 classes covering all hard registers used for register allocation
248 purpose. Any move between two registers of a cover class should be 236 purpose. Any move between two registers of a cover class should be
265 or could index an array. */ 253 or could index an array. */
266 254
267 #define REGNO_REG_CLASS(REGNO) \ 255 #define REGNO_REG_CLASS(REGNO) \
268 ((REGNO) == 0 ? NO_REGS \ 256 ((REGNO) == 0 ? NO_REGS \
269 : (REGNO) == 1 ? R1_REGS \ 257 : (REGNO) == 1 ? R1_REGS \
270 : (REGNO) < 32 ? GENERAL_REGS \ 258 : (REGNO) < 32 || (REGNO) == 61 ? GENERAL_REGS \
271 : (REGNO) < 60 ? FP_REGS \ 259 : (REGNO) < 60 ? FP_REGS \
272 : SHIFT_REGS) 260 : SHIFT_REGS)
273 261
274 /* Return the maximum number of consecutive registers 262 /* Return the maximum number of consecutive registers
275 needed to represent mode MODE in a register of class CLASS. */ 263 needed to represent mode MODE in a register of class CLASS. */
291 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", \ 279 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", \
292 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", \ 280 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", \
293 "%fr4", "%fr5", "%fr6", "%fr7", "%fr8", "%fr9", "%fr10", "%fr11", \ 281 "%fr4", "%fr5", "%fr6", "%fr7", "%fr8", "%fr9", "%fr10", "%fr11", \
294 "%fr12", "%fr13", "%fr14", "%fr15", "%fr16", "%fr17", "%fr18", "%fr19", \ 282 "%fr12", "%fr13", "%fr14", "%fr15", "%fr16", "%fr17", "%fr18", "%fr19", \
295 "%fr20", "%fr21", "%fr22", "%fr23", "%fr24", "%fr25", "%fr26", "%fr27", \ 283 "%fr20", "%fr21", "%fr22", "%fr23", "%fr24", "%fr25", "%fr26", "%fr27", \
296 "%fr28", "%fr29", "%fr30", "%fr31", "SAR"} 284 "%fr28", "%fr29", "%fr30", "%fr31", "SAR", "sfp"}
297 285
298 #define ADDITIONAL_REGISTER_NAMES \ 286 #define ADDITIONAL_REGISTER_NAMES \
299 {{"%cr11",60}} 287 {{"%cr11",60}}
300 288
301 #define FP_SAVED_REG_LAST 49 289 #define FP_SAVED_REG_LAST 49