--- a/gcc/config/msp430/msp430.h	Thu Oct 25 07:37:49 2018 +0900
+++ b/gcc/config/msp430/msp430.h	Thu Feb 13 11:34:05 2020 +0900
@@ -1,5 +1,5 @@
 /* GCC backend definitions for the TI MSP430 Processor
-   Copyright (C) 2012-2018 Free Software Foundation, Inc.
+   Copyright (C) 2012-2020 Free Software Foundation, Inc.
    Contributed by Red Hat.
 
    This file is part of GCC.
@@ -26,10 +26,10 @@
 extern bool msp430x;
 #endif
 
-#define TARGET_CPU_CPP_BUILTINS()               \
-  do                                            \
-    {                                           \
-      builtin_define ("NO_TRAMPOLINES");        \
+#define TARGET_CPU_CPP_BUILTINS()		\
+  do						\
+    {						\
+      builtin_define ("NO_TRAMPOLINES");	\
       builtin_define ("__MSP430__"); 		\
       builtin_define (msp430_mcu_name ());	\
       if (msp430x)				\
@@ -41,35 +41,80 @@
 	}					\
       else					\
 	builtin_assert ("cpu=MSP430"); 		\
-    }                                           \
+    }						\
   while (0)
 
+/* For the "c" language where exceptions are implicitly disabled, use
+   crt*_no_eh.o unless -fexceptions is passed.  For other languages, only use
+   crt*_no_eh.o if -fno-exceptions is explicitly passed.  */
 #undef  STARTFILE_SPEC
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{minrt:crt0-minrt.o%s}%{!minrt:crt0.o%s}} %{!minrt:crtbegin.o%s}"
+#define STARTFILE_SPEC "%{pg:gcrt0.o%s}" \
+  "%{!pg:%{minrt:crt0-minrt.o%s}%{!minrt:crt0.o%s}} " \
+  "%{!minrt:%{,c:%{!fexceptions:crtbegin_no_eh.o%s; :crtbegin.o%s}; " \
+    ":%{fno-exceptions:crtbegin_no_eh.o%s; :crtbegin.o%s}}}"
 
 /* -lgcc is included because crtend.o needs __mspabi_func_epilog_1.  */
 #undef  ENDFILE_SPEC
-#define ENDFILE_SPEC "%{!minrt:crtend.o%s} %{minrt:crtn-minrt.o%s}%{!minrt:crtn.o%s} -lgcc"
+#define ENDFILE_SPEC \
+  "%{!minrt:%{,c:%{!fexceptions:crtend_no_eh.o%s; :crtend.o%s}; " \
+    ":%{fno-exceptions:crtend_no_eh.o%s; :crtend.o%s}}} " \
+  "%{minrt:%:if-exists(crtn-minrt.o%s)}%{!minrt:%:if-exists(crtn.o%s)} -lgcc"
 
 #define ASM_SPEC "-mP " /* Enable polymorphic instructions.  */ \
-  "%{mcpu=*:-mcpu=%*}%{!mcpu=*:%{mmcu=*:-mmcu=%*}} " /* Pass the CPU type on to the assembler.  */ \
+  "%{mcpu=*:-mcpu=%*} " /* Pass the CPU type on to the assembler.  */ \
   "%{mrelax=-mQ} " /* Pass the relax option on to the assembler.  */ \
-  "%{mlarge:-ml} " /* Tell the assembler if we are building for the LARGE pointer model.  */ \
-  "%{!msim:-md} %{msim:%{mlarge:-md}} " /* Copy data from ROM to RAM if necessary.  */ \
-  "%{msilicon-errata=*:-msilicon-errata=%*} " /* Pass on -msilicon-errata.  */ \
-  "%{msilicon-errata-warn=*:-msilicon-errata-warn=%*} " /* Pass on -msilicon-errata-warn.  */ \
-  "%{ffunction-sections:-gdwarf-sections} " /* If function sections are being created then create DWARF line number sections as well.  */ \
-  "%{mdata-region=*:-mdata-region=%*} " /* Pass on -mdata-region.  */
+  /* Tell the assembler if we are building for the LARGE pointer model.  */ \
+  "%{mlarge:-ml} " \
+  /* Copy data from ROM to RAM if necessary.  */ \
+  "%{!msim:-md} %{msim:%{mlarge:-md}} " \
+  "%{msilicon-errata=*:-msilicon-errata=%*} " \
+  "%{msilicon-errata-warn=*:-msilicon-errata-warn=%*} " \
+  /* Create DWARF line number sections for -ffunction-sections.  */ \
+  "%{ffunction-sections:-gdwarf-sections} " \
+  "%{mdata-region=*:-mdata-region=%*} "
 
 /* Enable linker section garbage collection by default, unless we
    are creating a relocatable binary (gc does not work) or debugging
-   is enabled  (the GDB testsuite relies upon unused entities not being deleted).  */
+   is enabled  (the GDB testsuite relies upon unused entities not being
+   deleted).  */
 #define LINK_SPEC "%{mrelax:--relax} %{mlarge:%{!r:%{!g:--gc-sections}}} " \
-  "%{mcode-region=*:--code-region=%*} %{mdata-region=*:--data-region=%*}"
+  "%{mcode-region=*:--code-region=%:" \
+    "msp430_propagate_region_opt(%* %{muse-lower-region-prefix})} " \
+  "%{mdata-region=*:--data-region=%:" \
+    "msp430_propagate_region_opt(%* %{muse-lower-region-prefix})} " \
+  "%:msp430_get_linker_devices_include_path() " \
+  "%{mtiny-printf:--wrap puts --wrap printf} "
+
+#define DRIVER_SELF_SPECS \
+  " %{!mlarge:%{mcode-region=*:%{mdata-region=*:%e-mcode-region and "	\
+    "-mdata-region require the large memory model (-mlarge)}}}" \
+  " %{!mlarge:%{mcode-region=*:"	\
+    "%e-mcode-region requires the large memory model (-mlarge)}}"	\
+  " %{!mlarge:%{mdata-region=*:"	\
+    "%e-mdata-region requires the large memory model (-mlarge)}}"	\
+  " %{mno-warn-devices-csv:%:msp430_set_driver_var(msp430_warn_devices_csv 0)}"\
+  " %{mdevices-csv-loc=*:%:msp430_set_driver_var(msp430_devices_csv_loc %*)}"\
+  " %{I*:%:msp430_check_path_for_devices(%{I*:%*})}"       \
+  " %{L*:%:msp430_check_path_for_devices(%{L*:%*})}"       \
+  " %{!mcpu=*:%{mmcu=*:%:msp430_select_cpu(%{mmcu=*:%*})}}"
 
 extern const char * msp430_select_hwmult_lib (int, const char **);
+extern const char * msp430_select_cpu (int, const char **);
+extern const char * msp430_set_driver_var (int, const char **);
+extern const char * msp430_check_path_for_devices (int, const char **);
+extern const char *msp430_propagate_region_opt (int, const char **);
+extern const char *msp430_get_linker_devices_include_path (int, const char **);
+
+/* There must be a trailing comma after the last item, see gcc.c
+   "static_spec_functions".  */
 # define EXTRA_SPEC_FUNCTIONS				\
-  { "msp430_hwmult_lib", msp430_select_hwmult_lib },
+  { "msp430_hwmult_lib", msp430_select_hwmult_lib },	\
+  { "msp430_select_cpu", msp430_select_cpu },		\
+  { "msp430_set_driver_var", msp430_set_driver_var },		\
+  { "msp430_check_path_for_devices", msp430_check_path_for_devices }, \
+  { "msp430_propagate_region_opt", msp430_propagate_region_opt }, \
+  { "msp430_get_linker_devices_include_path", \
+    msp430_get_linker_devices_include_path },
 
 /* Specify the libraries to include on the linker command line.
 
@@ -89,7 +134,8 @@
 #undef  LIB_SPEC
 #define LIB_SPEC "					\
 --start-group						\
-%{mhwmult=auto:%{mmcu=*:%:msp430_hwmult_lib(mcu %{mmcu=*:%*});:%:msp430_hwmult_lib(default)}; \
+%{mhwmult=auto:%{mmcu=*:%:msp430_hwmult_lib(mcu %{mmcu=*:%*});\
+  :%:msp430_hwmult_lib(default)};			\
   mhwmult=*:%:msp430_hwmult_lib(hwmult %{mhwmult=*:%*}); \
   mmcu=*:%:msp430_hwmult_lib(mcu %{mmcu=*:%*});		\
   :%:msp430_hwmult_lib(default)}			\
@@ -159,6 +205,11 @@
 #define PTR_SIZE			(TARGET_LARGE ? 4 : 2)
 #define	POINTERS_EXTEND_UNSIGNED	1
 
+/* TARGET_VTABLE_ENTRY_ALIGN defaults to POINTER_SIZE, which is 20 for
+   TARGET_LARGE.  Pointer alignment is always 16 for MSP430, so set explicitly
+   here.  */
+#define TARGET_VTABLE_ENTRY_ALIGN 16
+
 #define ADDR_SPACE_NEAR	1
 #define ADDR_SPACE_FAR	2
 
@@ -180,9 +231,11 @@
 /* Layout of Source Language Data Types */
 
 #undef  SIZE_TYPE
-#define SIZE_TYPE			(TARGET_LARGE ? "__int20 unsigned" : "unsigned int")
+#define SIZE_TYPE			(TARGET_LARGE \
+					 ? "__int20__ unsigned" \
+					 : "unsigned int")
 #undef  PTRDIFF_TYPE
-#define PTRDIFF_TYPE			(TARGET_LARGE ? "__int20" : "int")
+#define PTRDIFF_TYPE			(TARGET_LARGE ? "__int20__" : "int")
 #undef  WCHAR_TYPE
 #define WCHAR_TYPE			"long int"
 #undef  WCHAR_TYPE_SIZE
@@ -217,6 +270,28 @@
   "argptr"							\
 }
 
+/* Allow lowercase "r" to be used in register names instead of upper
+   case "R".  */
+#define ADDITIONAL_REGISTER_NAMES	\
+{					\
+    { "r0",  0 },			\
+    { "r1",  1 },			\
+    { "r2",  2 },			\
+    { "r3",  3 },			\
+    { "r4",  4 },			\
+    { "r5",  5 },			\
+    { "r6",  6 },			\
+    { "r7",  7 },			\
+    { "r8",  8 },			\
+    { "r9",  9 },			\
+    { "r10", 10 },			\
+    { "r11", 11 },			\
+    { "r12", 12 },			\
+    { "r13", 13 },			\
+    { "r14", 14 },			\
+    { "r15", 15 }			\
+}
+
 enum reg_class
 {
   NO_REGS,
@@ -241,25 +316,32 @@
   0x00000000,		   \
   0x00001000,		   \
   0x00002000,		   \
-  0x0000fff2,		   \
+  0x0000fff3,		   \
   0x0001ffff		   \
 }
 
+/* GENERAL_REGS just means that the "g" and "r" constraints can use these
+   registers.
+   Even though R0 (PC) and R1 (SP) are not "general" in that they can be used
+   for any purpose by the register allocator, they are general in that they can
+   be used by any instruction in any addressing mode.  */
 #define GENERAL_REGS			GEN_REGS
 #define BASE_REG_CLASS  		GEN_REGS
 #define INDEX_REG_CLASS			GEN_REGS
 #define N_REG_CLASSES			(int) LIM_REG_CLASSES
 
-#define PC_REGNUM 		        0
-#define STACK_POINTER_REGNUM 	        1
-#define CC_REGNUM                       2
+#define PC_REGNUM			0
+#define STACK_POINTER_REGNUM		1
+#define CC_REGNUM 			2
 #define FRAME_POINTER_REGNUM 		4 /* not usually used, call preserved */
 #define ARG_POINTER_REGNUM 		16
 #define STATIC_CHAIN_REGNUM 		5 /* FIXME */
 
 #define FIRST_PSEUDO_REGISTER 		17
 
-#define REGNO_REG_CLASS(REGNO)          ((REGNO) < 17 \
+#define REGNO_REG_CLASS(REGNO)		(REGNO != 2 \
+					 && REGNO != 3 \
+					 && REGNO < 17 \
 					 ? GEN_REGS : NO_REGS)
 
 #define TRAMPOLINE_SIZE			4 /* FIXME */
@@ -338,7 +420,8 @@
   (((N) < 3) ? ((N) + 12) : INVALID_REGNUM)
 
 #define EH_RETURN_HANDLER_RTX \
-  gen_rtx_MEM(Pmode, gen_rtx_PLUS (Pmode, gen_rtx_REG(Pmode, SP_REGNO), gen_rtx_REG (Pmode, 15)))
+  gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, SP_REGNO), \
+				   gen_rtx_REG (Pmode, 15)))
 
 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 15)
 
@@ -382,7 +465,7 @@
   do						\
     {						\
       if ((LOG) == 0)				\
-        break;					\
+	break;					\
       fprintf (STREAM, "\t.balign %d\n", 1 << (LOG));	\
     }						\
   while (0)
@@ -402,18 +485,39 @@
 /* Prevent reload (and others) from choosing HImode stack slots
    when spilling hard registers when they may contain PSImode values.  */
 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO,NREGS,MODE) \
-  ((TARGET_LARGE && ((NREGS) <= 2)) ? PSImode : choose_hard_reg_mode ((REGNO), (NREGS), false))
+  ((TARGET_LARGE && ((NREGS) <= 2)) ? PSImode \
+   : choose_hard_reg_mode ((REGNO), (NREGS), NULL))
 
 #define ACCUMULATE_OUTGOING_ARGS 1
 
+#define HAVE_POST_INCREMENT 1
+
+/* This (unsurprisingly) improves code size in the vast majority of cases, we
+   want to prevent any instructions using a "store post increment" from being
+   generated.  These will have to later be reloaded since msp430 does not
+   support post inc for the destination operand.  */
+#define USE_STORE_POST_INCREMENT(MODE)  0
+
+/* Many other targets set USE_LOAD_POST_INCREMENT to 0.  For msp430-elf
+   the benefit of disabling it is not clear.  When looking at code size, on
+   average, there is a slight advantage to leaving it enabled.  */
+
 #undef  ASM_DECLARE_FUNCTION_NAME
 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
   msp430_start_function ((FILE), (NAME), (DECL))
 
 #define TARGET_HAS_NO_HW_DIVIDE (! TARGET_HWMULT)
 
+void msp430_register_pre_includes (const char *sysroot ATTRIBUTE_UNUSED,
+				   const char *iprefix ATTRIBUTE_UNUSED,
+				   int stdinc ATTRIBUTE_UNUSED);
+#undef TARGET_EXTRA_PRE_INCLUDES
+#define TARGET_EXTRA_PRE_INCLUDES msp430_register_pre_includes
+
 #undef  USE_SELECT_SECTION_FOR_FUNCTIONS
 #define USE_SELECT_SECTION_FOR_FUNCTIONS 1
 
 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(FILE, DECL, NAME, SIZE, ALIGN)	\
   msp430_output_aligned_decl_common ((FILE), (DECL), (NAME), (SIZE), (ALIGN))
+
+#define SYMBOL_FLAG_LOW_MEM (SYMBOL_FLAG_MACH_DEP << 0)