Mercurial > hg > CbC > CbC_gcc
annotate gcc/caller-save.c @ 111:04ced10e8804
gcc 7
| author | kono |
|---|---|
| date | Fri, 27 Oct 2017 22:46:09 +0900 |
| parents | f6334be47118 |
| children | 84e7813d76e9 |
| rev | line source |
|---|---|
| 0 | 1 /* Save and restore call-clobbered registers which are live across a call. |
| 111 | 2 Copyright (C) 1989-2017 Free Software Foundation, Inc. |
| 0 | 3 |
| 4 This file is part of GCC. | |
| 5 | |
| 6 GCC is free software; you can redistribute it and/or modify it under | |
| 7 the terms of the GNU General Public License as published by the Free | |
| 8 Software Foundation; either version 3, or (at your option) any later | |
| 9 version. | |
| 10 | |
| 11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
| 12 WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 14 for more details. | |
| 15 | |
| 16 You should have received a copy of the GNU General Public License | |
| 17 along with GCC; see the file COPYING3. If not see | |
| 18 <http://www.gnu.org/licenses/>. */ | |
| 19 | |
| 20 #include "config.h" | |
| 21 #include "system.h" | |
| 22 #include "coretypes.h" | |
| 111 | 23 #include "backend.h" |
| 0 | 24 #include "rtl.h" |
| 111 | 25 #include "tree.h" |
| 26 #include "predict.h" | |
|
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27 #include "df.h" |
| 111 | 28 #include "memmodel.h" |
| 29 #include "tm_p.h" | |
| 30 #include "insn-config.h" | |
| 31 #include "regs.h" | |
| 32 #include "emit-rtl.h" | |
| 33 #include "recog.h" | |
| 0 | 34 #include "reload.h" |
| 111 | 35 #include "alias.h" |
| 0 | 36 #include "addresses.h" |
| 111 | 37 #include "dumpfile.h" |
| 38 #include "rtl-iter.h" | |
| 39 #include "target.h" | |
| 0 | 40 |
| 41 #define MOVE_MAX_WORDS (MOVE_MAX / UNITS_PER_WORD) | |
| 42 | |
|
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43 #define regno_save_mode \ |
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44 (this_target_reload->x_regno_save_mode) |
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45 #define cached_reg_save_code \ |
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46 (this_target_reload->x_cached_reg_save_code) |
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47 #define cached_reg_restore_code \ |
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48 (this_target_reload->x_cached_reg_restore_code) |
| 0 | 49 |
| 50 /* For each hard register, a place on the stack where it can be saved, | |
| 51 if needed. */ | |
| 52 | |
| 53 static rtx | |
| 54 regno_save_mem[FIRST_PSEUDO_REGISTER][MAX_MOVE_MAX / MIN_UNITS_PER_WORD + 1]; | |
| 55 | |
| 56 /* The number of elements in the subsequent array. */ | |
| 57 static int save_slots_num; | |
| 58 | |
| 59 /* Allocated slots so far. */ | |
| 60 static rtx save_slots[FIRST_PSEUDO_REGISTER]; | |
| 61 | |
| 62 /* Set of hard regs currently residing in save area (during insn scan). */ | |
| 63 | |
| 64 static HARD_REG_SET hard_regs_saved; | |
| 65 | |
| 66 /* Number of registers currently in hard_regs_saved. */ | |
| 67 | |
| 68 static int n_regs_saved; | |
| 69 | |
| 70 /* Computed by mark_referenced_regs, all regs referenced in a given | |
| 71 insn. */ | |
| 72 static HARD_REG_SET referenced_regs; | |
| 73 | |
| 74 | |
| 111 | 75 typedef void refmarker_fn (rtx *loc, machine_mode mode, int hardregno, |
|
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76 void *mark_arg); |
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77 |
| 111 | 78 static int reg_save_code (int, machine_mode); |
| 79 static int reg_restore_code (int, machine_mode); | |
| 0 | 80 |
| 81 struct saved_hard_reg; | |
| 82 static void initiate_saved_hard_regs (void); | |
| 111 | 83 static void new_saved_hard_reg (int, int); |
| 0 | 84 static void finish_saved_hard_regs (void); |
| 85 static int saved_hard_reg_compare_func (const void *, const void *); | |
| 86 | |
| 87 static void mark_set_regs (rtx, const_rtx, void *); | |
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88 static void mark_referenced_regs (rtx *, refmarker_fn *mark, void *mark_arg); |
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89 static refmarker_fn mark_reg_as_referenced; |
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90 static refmarker_fn replace_reg_with_saved_mem; |
| 0 | 91 static int insert_save (struct insn_chain *, int, int, HARD_REG_SET *, |
| 111 | 92 machine_mode *); |
| 0 | 93 static int insert_restore (struct insn_chain *, int, int, int, |
| 111 | 94 machine_mode *); |
| 0 | 95 static struct insn_chain *insert_one_insn (struct insn_chain *, int, int, |
| 96 rtx); | |
| 97 static void add_stored_regs (rtx, const_rtx, void *); | |
| 98 | |
| 99 | |
| 100 | |
| 101 static GTY(()) rtx savepat; | |
| 102 static GTY(()) rtx restpat; | |
| 103 static GTY(()) rtx test_reg; | |
| 104 static GTY(()) rtx test_mem; | |
| 111 | 105 static GTY(()) rtx_insn *saveinsn; |
| 106 static GTY(()) rtx_insn *restinsn; | |
| 0 | 107 |
| 108 /* Return the INSN_CODE used to save register REG in mode MODE. */ | |
| 109 static int | |
| 111 | 110 reg_save_code (int reg, machine_mode mode) |
| 0 | 111 { |
| 112 bool ok; | |
| 113 if (cached_reg_save_code[reg][mode]) | |
| 114 return cached_reg_save_code[reg][mode]; | |
| 111 | 115 if (!targetm.hard_regno_mode_ok (reg, mode)) |
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116 { |
| 111 | 117 /* Depending on how targetm.hard_regno_mode_ok is defined, range |
| 118 propagation might deduce here that reg >= FIRST_PSEUDO_REGISTER. | |
| 119 So the assert below silences a warning. */ | |
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120 gcc_assert (reg < FIRST_PSEUDO_REGISTER); |
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121 cached_reg_save_code[reg][mode] = -1; |
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122 cached_reg_restore_code[reg][mode] = -1; |
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123 return -1; |
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124 } |
| 0 | 125 |
| 126 /* Update the register number and modes of the register | |
| 127 and memory operand. */ | |
| 111 | 128 set_mode_and_regno (test_reg, mode, reg); |
| 0 | 129 PUT_MODE (test_mem, mode); |
| 130 | |
| 131 /* Force re-recognition of the modified insns. */ | |
| 132 INSN_CODE (saveinsn) = -1; | |
| 133 INSN_CODE (restinsn) = -1; | |
| 134 | |
| 135 cached_reg_save_code[reg][mode] = recog_memoized (saveinsn); | |
| 136 cached_reg_restore_code[reg][mode] = recog_memoized (restinsn); | |
| 137 | |
| 138 /* Now extract both insns and see if we can meet their | |
| 111 | 139 constraints. We don't know here whether the save and restore will |
| 140 be in size- or speed-tuned code, so just use the set of enabled | |
| 141 alternatives. */ | |
| 0 | 142 ok = (cached_reg_save_code[reg][mode] != -1 |
| 143 && cached_reg_restore_code[reg][mode] != -1); | |
| 144 if (ok) | |
| 145 { | |
| 146 extract_insn (saveinsn); | |
| 111 | 147 ok = constrain_operands (1, get_enabled_alternatives (saveinsn)); |
| 0 | 148 extract_insn (restinsn); |
| 111 | 149 ok &= constrain_operands (1, get_enabled_alternatives (restinsn)); |
| 0 | 150 } |
| 151 | |
| 152 if (! ok) | |
| 153 { | |
| 154 cached_reg_save_code[reg][mode] = -1; | |
| 155 cached_reg_restore_code[reg][mode] = -1; | |
| 156 } | |
| 157 gcc_assert (cached_reg_save_code[reg][mode]); | |
| 158 return cached_reg_save_code[reg][mode]; | |
| 159 } | |
| 160 | |
| 161 /* Return the INSN_CODE used to restore register REG in mode MODE. */ | |
| 162 static int | |
| 111 | 163 reg_restore_code (int reg, machine_mode mode) |
| 0 | 164 { |
| 165 if (cached_reg_restore_code[reg][mode]) | |
| 166 return cached_reg_restore_code[reg][mode]; | |
| 167 /* Populate our cache. */ | |
| 168 reg_save_code (reg, mode); | |
| 169 return cached_reg_restore_code[reg][mode]; | |
| 170 } | |
| 171 | |
| 172 /* Initialize for caller-save. | |
| 173 | |
| 174 Look at all the hard registers that are used by a call and for which | |
| 175 reginfo.c has not already excluded from being used across a call. | |
| 176 | |
| 177 Ensure that we can find a mode to save the register and that there is a | |
| 178 simple insn to save and restore the register. This latter check avoids | |
| 179 problems that would occur if we tried to save the MQ register of some | |
| 180 machines directly into memory. */ | |
| 181 | |
| 182 void | |
| 183 init_caller_save (void) | |
| 184 { | |
| 185 rtx addr_reg; | |
| 186 int offset; | |
| 187 rtx address; | |
| 188 int i, j; | |
| 189 | |
|
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190 if (caller_save_initialized_p) |
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191 return; |
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192 |
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193 caller_save_initialized_p = true; |
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194 |
| 0 | 195 CLEAR_HARD_REG_SET (no_caller_save_reg_set); |
| 196 /* First find all the registers that we need to deal with and all | |
| 197 the modes that they can have. If we can't find a mode to use, | |
| 198 we can't have the register live over calls. */ | |
| 199 | |
| 200 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
| 201 { | |
|
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202 if (call_used_regs[i] |
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203 && !TEST_HARD_REG_BIT (call_fixed_reg_set, i)) |
| 0 | 204 { |
| 205 for (j = 1; j <= MOVE_MAX_WORDS; j++) | |
| 206 { | |
| 207 regno_save_mode[i][j] = HARD_REGNO_CALLER_SAVE_MODE (i, j, | |
| 208 VOIDmode); | |
| 209 if (regno_save_mode[i][j] == VOIDmode && j == 1) | |
| 210 { | |
| 211 SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
| 212 } | |
| 213 } | |
| 214 } | |
| 215 else | |
| 216 regno_save_mode[i][1] = VOIDmode; | |
| 217 } | |
| 218 | |
| 219 /* The following code tries to approximate the conditions under which | |
| 220 we can easily save and restore a register without scratch registers or | |
| 221 other complexities. It will usually work, except under conditions where | |
| 222 the validity of an insn operand is dependent on the address offset. | |
| 223 No such cases are currently known. | |
| 224 | |
| 225 We first find a typical offset from some BASE_REG_CLASS register. | |
| 226 This address is chosen by finding the first register in the class | |
| 227 and by finding the smallest power of two that is a valid offset from | |
| 228 that register in every mode we will use to save registers. */ | |
| 229 | |
| 230 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
| 231 if (TEST_HARD_REG_BIT | |
| 232 (reg_class_contents | |
| 111 | 233 [(int) base_reg_class (regno_save_mode[i][1], ADDR_SPACE_GENERIC, |
| 234 PLUS, CONST_INT)], i)) | |
| 0 | 235 break; |
| 236 | |
| 237 gcc_assert (i < FIRST_PSEUDO_REGISTER); | |
| 238 | |
| 239 addr_reg = gen_rtx_REG (Pmode, i); | |
| 240 | |
| 241 for (offset = 1 << (HOST_BITS_PER_INT / 2); offset; offset >>= 1) | |
| 242 { | |
| 111 | 243 address = gen_rtx_PLUS (Pmode, addr_reg, gen_int_mode (offset, Pmode)); |
| 0 | 244 |
| 245 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
| 246 if (regno_save_mode[i][1] != VOIDmode | |
| 247 && ! strict_memory_address_p (regno_save_mode[i][1], address)) | |
| 248 break; | |
| 249 | |
| 250 if (i == FIRST_PSEUDO_REGISTER) | |
| 251 break; | |
| 252 } | |
| 253 | |
| 254 /* If we didn't find a valid address, we must use register indirect. */ | |
| 255 if (offset == 0) | |
| 256 address = addr_reg; | |
| 257 | |
| 258 /* Next we try to form an insn to save and restore the register. We | |
| 259 see if such an insn is recognized and meets its constraints. | |
| 260 | |
| 261 To avoid lots of unnecessary RTL allocation, we construct all the RTL | |
| 262 once, then modify the memory and register operands in-place. */ | |
| 263 | |
| 111 | 264 test_reg = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1); |
| 265 test_mem = gen_rtx_MEM (word_mode, address); | |
| 266 savepat = gen_rtx_SET (test_mem, test_reg); | |
| 267 restpat = gen_rtx_SET (test_reg, test_mem); | |
| 0 | 268 |
| 111 | 269 saveinsn = gen_rtx_INSN (VOIDmode, 0, 0, 0, savepat, 0, -1, 0); |
| 270 restinsn = gen_rtx_INSN (VOIDmode, 0, 0, 0, restpat, 0, -1, 0); | |
| 0 | 271 |
| 272 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
| 273 for (j = 1; j <= MOVE_MAX_WORDS; j++) | |
| 274 if (reg_save_code (i,regno_save_mode[i][j]) == -1) | |
| 275 { | |
| 276 regno_save_mode[i][j] = VOIDmode; | |
| 277 if (j == 1) | |
| 278 { | |
| 279 SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
| 280 if (call_used_regs[i]) | |
| 281 SET_HARD_REG_BIT (no_caller_save_reg_set, i); | |
| 282 } | |
| 283 } | |
| 284 } | |
| 285 | |
| 286 | |
| 287 | |
| 288 /* Initialize save areas by showing that we haven't allocated any yet. */ | |
| 289 | |
| 290 void | |
| 291 init_save_areas (void) | |
| 292 { | |
| 293 int i, j; | |
| 294 | |
| 295 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
| 296 for (j = 1; j <= MOVE_MAX_WORDS; j++) | |
| 297 regno_save_mem[i][j] = 0; | |
| 298 save_slots_num = 0; | |
|
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299 |
| 0 | 300 } |
| 301 | |
| 302 /* The structure represents a hard register which should be saved | |
| 303 through the call. It is used when the integrated register | |
| 304 allocator (IRA) is used and sharing save slots is on. */ | |
| 305 struct saved_hard_reg | |
| 306 { | |
| 307 /* Order number starting with 0. */ | |
| 308 int num; | |
| 309 /* The hard regno. */ | |
| 310 int hard_regno; | |
| 311 /* Execution frequency of all calls through which given hard | |
| 312 register should be saved. */ | |
| 313 int call_freq; | |
| 314 /* Stack slot reserved to save the hard register through calls. */ | |
| 315 rtx slot; | |
| 316 /* True if it is first hard register in the chain of hard registers | |
| 317 sharing the same stack slot. */ | |
| 318 int first_p; | |
| 319 /* Order number of the next hard register structure with the same | |
| 320 slot in the chain. -1 represents end of the chain. */ | |
| 321 int next; | |
| 322 }; | |
| 323 | |
| 324 /* Map: hard register number to the corresponding structure. */ | |
| 325 static struct saved_hard_reg *hard_reg_map[FIRST_PSEUDO_REGISTER]; | |
| 326 | |
| 327 /* The number of all structures representing hard registers should be | |
| 328 saved, in order words, the number of used elements in the following | |
| 329 array. */ | |
| 330 static int saved_regs_num; | |
| 331 | |
| 332 /* Pointers to all the structures. Index is the order number of the | |
| 333 corresponding structure. */ | |
| 334 static struct saved_hard_reg *all_saved_regs[FIRST_PSEUDO_REGISTER]; | |
| 335 | |
| 336 /* First called function for work with saved hard registers. */ | |
| 337 static void | |
| 338 initiate_saved_hard_regs (void) | |
| 339 { | |
| 340 int i; | |
| 341 | |
| 342 saved_regs_num = 0; | |
| 343 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
| 344 hard_reg_map[i] = NULL; | |
| 345 } | |
| 346 | |
| 347 /* Allocate and return new saved hard register with given REGNO and | |
| 348 CALL_FREQ. */ | |
| 111 | 349 static void |
| 0 | 350 new_saved_hard_reg (int regno, int call_freq) |
| 351 { | |
| 352 struct saved_hard_reg *saved_reg; | |
| 353 | |
| 354 saved_reg | |
| 355 = (struct saved_hard_reg *) xmalloc (sizeof (struct saved_hard_reg)); | |
| 356 hard_reg_map[regno] = all_saved_regs[saved_regs_num] = saved_reg; | |
| 357 saved_reg->num = saved_regs_num++; | |
| 358 saved_reg->hard_regno = regno; | |
| 359 saved_reg->call_freq = call_freq; | |
| 360 saved_reg->first_p = FALSE; | |
| 361 saved_reg->next = -1; | |
| 362 } | |
| 363 | |
| 364 /* Free memory allocated for the saved hard registers. */ | |
| 365 static void | |
| 366 finish_saved_hard_regs (void) | |
| 367 { | |
| 368 int i; | |
| 369 | |
| 370 for (i = 0; i < saved_regs_num; i++) | |
| 371 free (all_saved_regs[i]); | |
| 372 } | |
| 373 | |
| 374 /* The function is used to sort the saved hard register structures | |
| 375 according their frequency. */ | |
| 376 static int | |
| 377 saved_hard_reg_compare_func (const void *v1p, const void *v2p) | |
| 378 { | |
| 379 const struct saved_hard_reg *p1 = *(struct saved_hard_reg * const *) v1p; | |
| 380 const struct saved_hard_reg *p2 = *(struct saved_hard_reg * const *) v2p; | |
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381 |
| 0 | 382 if (flag_omit_frame_pointer) |
| 383 { | |
| 384 if (p1->call_freq - p2->call_freq != 0) | |
| 385 return p1->call_freq - p2->call_freq; | |
| 386 } | |
| 387 else if (p2->call_freq - p1->call_freq != 0) | |
| 388 return p2->call_freq - p1->call_freq; | |
| 389 | |
| 390 return p1->num - p2->num; | |
| 391 } | |
| 392 | |
| 393 /* Allocate save areas for any hard registers that might need saving. | |
| 394 We take a conservative approach here and look for call-clobbered hard | |
| 395 registers that are assigned to pseudos that cross calls. This may | |
| 396 overestimate slightly (especially if some of these registers are later | |
| 397 used as spill registers), but it should not be significant. | |
| 398 | |
| 399 For IRA we use priority coloring to decrease stack slots needed for | |
| 400 saving hard registers through calls. We build conflicts for them | |
| 401 to do coloring. | |
| 402 | |
| 403 Future work: | |
| 404 | |
| 405 In the fallback case we should iterate backwards across all possible | |
| 406 modes for the save, choosing the largest available one instead of | |
| 407 falling back to the smallest mode immediately. (eg TF -> DF -> SF). | |
| 408 | |
| 409 We do not try to use "move multiple" instructions that exist | |
| 410 on some machines (such as the 68k moveml). It could be a win to try | |
| 411 and use them when possible. The hard part is doing it in a way that is | |
| 412 machine independent since they might be saving non-consecutive | |
| 413 registers. (imagine caller-saving d0,d1,a0,a1 on the 68k) */ | |
| 414 | |
| 415 void | |
| 416 setup_save_areas (void) | |
| 417 { | |
|
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418 int i, j, k, freq; |
| 0 | 419 HARD_REG_SET hard_regs_used; |
|
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420 struct saved_hard_reg *saved_reg; |
| 111 | 421 rtx_insn *insn; |
|
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422 struct insn_chain *chain, *next; |
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423 unsigned int regno; |
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424 HARD_REG_SET hard_regs_to_save, used_regs, this_insn_sets; |
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425 reg_set_iterator rsi; |
| 0 | 426 |
| 427 CLEAR_HARD_REG_SET (hard_regs_used); | |
|
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428 |
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429 /* Find every CALL_INSN and record which hard regs are live across the |
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430 call into HARD_REG_MAP and HARD_REGS_USED. */ |
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431 initiate_saved_hard_regs (); |
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432 /* Create hard reg saved regs. */ |
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433 for (chain = reload_insn_chain; chain != 0; chain = next) |
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434 { |
| 111 | 435 rtx cheap; |
| 436 | |
|
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437 insn = chain->insn; |
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438 next = chain->next; |
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439 if (!CALL_P (insn) |
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440 || find_reg_note (insn, REG_NORETURN, NULL)) |
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441 continue; |
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442 freq = REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn)); |
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443 REG_SET_TO_HARD_REG_SET (hard_regs_to_save, |
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444 &chain->live_throughout); |
| 111 | 445 get_call_reg_set_usage (insn, &used_regs, call_used_reg_set); |
|
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446 |
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447 /* Record all registers set in this call insn. These don't |
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448 need to be saved. N.B. the call insn might set a subreg |
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449 of a multi-hard-reg pseudo; then the pseudo is considered |
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450 live during the call, but the subreg that is set |
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451 isn't. */ |
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452 CLEAR_HARD_REG_SET (this_insn_sets); |
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453 note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); |
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454 /* Sibcalls are considered to set the return value. */ |
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455 if (SIBLING_CALL_P (insn) && crtl->return_rtx) |
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456 mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets); |
| 0 | 457 |
|
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458 AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set); |
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459 AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets); |
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460 AND_HARD_REG_SET (hard_regs_to_save, used_regs); |
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461 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) |
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462 if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) |
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463 { |
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464 if (hard_reg_map[regno] != NULL) |
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465 hard_reg_map[regno]->call_freq += freq; |
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466 else |
| 111 | 467 new_saved_hard_reg (regno, freq); |
|
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468 SET_HARD_REG_BIT (hard_regs_used, regno); |
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469 } |
| 111 | 470 cheap = find_reg_note (insn, REG_RETURNED, NULL); |
| 471 if (cheap) | |
| 472 cheap = XEXP (cheap, 0); | |
|
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473 /* Look through all live pseudos, mark their hard registers. */ |
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474 EXECUTE_IF_SET_IN_REG_SET |
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475 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) |
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476 { |
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477 int r = reg_renumber[regno]; |
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478 int bound; |
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479 |
| 111 | 480 if (r < 0 || regno_reg_rtx[regno] == cheap) |
|
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481 continue; |
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482 |
| 111 | 483 bound = r + hard_regno_nregs (r, PSEUDO_REGNO_MODE (regno)); |
|
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484 for (; r < bound; r++) |
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485 if (TEST_HARD_REG_BIT (used_regs, r)) |
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486 { |
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487 if (hard_reg_map[r] != NULL) |
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488 hard_reg_map[r]->call_freq += freq; |
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489 else |
| 111 | 490 new_saved_hard_reg (r, freq); |
|
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491 SET_HARD_REG_BIT (hard_regs_to_save, r); |
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492 SET_HARD_REG_BIT (hard_regs_used, r); |
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493 } |
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494 } |
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495 } |
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496 |
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497 /* If requested, figure out which hard regs can share save slots. */ |
| 0 | 498 if (optimize && flag_ira_share_save_slots) |
| 499 { | |
|
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500 rtx slot; |
| 0 | 501 char *saved_reg_conflicts; |
|
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502 int next_k; |
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503 struct saved_hard_reg *saved_reg2, *saved_reg3; |
| 0 | 504 int call_saved_regs_num; |
| 505 struct saved_hard_reg *call_saved_regs[FIRST_PSEUDO_REGISTER]; | |
| 506 int best_slot_num; | |
| 507 int prev_save_slots_num; | |
| 508 rtx prev_save_slots[FIRST_PSEUDO_REGISTER]; | |
|
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509 |
| 0 | 510 /* Find saved hard register conflicts. */ |
| 511 saved_reg_conflicts = (char *) xmalloc (saved_regs_num * saved_regs_num); | |
| 512 memset (saved_reg_conflicts, 0, saved_regs_num * saved_regs_num); | |
| 513 for (chain = reload_insn_chain; chain != 0; chain = next) | |
| 514 { | |
| 111 | 515 rtx cheap; |
| 0 | 516 call_saved_regs_num = 0; |
| 517 insn = chain->insn; | |
| 518 next = chain->next; | |
|
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519 if (!CALL_P (insn) |
| 0 | 520 || find_reg_note (insn, REG_NORETURN, NULL)) |
| 521 continue; | |
| 111 | 522 |
| 523 cheap = find_reg_note (insn, REG_RETURNED, NULL); | |
| 524 if (cheap) | |
| 525 cheap = XEXP (cheap, 0); | |
| 526 | |
| 0 | 527 REG_SET_TO_HARD_REG_SET (hard_regs_to_save, |
| 528 &chain->live_throughout); | |
| 111 | 529 get_call_reg_set_usage (insn, &used_regs, call_used_reg_set); |
| 0 | 530 |
| 531 /* Record all registers set in this call insn. These don't | |
| 532 need to be saved. N.B. the call insn might set a subreg | |
| 533 of a multi-hard-reg pseudo; then the pseudo is considered | |
| 534 live during the call, but the subreg that is set | |
| 535 isn't. */ | |
| 536 CLEAR_HARD_REG_SET (this_insn_sets); | |
| 537 note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); | |
| 538 /* Sibcalls are considered to set the return value, | |
|
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539 compare df-scan.c:df_get_call_refs. */ |
| 0 | 540 if (SIBLING_CALL_P (insn) && crtl->return_rtx) |
| 541 mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets); | |
| 542 | |
| 543 AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set); | |
| 544 AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets); | |
| 545 AND_HARD_REG_SET (hard_regs_to_save, used_regs); | |
| 546 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
| 547 if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) | |
| 548 { | |
| 549 gcc_assert (hard_reg_map[regno] != NULL); | |
| 550 call_saved_regs[call_saved_regs_num++] = hard_reg_map[regno]; | |
| 551 } | |
| 552 /* Look through all live pseudos, mark their hard registers. */ | |
| 553 EXECUTE_IF_SET_IN_REG_SET | |
| 554 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) | |
| 555 { | |
| 556 int r = reg_renumber[regno]; | |
| 557 int bound; | |
|
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558 |
| 111 | 559 if (r < 0 || regno_reg_rtx[regno] == cheap) |
| 0 | 560 continue; |
| 561 | |
| 111 | 562 bound = r + hard_regno_nregs (r, PSEUDO_REGNO_MODE (regno)); |
| 0 | 563 for (; r < bound; r++) |
| 564 if (TEST_HARD_REG_BIT (used_regs, r)) | |
| 565 call_saved_regs[call_saved_regs_num++] = hard_reg_map[r]; | |
| 566 } | |
| 567 for (i = 0; i < call_saved_regs_num; i++) | |
| 568 { | |
| 569 saved_reg = call_saved_regs[i]; | |
| 570 for (j = 0; j < call_saved_regs_num; j++) | |
| 571 if (i != j) | |
| 572 { | |
| 573 saved_reg2 = call_saved_regs[j]; | |
| 574 saved_reg_conflicts[saved_reg->num * saved_regs_num | |
| 575 + saved_reg2->num] | |
| 576 = saved_reg_conflicts[saved_reg2->num * saved_regs_num | |
| 577 + saved_reg->num] | |
| 578 = TRUE; | |
| 579 } | |
| 580 } | |
| 581 } | |
| 582 /* Sort saved hard regs. */ | |
| 583 qsort (all_saved_regs, saved_regs_num, sizeof (struct saved_hard_reg *), | |
| 584 saved_hard_reg_compare_func); | |
| 585 /* Initiate slots available from the previous reload | |
| 586 iteration. */ | |
| 587 prev_save_slots_num = save_slots_num; | |
| 588 memcpy (prev_save_slots, save_slots, save_slots_num * sizeof (rtx)); | |
| 589 save_slots_num = 0; | |
| 590 /* Allocate stack slots for the saved hard registers. */ | |
| 591 for (i = 0; i < saved_regs_num; i++) | |
| 592 { | |
| 593 saved_reg = all_saved_regs[i]; | |
| 594 regno = saved_reg->hard_regno; | |
| 595 for (j = 0; j < i; j++) | |
| 596 { | |
| 597 saved_reg2 = all_saved_regs[j]; | |
| 598 if (! saved_reg2->first_p) | |
| 599 continue; | |
| 600 slot = saved_reg2->slot; | |
| 601 for (k = j; k >= 0; k = next_k) | |
| 602 { | |
| 603 saved_reg3 = all_saved_regs[k]; | |
| 604 next_k = saved_reg3->next; | |
| 605 if (saved_reg_conflicts[saved_reg->num * saved_regs_num | |
| 606 + saved_reg3->num]) | |
| 607 break; | |
| 608 } | |
| 609 if (k < 0 | |
| 610 && (GET_MODE_SIZE (regno_save_mode[regno][1]) | |
| 611 <= GET_MODE_SIZE (regno_save_mode | |
| 612 [saved_reg2->hard_regno][1]))) | |
| 613 { | |
| 614 saved_reg->slot | |
| 615 = adjust_address_nv | |
| 616 (slot, regno_save_mode[saved_reg->hard_regno][1], 0); | |
| 617 regno_save_mem[regno][1] = saved_reg->slot; | |
| 618 saved_reg->next = saved_reg2->next; | |
| 619 saved_reg2->next = i; | |
| 620 if (dump_file != NULL) | |
| 621 fprintf (dump_file, "%d uses slot of %d\n", | |
| 622 regno, saved_reg2->hard_regno); | |
| 623 break; | |
| 624 } | |
| 625 } | |
| 626 if (j == i) | |
| 627 { | |
| 628 saved_reg->first_p = TRUE; | |
| 629 for (best_slot_num = -1, j = 0; j < prev_save_slots_num; j++) | |
| 630 { | |
| 631 slot = prev_save_slots[j]; | |
| 632 if (slot == NULL_RTX) | |
| 633 continue; | |
| 634 if (GET_MODE_SIZE (regno_save_mode[regno][1]) | |
| 635 <= GET_MODE_SIZE (GET_MODE (slot)) | |
| 636 && best_slot_num < 0) | |
| 637 best_slot_num = j; | |
| 638 if (GET_MODE (slot) == regno_save_mode[regno][1]) | |
| 639 break; | |
| 640 } | |
| 641 if (best_slot_num >= 0) | |
| 642 { | |
| 643 saved_reg->slot = prev_save_slots[best_slot_num]; | |
| 644 saved_reg->slot | |
| 645 = adjust_address_nv | |
| 646 (saved_reg->slot, | |
| 647 regno_save_mode[saved_reg->hard_regno][1], 0); | |
| 648 if (dump_file != NULL) | |
| 649 fprintf (dump_file, | |
| 650 "%d uses a slot from prev iteration\n", regno); | |
| 651 prev_save_slots[best_slot_num] = NULL_RTX; | |
| 652 if (best_slot_num + 1 == prev_save_slots_num) | |
| 653 prev_save_slots_num--; | |
| 654 } | |
| 655 else | |
| 656 { | |
| 657 saved_reg->slot | |
| 658 = assign_stack_local_1 | |
| 659 (regno_save_mode[regno][1], | |
|
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660 GET_MODE_SIZE (regno_save_mode[regno][1]), 0, |
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661 ASLK_REDUCE_ALIGN); |
| 0 | 662 if (dump_file != NULL) |
| 663 fprintf (dump_file, "%d uses a new slot\n", regno); | |
| 664 } | |
| 665 regno_save_mem[regno][1] = saved_reg->slot; | |
| 666 save_slots[save_slots_num++] = saved_reg->slot; | |
| 667 } | |
| 668 } | |
| 669 free (saved_reg_conflicts); | |
| 670 finish_saved_hard_regs (); | |
| 671 } | |
| 672 else | |
| 673 { | |
|
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674 /* We are not sharing slots. |
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675 |
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676 Run through all the call-used hard-registers and allocate |
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677 space for each in the caller-save area. Try to allocate space |
| 0 | 678 in a manner which allows multi-register saves/restores to be done. */ |
|
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679 |
| 0 | 680 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
| 681 for (j = MOVE_MAX_WORDS; j > 0; j--) | |
| 682 { | |
| 683 int do_save = 1; | |
|
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684 |
| 0 | 685 /* If no mode exists for this size, try another. Also break out |
| 686 if we have already saved this hard register. */ | |
| 687 if (regno_save_mode[i][j] == VOIDmode || regno_save_mem[i][1] != 0) | |
| 688 continue; | |
|
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689 |
| 0 | 690 /* See if any register in this group has been saved. */ |
| 691 for (k = 0; k < j; k++) | |
| 692 if (regno_save_mem[i + k][1]) | |
| 693 { | |
| 694 do_save = 0; | |
| 695 break; | |
| 696 } | |
| 697 if (! do_save) | |
| 698 continue; | |
|
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699 |
| 0 | 700 for (k = 0; k < j; k++) |
| 701 if (! TEST_HARD_REG_BIT (hard_regs_used, i + k)) | |
| 702 { | |
| 703 do_save = 0; | |
| 704 break; | |
| 705 } | |
| 706 if (! do_save) | |
| 707 continue; | |
|
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708 |
| 0 | 709 /* We have found an acceptable mode to store in. Since |
| 710 hard register is always saved in the widest mode | |
| 711 available, the mode may be wider than necessary, it is | |
| 712 OK to reduce the alignment of spill space. We will | |
| 713 verify that it is equal to or greater than required | |
| 714 when we restore and save the hard register in | |
| 715 insert_restore and insert_save. */ | |
| 716 regno_save_mem[i][j] | |
| 717 = assign_stack_local_1 (regno_save_mode[i][j], | |
| 718 GET_MODE_SIZE (regno_save_mode[i][j]), | |
|
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719 0, ASLK_REDUCE_ALIGN); |
|
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720 |
| 0 | 721 /* Setup single word save area just in case... */ |
| 722 for (k = 0; k < j; k++) | |
| 723 /* This should not depend on WORDS_BIG_ENDIAN. | |
| 724 The order of words in regs is the same as in memory. */ | |
| 725 regno_save_mem[i + k][1] | |
| 726 = adjust_address_nv (regno_save_mem[i][j], | |
| 727 regno_save_mode[i + k][1], | |
| 728 k * UNITS_PER_WORD); | |
| 729 } | |
| 730 } | |
| 731 | |
| 732 /* Now loop again and set the alias set of any save areas we made to | |
| 733 the alias set used to represent frame objects. */ | |
| 734 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
| 735 for (j = MOVE_MAX_WORDS; j > 0; j--) | |
| 736 if (regno_save_mem[i][j] != 0) | |
| 737 set_mem_alias_set (regno_save_mem[i][j], get_frame_alias_set ()); | |
| 738 } | |
| 739 | |
| 740 | |
| 741 | |
| 742 /* Find the places where hard regs are live across calls and save them. */ | |
| 743 | |
| 744 void | |
| 745 save_call_clobbered_regs (void) | |
| 746 { | |
|
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747 struct insn_chain *chain, *next, *last = NULL; |
| 111 | 748 machine_mode save_mode [FIRST_PSEUDO_REGISTER]; |
| 0 | 749 |
| 750 /* Computed in mark_set_regs, holds all registers set by the current | |
| 751 instruction. */ | |
| 752 HARD_REG_SET this_insn_sets; | |
| 753 | |
| 754 CLEAR_HARD_REG_SET (hard_regs_saved); | |
| 755 n_regs_saved = 0; | |
| 756 | |
| 757 for (chain = reload_insn_chain; chain != 0; chain = next) | |
| 758 { | |
| 111 | 759 rtx_insn *insn = chain->insn; |
| 0 | 760 enum rtx_code code = GET_CODE (insn); |
| 761 | |
| 762 next = chain->next; | |
| 763 | |
| 764 gcc_assert (!chain->is_caller_save_insn); | |
| 765 | |
|
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766 if (NONDEBUG_INSN_P (insn)) |
| 0 | 767 { |
| 768 /* If some registers have been saved, see if INSN references | |
| 769 any of them. We must restore them before the insn if so. */ | |
| 770 | |
| 771 if (n_regs_saved) | |
| 772 { | |
| 773 int regno; | |
|
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774 HARD_REG_SET this_insn_sets; |
| 0 | 775 |
| 776 if (code == JUMP_INSN) | |
| 777 /* Restore all registers if this is a JUMP_INSN. */ | |
| 778 COPY_HARD_REG_SET (referenced_regs, hard_regs_saved); | |
| 779 else | |
| 780 { | |
| 781 CLEAR_HARD_REG_SET (referenced_regs); | |
|
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782 mark_referenced_regs (&PATTERN (insn), |
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783 mark_reg_as_referenced, NULL); |
| 0 | 784 AND_HARD_REG_SET (referenced_regs, hard_regs_saved); |
| 785 } | |
| 786 | |
| 787 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
| 788 if (TEST_HARD_REG_BIT (referenced_regs, regno)) | |
|
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789 regno += insert_restore (chain, 1, regno, MOVE_MAX_WORDS, |
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790 save_mode); |
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791 /* If a saved register is set after the call, this means we no |
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792 longer should restore it. This can happen when parts of a |
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793 multi-word pseudo do not conflict with other pseudos, so |
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794 IRA may allocate the same hard register for both. One may |
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795 be live across the call, while the other is set |
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796 afterwards. */ |
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797 CLEAR_HARD_REG_SET (this_insn_sets); |
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798 note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); |
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799 AND_COMPL_HARD_REG_SET (hard_regs_saved, this_insn_sets); |
| 0 | 800 } |
| 801 | |
| 802 if (code == CALL_INSN | |
| 803 && ! SIBLING_CALL_P (insn) | |
| 804 && ! find_reg_note (insn, REG_NORETURN, NULL)) | |
| 805 { | |
| 806 unsigned regno; | |
| 807 HARD_REG_SET hard_regs_to_save; | |
| 111 | 808 HARD_REG_SET call_def_reg_set; |
| 0 | 809 reg_set_iterator rsi; |
| 111 | 810 rtx cheap; |
| 811 | |
| 812 cheap = find_reg_note (insn, REG_RETURNED, NULL); | |
| 813 if (cheap) | |
| 814 cheap = XEXP (cheap, 0); | |
| 0 | 815 |
| 816 /* Use the register life information in CHAIN to compute which | |
| 817 regs are live during the call. */ | |
| 818 REG_SET_TO_HARD_REG_SET (hard_regs_to_save, | |
| 819 &chain->live_throughout); | |
| 820 /* Save hard registers always in the widest mode available. */ | |
| 821 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
| 822 if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) | |
| 823 save_mode [regno] = regno_save_mode [regno][1]; | |
| 824 else | |
| 825 save_mode [regno] = VOIDmode; | |
| 826 | |
| 827 /* Look through all live pseudos, mark their hard registers | |
| 828 and choose proper mode for saving. */ | |
| 829 EXECUTE_IF_SET_IN_REG_SET | |
| 830 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) | |
| 831 { | |
| 832 int r = reg_renumber[regno]; | |
| 833 int nregs; | |
| 111 | 834 machine_mode mode; |
| 0 | 835 |
| 111 | 836 if (r < 0 || regno_reg_rtx[regno] == cheap) |
| 0 | 837 continue; |
| 111 | 838 nregs = hard_regno_nregs (r, PSEUDO_REGNO_MODE (regno)); |
| 0 | 839 mode = HARD_REGNO_CALLER_SAVE_MODE |
| 840 (r, nregs, PSEUDO_REGNO_MODE (regno)); | |
| 111 | 841 if (partial_subreg_p (save_mode[r], mode)) |
| 0 | 842 save_mode[r] = mode; |
| 843 while (nregs-- > 0) | |
| 844 SET_HARD_REG_BIT (hard_regs_to_save, r + nregs); | |
| 845 } | |
| 846 | |
| 847 /* Record all registers set in this call insn. These don't need | |
| 848 to be saved. N.B. the call insn might set a subreg of a | |
| 849 multi-hard-reg pseudo; then the pseudo is considered live | |
| 850 during the call, but the subreg that is set isn't. */ | |
| 851 CLEAR_HARD_REG_SET (this_insn_sets); | |
| 852 note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); | |
| 853 | |
| 854 /* Compute which hard regs must be saved before this call. */ | |
| 855 AND_COMPL_HARD_REG_SET (hard_regs_to_save, call_fixed_reg_set); | |
| 856 AND_COMPL_HARD_REG_SET (hard_regs_to_save, this_insn_sets); | |
| 857 AND_COMPL_HARD_REG_SET (hard_regs_to_save, hard_regs_saved); | |
| 111 | 858 get_call_reg_set_usage (insn, &call_def_reg_set, |
| 859 call_used_reg_set); | |
| 860 AND_HARD_REG_SET (hard_regs_to_save, call_def_reg_set); | |
| 0 | 861 |
| 862 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
| 863 if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) | |
| 864 regno += insert_save (chain, 1, regno, &hard_regs_to_save, save_mode); | |
| 865 | |
| 866 /* Must recompute n_regs_saved. */ | |
| 867 n_regs_saved = 0; | |
| 868 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
| 869 if (TEST_HARD_REG_BIT (hard_regs_saved, regno)) | |
| 870 n_regs_saved++; | |
| 111 | 871 |
| 872 if (cheap | |
| 873 && HARD_REGISTER_P (cheap) | |
| 874 && TEST_HARD_REG_BIT (call_used_reg_set, REGNO (cheap))) | |
| 875 { | |
| 876 rtx dest, newpat; | |
| 877 rtx pat = PATTERN (insn); | |
| 878 if (GET_CODE (pat) == PARALLEL) | |
| 879 pat = XVECEXP (pat, 0, 0); | |
| 880 dest = SET_DEST (pat); | |
| 881 /* For multiple return values dest is PARALLEL. | |
| 882 Currently we handle only single return value case. */ | |
| 883 if (REG_P (dest)) | |
| 884 { | |
| 885 newpat = gen_rtx_SET (cheap, copy_rtx (dest)); | |
| 886 chain = insert_one_insn (chain, 0, -1, newpat); | |
| 887 } | |
| 888 } | |
| 0 | 889 } |
|
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890 last = chain; |
| 0 | 891 } |
|
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892 else if (DEBUG_INSN_P (insn) && n_regs_saved) |
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893 mark_referenced_regs (&PATTERN (insn), |
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894 replace_reg_with_saved_mem, |
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895 save_mode); |
| 0 | 896 |
| 897 if (chain->next == 0 || chain->next->block != chain->block) | |
| 898 { | |
| 899 int regno; | |
| 900 /* At the end of the basic block, we must restore any registers that | |
| 901 remain saved. If the last insn in the block is a JUMP_INSN, put | |
| 902 the restore before the insn, otherwise, put it after the insn. */ | |
| 903 | |
|
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904 if (n_regs_saved |
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905 && DEBUG_INSN_P (insn) |
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906 && last |
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907 && last->block == chain->block) |
|
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908 { |
| 111 | 909 rtx_insn *ins, *prev; |
|
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910 basic_block bb = BLOCK_FOR_INSN (insn); |
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911 |
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912 /* When adding hard reg restores after a DEBUG_INSN, move |
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913 all notes between last real insn and this DEBUG_INSN after |
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914 the DEBUG_INSN, otherwise we could get code |
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915 -g/-g0 differences. */ |
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916 for (ins = PREV_INSN (insn); ins != last->insn; ins = prev) |
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917 { |
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918 prev = PREV_INSN (ins); |
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919 if (NOTE_P (ins)) |
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920 { |
| 111 | 921 SET_NEXT_INSN (prev) = NEXT_INSN (ins); |
| 922 SET_PREV_INSN (NEXT_INSN (ins)) = prev; | |
| 923 SET_PREV_INSN (ins) = insn; | |
| 924 SET_NEXT_INSN (ins) = NEXT_INSN (insn); | |
| 925 SET_NEXT_INSN (insn) = ins; | |
|
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926 if (NEXT_INSN (ins)) |
| 111 | 927 SET_PREV_INSN (NEXT_INSN (ins)) = ins; |
|
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928 if (BB_END (bb) == insn) |
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929 BB_END (bb) = ins; |
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930 } |
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931 else |
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932 gcc_assert (DEBUG_INSN_P (ins)); |
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933 } |
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934 } |
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935 last = NULL; |
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936 |
| 0 | 937 if (n_regs_saved) |
| 938 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
| 939 if (TEST_HARD_REG_BIT (hard_regs_saved, regno)) | |
| 940 regno += insert_restore (chain, JUMP_P (insn), | |
| 941 regno, MOVE_MAX_WORDS, save_mode); | |
| 942 } | |
| 943 } | |
| 944 } | |
| 945 | |
| 946 /* Here from note_stores, or directly from save_call_clobbered_regs, when | |
| 947 an insn stores a value in a register. | |
| 948 Set the proper bit or bits in this_insn_sets. All pseudos that have | |
| 949 been assigned hard regs have had their register number changed already, | |
| 950 so we can ignore pseudos. */ | |
| 951 static void | |
| 952 mark_set_regs (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *data) | |
| 953 { | |
| 954 int regno, endregno, i; | |
| 955 HARD_REG_SET *this_insn_sets = (HARD_REG_SET *) data; | |
| 956 | |
| 957 if (GET_CODE (reg) == SUBREG) | |
| 958 { | |
| 959 rtx inner = SUBREG_REG (reg); | |
| 960 if (!REG_P (inner) || REGNO (inner) >= FIRST_PSEUDO_REGISTER) | |
| 961 return; | |
| 962 regno = subreg_regno (reg); | |
| 963 endregno = regno + subreg_nregs (reg); | |
| 964 } | |
| 965 else if (REG_P (reg) | |
| 966 && REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
| 967 { | |
| 968 regno = REGNO (reg); | |
| 111 | 969 endregno = END_REGNO (reg); |
| 0 | 970 } |
| 971 else | |
| 972 return; | |
| 973 | |
| 974 for (i = regno; i < endregno; i++) | |
| 975 SET_HARD_REG_BIT (*this_insn_sets, i); | |
| 976 } | |
| 977 | |
| 978 /* Here from note_stores when an insn stores a value in a register. | |
| 979 Set the proper bit or bits in the passed regset. All pseudos that have | |
| 980 been assigned hard regs have had their register number changed already, | |
| 981 so we can ignore pseudos. */ | |
| 982 static void | |
| 983 add_stored_regs (rtx reg, const_rtx setter, void *data) | |
| 984 { | |
| 985 int regno, endregno, i; | |
| 111 | 986 machine_mode mode = GET_MODE (reg); |
| 0 | 987 int offset = 0; |
| 988 | |
| 989 if (GET_CODE (setter) == CLOBBER) | |
| 990 return; | |
| 991 | |
| 992 if (GET_CODE (reg) == SUBREG | |
| 993 && REG_P (SUBREG_REG (reg)) | |
| 994 && REGNO (SUBREG_REG (reg)) < FIRST_PSEUDO_REGISTER) | |
| 995 { | |
| 996 offset = subreg_regno_offset (REGNO (SUBREG_REG (reg)), | |
| 997 GET_MODE (SUBREG_REG (reg)), | |
| 998 SUBREG_BYTE (reg), | |
| 999 GET_MODE (reg)); | |
| 1000 regno = REGNO (SUBREG_REG (reg)) + offset; | |
| 1001 endregno = regno + subreg_nregs (reg); | |
| 1002 } | |
| 1003 else | |
| 1004 { | |
| 1005 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER) | |
| 1006 return; | |
| 1007 | |
| 1008 regno = REGNO (reg) + offset; | |
| 1009 endregno = end_hard_regno (mode, regno); | |
| 1010 } | |
| 1011 | |
| 1012 for (i = regno; i < endregno; i++) | |
| 1013 SET_REGNO_REG_SET ((regset) data, i); | |
| 1014 } | |
| 1015 | |
| 1016 /* Walk X and record all referenced registers in REFERENCED_REGS. */ | |
| 1017 static void | |
|
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1018 mark_referenced_regs (rtx *loc, refmarker_fn *mark, void *arg) |
| 0 | 1019 { |
|
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1020 enum rtx_code code = GET_CODE (*loc); |
| 0 | 1021 const char *fmt; |
| 1022 int i, j; | |
| 1023 | |
| 1024 if (code == SET) | |
|
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1025 mark_referenced_regs (&SET_SRC (*loc), mark, arg); |
| 0 | 1026 if (code == SET || code == CLOBBER) |
| 1027 { | |
|
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1028 loc = &SET_DEST (*loc); |
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1029 code = GET_CODE (*loc); |
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1030 if ((code == REG && REGNO (*loc) < FIRST_PSEUDO_REGISTER) |
| 0 | 1031 || code == PC || code == CC0 |
|
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1032 || (code == SUBREG && REG_P (SUBREG_REG (*loc)) |
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1033 && REGNO (SUBREG_REG (*loc)) < FIRST_PSEUDO_REGISTER |
| 0 | 1034 /* If we're setting only part of a multi-word register, |
| 1035 we shall mark it as referenced, because the words | |
| 1036 that are not being set should be restored. */ | |
| 111 | 1037 && !read_modify_subreg_p (*loc))) |
| 0 | 1038 return; |
| 1039 } | |
| 1040 if (code == MEM || code == SUBREG) | |
| 1041 { | |
|
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1042 loc = &XEXP (*loc, 0); |
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1043 code = GET_CODE (*loc); |
| 0 | 1044 } |
| 1045 | |
| 1046 if (code == REG) | |
| 1047 { | |
|
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1048 int regno = REGNO (*loc); |
| 0 | 1049 int hardregno = (regno < FIRST_PSEUDO_REGISTER ? regno |
| 1050 : reg_renumber[regno]); | |
| 1051 | |
| 1052 if (hardregno >= 0) | |
|
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1053 mark (loc, GET_MODE (*loc), hardregno, arg); |
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1054 else if (arg) |
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1055 /* ??? Will we ever end up with an equiv expression in a debug |
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1056 insn, that would have required restoring a reg, or will |
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1057 reload take care of it for us? */ |
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1058 return; |
| 0 | 1059 /* If this is a pseudo that did not get a hard register, scan its |
| 1060 memory location, since it might involve the use of another | |
| 1061 register, which might be saved. */ | |
| 111 | 1062 else if (reg_equiv_mem (regno) != 0) |
| 1063 mark_referenced_regs (&XEXP (reg_equiv_mem (regno), 0), mark, arg); | |
| 1064 else if (reg_equiv_address (regno) != 0) | |
| 1065 mark_referenced_regs (®_equiv_address (regno), mark, arg); | |
| 0 | 1066 return; |
| 1067 } | |
| 1068 | |
| 1069 fmt = GET_RTX_FORMAT (code); | |
| 1070 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
| 1071 { | |
| 1072 if (fmt[i] == 'e') | |
|
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1073 mark_referenced_regs (&XEXP (*loc, i), mark, arg); |
| 0 | 1074 else if (fmt[i] == 'E') |
|
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1075 for (j = XVECLEN (*loc, i) - 1; j >= 0; j--) |
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1076 mark_referenced_regs (&XVECEXP (*loc, i, j), mark, arg); |
| 0 | 1077 } |
| 1078 } | |
|
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1079 |
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1080 /* Parameter function for mark_referenced_regs() that adds registers |
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1081 present in the insn and in equivalent mems and addresses to |
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1082 referenced_regs. */ |
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1083 |
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1084 static void |
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1085 mark_reg_as_referenced (rtx *loc ATTRIBUTE_UNUSED, |
| 111 | 1086 machine_mode mode, |
|
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1087 int hardregno, |
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1088 void *arg ATTRIBUTE_UNUSED) |
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1089 { |
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1090 add_to_hard_reg_set (&referenced_regs, mode, hardregno); |
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1091 } |
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1092 |
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1093 /* Parameter function for mark_referenced_regs() that replaces |
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1094 registers referenced in a debug_insn that would have been restored, |
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1095 should it be a non-debug_insn, with their save locations. */ |
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1096 |
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1097 static void |
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1098 replace_reg_with_saved_mem (rtx *loc, |
| 111 | 1099 machine_mode mode, |
|
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1100 int regno, |
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1101 void *arg) |
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1102 { |
| 111 | 1103 unsigned int i, nregs = hard_regno_nregs (regno, mode); |
|
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1104 rtx mem; |
| 111 | 1105 machine_mode *save_mode = (machine_mode *)arg; |
|
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1106 |
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1107 for (i = 0; i < nregs; i++) |
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1108 if (TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) |
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1109 break; |
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1110 |
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1111 /* If none of the registers in the range would need restoring, we're |
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1112 all set. */ |
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1113 if (i == nregs) |
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1114 return; |
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1115 |
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1116 while (++i < nregs) |
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1117 if (!TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) |
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1118 break; |
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1119 |
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1120 if (i == nregs |
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1121 && regno_save_mem[regno][nregs]) |
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1122 { |
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1123 mem = copy_rtx (regno_save_mem[regno][nregs]); |
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1124 |
| 111 | 1125 if (nregs == hard_regno_nregs (regno, save_mode[regno])) |
|
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1126 mem = adjust_address_nv (mem, save_mode[regno], 0); |
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1127 |
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1128 if (GET_MODE (mem) != mode) |
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1129 { |
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1130 /* This is gen_lowpart_if_possible(), but without validating |
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1131 the newly-formed address. */ |
| 111 | 1132 HOST_WIDE_INT offset = byte_lowpart_offset (mode, GET_MODE (mem)); |
|
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1133 mem = adjust_address_nv (mem, mode, offset); |
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1134 } |
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1135 } |
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1136 else |
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1137 { |
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1138 mem = gen_rtx_CONCATN (mode, rtvec_alloc (nregs)); |
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1139 for (i = 0; i < nregs; i++) |
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1140 if (TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) |
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1141 { |
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1142 gcc_assert (regno_save_mem[regno + i][1]); |
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1143 XVECEXP (mem, 0, i) = copy_rtx (regno_save_mem[regno + i][1]); |
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1144 } |
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1145 else |
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1146 { |
| 111 | 1147 machine_mode smode = save_mode[regno]; |
| 1148 gcc_assert (smode != VOIDmode); | |
| 1149 if (hard_regno_nregs (regno, smode) > 1) | |
| 1150 smode = mode_for_size (GET_MODE_SIZE (mode) / nregs, | |
| 1151 GET_MODE_CLASS (mode), 0).require (); | |
| 1152 XVECEXP (mem, 0, i) = gen_rtx_REG (smode, regno + i); | |
|
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1153 } |
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1154 } |
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1155 |
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1156 gcc_assert (GET_MODE (mem) == mode); |
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1157 *loc = mem; |
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1158 } |
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1159 |
| 0 | 1160 |
| 1161 /* Insert a sequence of insns to restore. Place these insns in front of | |
| 1162 CHAIN if BEFORE_P is nonzero, behind the insn otherwise. MAXRESTORE is | |
| 1163 the maximum number of registers which should be restored during this call. | |
| 1164 It should never be less than 1 since we only work with entire registers. | |
| 1165 | |
| 1166 Note that we have verified in init_caller_save that we can do this | |
| 1167 with a simple SET, so use it. Set INSN_CODE to what we save there | |
| 1168 since the address might not be valid so the insn might not be recognized. | |
| 1169 These insns will be reloaded and have register elimination done by | |
| 1170 find_reload, so we need not worry about that here. | |
| 1171 | |
| 1172 Return the extra number of registers saved. */ | |
| 1173 | |
| 1174 static int | |
| 1175 insert_restore (struct insn_chain *chain, int before_p, int regno, | |
| 111 | 1176 int maxrestore, machine_mode *save_mode) |
| 0 | 1177 { |
| 1178 int i, k; | |
| 1179 rtx pat = NULL_RTX; | |
| 1180 int code; | |
| 1181 unsigned int numregs = 0; | |
| 1182 struct insn_chain *new_chain; | |
| 1183 rtx mem; | |
| 1184 | |
| 1185 /* A common failure mode if register status is not correct in the | |
| 1186 RTL is for this routine to be called with a REGNO we didn't | |
| 1187 expect to save. That will cause us to write an insn with a (nil) | |
| 1188 SET_DEST or SET_SRC. Instead of doing so and causing a crash | |
| 1189 later, check for this common case here instead. This will remove | |
| 1190 one step in debugging such problems. */ | |
| 1191 gcc_assert (regno_save_mem[regno][1]); | |
| 1192 | |
| 1193 /* Get the pattern to emit and update our status. | |
| 1194 | |
| 1195 See if we can restore `maxrestore' registers at once. Work | |
| 1196 backwards to the single register case. */ | |
| 1197 for (i = maxrestore; i > 0; i--) | |
| 1198 { | |
| 1199 int j; | |
| 1200 int ok = 1; | |
| 1201 | |
| 1202 if (regno_save_mem[regno][i] == 0) | |
| 1203 continue; | |
| 1204 | |
| 1205 for (j = 0; j < i; j++) | |
| 1206 if (! TEST_HARD_REG_BIT (hard_regs_saved, regno + j)) | |
| 1207 { | |
| 1208 ok = 0; | |
| 1209 break; | |
| 1210 } | |
| 1211 /* Must do this one restore at a time. */ | |
| 1212 if (! ok) | |
| 1213 continue; | |
| 1214 | |
| 1215 numregs = i; | |
| 1216 break; | |
| 1217 } | |
| 1218 | |
| 1219 mem = regno_save_mem [regno][numregs]; | |
| 1220 if (save_mode [regno] != VOIDmode | |
| 1221 && save_mode [regno] != GET_MODE (mem) | |
| 111 | 1222 && numregs == hard_regno_nregs (regno, save_mode [regno]) |
| 0 | 1223 /* Check that insn to restore REGNO in save_mode[regno] is |
| 1224 correct. */ | |
| 1225 && reg_save_code (regno, save_mode[regno]) >= 0) | |
|
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1226 mem = adjust_address_nv (mem, save_mode[regno], 0); |
| 0 | 1227 else |
| 1228 mem = copy_rtx (mem); | |
| 1229 | |
| 1230 /* Verify that the alignment of spill space is equal to or greater | |
| 1231 than required. */ | |
| 1232 gcc_assert (MIN (MAX_SUPPORTED_STACK_ALIGNMENT, | |
| 1233 GET_MODE_ALIGNMENT (GET_MODE (mem))) <= MEM_ALIGN (mem)); | |
| 1234 | |
| 111 | 1235 pat = gen_rtx_SET (gen_rtx_REG (GET_MODE (mem), regno), mem); |
| 0 | 1236 code = reg_restore_code (regno, GET_MODE (mem)); |
| 1237 new_chain = insert_one_insn (chain, before_p, code, pat); | |
| 1238 | |
| 1239 /* Clear status for all registers we restored. */ | |
| 1240 for (k = 0; k < i; k++) | |
| 1241 { | |
| 1242 CLEAR_HARD_REG_BIT (hard_regs_saved, regno + k); | |
| 1243 SET_REGNO_REG_SET (&new_chain->dead_or_set, regno + k); | |
| 1244 n_regs_saved--; | |
| 1245 } | |
| 1246 | |
| 1247 /* Tell our callers how many extra registers we saved/restored. */ | |
| 1248 return numregs - 1; | |
| 1249 } | |
| 1250 | |
| 1251 /* Like insert_restore above, but save registers instead. */ | |
| 1252 | |
| 1253 static int | |
| 1254 insert_save (struct insn_chain *chain, int before_p, int regno, | |
| 111 | 1255 HARD_REG_SET *to_save, machine_mode *save_mode) |
| 0 | 1256 { |
| 1257 int i; | |
| 1258 unsigned int k; | |
| 1259 rtx pat = NULL_RTX; | |
| 1260 int code; | |
| 1261 unsigned int numregs = 0; | |
| 1262 struct insn_chain *new_chain; | |
| 1263 rtx mem; | |
| 1264 | |
| 1265 /* A common failure mode if register status is not correct in the | |
| 1266 RTL is for this routine to be called with a REGNO we didn't | |
| 1267 expect to save. That will cause us to write an insn with a (nil) | |
| 1268 SET_DEST or SET_SRC. Instead of doing so and causing a crash | |
| 1269 later, check for this common case here. This will remove one | |
| 1270 step in debugging such problems. */ | |
| 1271 gcc_assert (regno_save_mem[regno][1]); | |
| 1272 | |
| 1273 /* Get the pattern to emit and update our status. | |
| 1274 | |
| 1275 See if we can save several registers with a single instruction. | |
| 1276 Work backwards to the single register case. */ | |
| 1277 for (i = MOVE_MAX_WORDS; i > 0; i--) | |
| 1278 { | |
| 1279 int j; | |
| 1280 int ok = 1; | |
| 1281 if (regno_save_mem[regno][i] == 0) | |
| 1282 continue; | |
| 1283 | |
| 1284 for (j = 0; j < i; j++) | |
| 1285 if (! TEST_HARD_REG_BIT (*to_save, regno + j)) | |
| 1286 { | |
| 1287 ok = 0; | |
| 1288 break; | |
| 1289 } | |
| 1290 /* Must do this one save at a time. */ | |
| 1291 if (! ok) | |
| 1292 continue; | |
| 1293 | |
| 1294 numregs = i; | |
| 1295 break; | |
| 1296 } | |
| 1297 | |
| 1298 mem = regno_save_mem [regno][numregs]; | |
| 1299 if (save_mode [regno] != VOIDmode | |
| 1300 && save_mode [regno] != GET_MODE (mem) | |
| 111 | 1301 && numregs == hard_regno_nregs (regno, save_mode [regno]) |
| 0 | 1302 /* Check that insn to save REGNO in save_mode[regno] is |
| 1303 correct. */ | |
| 1304 && reg_save_code (regno, save_mode[regno]) >= 0) | |
|
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1305 mem = adjust_address_nv (mem, save_mode[regno], 0); |
| 0 | 1306 else |
| 1307 mem = copy_rtx (mem); | |
| 1308 | |
| 1309 /* Verify that the alignment of spill space is equal to or greater | |
| 1310 than required. */ | |
| 1311 gcc_assert (MIN (MAX_SUPPORTED_STACK_ALIGNMENT, | |
| 1312 GET_MODE_ALIGNMENT (GET_MODE (mem))) <= MEM_ALIGN (mem)); | |
| 1313 | |
| 111 | 1314 pat = gen_rtx_SET (mem, gen_rtx_REG (GET_MODE (mem), regno)); |
| 0 | 1315 code = reg_save_code (regno, GET_MODE (mem)); |
| 1316 new_chain = insert_one_insn (chain, before_p, code, pat); | |
| 1317 | |
| 1318 /* Set hard_regs_saved and dead_or_set for all the registers we saved. */ | |
| 1319 for (k = 0; k < numregs; k++) | |
| 1320 { | |
| 1321 SET_HARD_REG_BIT (hard_regs_saved, regno + k); | |
| 1322 SET_REGNO_REG_SET (&new_chain->dead_or_set, regno + k); | |
| 1323 n_regs_saved++; | |
| 1324 } | |
| 1325 | |
| 1326 /* Tell our callers how many extra registers we saved/restored. */ | |
| 1327 return numregs - 1; | |
| 1328 } | |
| 1329 | |
| 1330 /* A note_uses callback used by insert_one_insn. Add the hard-register | |
| 1331 equivalent of each REG to regset DATA. */ | |
| 1332 | |
| 1333 static void | |
| 1334 add_used_regs (rtx *loc, void *data) | |
| 1335 { | |
| 111 | 1336 subrtx_iterator::array_type array; |
| 1337 FOR_EACH_SUBRTX (iter, array, *loc, NONCONST) | |
| 1338 { | |
| 1339 const_rtx x = *iter; | |
| 1340 if (REG_P (x)) | |
| 1341 { | |
| 1342 unsigned int regno = REGNO (x); | |
| 1343 if (HARD_REGISTER_NUM_P (regno)) | |
| 1344 bitmap_set_range ((regset) data, regno, REG_NREGS (x)); | |
| 1345 else | |
| 1346 gcc_checking_assert (reg_renumber[regno] < 0); | |
| 1347 } | |
| 1348 } | |
| 0 | 1349 } |
| 1350 | |
| 1351 /* Emit a new caller-save insn and set the code. */ | |
| 1352 static struct insn_chain * | |
| 1353 insert_one_insn (struct insn_chain *chain, int before_p, int code, rtx pat) | |
| 1354 { | |
| 111 | 1355 rtx_insn *insn = chain->insn; |
| 0 | 1356 struct insn_chain *new_chain; |
| 1357 | |
| 1358 /* If INSN references CC0, put our insns in front of the insn that sets | |
| 1359 CC0. This is always safe, since the only way we could be passed an | |
| 1360 insn that references CC0 is for a restore, and doing a restore earlier | |
| 1361 isn't a problem. We do, however, assume here that CALL_INSNs don't | |
| 1362 reference CC0. Guard against non-INSN's like CODE_LABEL. */ | |
| 1363 | |
| 111 | 1364 if (HAVE_cc0 && (NONJUMP_INSN_P (insn) || JUMP_P (insn)) |
| 0 | 1365 && before_p |
| 1366 && reg_referenced_p (cc0_rtx, PATTERN (insn))) | |
| 1367 chain = chain->prev, insn = chain->insn; | |
| 1368 | |
| 1369 new_chain = new_insn_chain (); | |
| 1370 if (before_p) | |
| 1371 { | |
| 1372 rtx link; | |
| 1373 | |
| 1374 new_chain->prev = chain->prev; | |
| 1375 if (new_chain->prev != 0) | |
| 1376 new_chain->prev->next = new_chain; | |
| 1377 else | |
| 1378 reload_insn_chain = new_chain; | |
| 1379 | |
| 1380 chain->prev = new_chain; | |
| 1381 new_chain->next = chain; | |
| 1382 new_chain->insn = emit_insn_before (pat, insn); | |
| 1383 /* ??? It would be nice if we could exclude the already / still saved | |
| 1384 registers from the live sets. */ | |
| 1385 COPY_REG_SET (&new_chain->live_throughout, &chain->live_throughout); | |
| 1386 note_uses (&PATTERN (chain->insn), add_used_regs, | |
| 1387 &new_chain->live_throughout); | |
| 1388 /* If CHAIN->INSN is a call, then the registers which contain | |
| 1389 the arguments to the function are live in the new insn. */ | |
| 1390 if (CALL_P (chain->insn)) | |
| 1391 for (link = CALL_INSN_FUNCTION_USAGE (chain->insn); | |
| 1392 link != NULL_RTX; | |
| 1393 link = XEXP (link, 1)) | |
| 1394 note_uses (&XEXP (link, 0), add_used_regs, | |
| 1395 &new_chain->live_throughout); | |
| 1396 | |
| 1397 CLEAR_REG_SET (&new_chain->dead_or_set); | |
| 111 | 1398 if (chain->insn == BB_HEAD (BASIC_BLOCK_FOR_FN (cfun, chain->block))) |
| 1399 BB_HEAD (BASIC_BLOCK_FOR_FN (cfun, chain->block)) = new_chain->insn; | |
| 0 | 1400 } |
| 1401 else | |
| 1402 { | |
| 1403 new_chain->next = chain->next; | |
| 1404 if (new_chain->next != 0) | |
| 1405 new_chain->next->prev = new_chain; | |
| 1406 chain->next = new_chain; | |
| 1407 new_chain->prev = chain; | |
| 1408 new_chain->insn = emit_insn_after (pat, insn); | |
| 1409 /* ??? It would be nice if we could exclude the already / still saved | |
| 1410 registers from the live sets, and observe REG_UNUSED notes. */ | |
| 1411 COPY_REG_SET (&new_chain->live_throughout, &chain->live_throughout); | |
| 1412 /* Registers that are set in CHAIN->INSN live in the new insn. | |
| 1413 (Unless there is a REG_UNUSED note for them, but we don't | |
| 1414 look for them here.) */ | |
| 1415 note_stores (PATTERN (chain->insn), add_stored_regs, | |
| 1416 &new_chain->live_throughout); | |
| 1417 CLEAR_REG_SET (&new_chain->dead_or_set); | |
| 111 | 1418 if (chain->insn == BB_END (BASIC_BLOCK_FOR_FN (cfun, chain->block))) |
| 1419 BB_END (BASIC_BLOCK_FOR_FN (cfun, chain->block)) = new_chain->insn; | |
| 0 | 1420 } |
| 1421 new_chain->block = chain->block; | |
| 1422 new_chain->is_caller_save_insn = 1; | |
| 1423 | |
| 1424 INSN_CODE (new_chain->insn) = code; | |
| 1425 return new_chain; | |
| 1426 } | |
| 1427 #include "gt-caller-save.h" |