Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/alpha/predicates.md @ 111:04ced10e8804
gcc 7
author | kono |
---|---|
date | Fri, 27 Oct 2017 22:46:09 +0900 |
parents | f6334be47118 |
children | 84e7813d76e9 |
rev | line source |
---|---|
0 | 1 ;; Predicate definitions for DEC Alpha. |
111 | 2 ;; Copyright (C) 2004-2017 Free Software Foundation, Inc. |
0 | 3 ;; |
4 ;; This file is part of GCC. | |
5 ;; | |
6 ;; GCC is free software; you can redistribute it and/or modify | |
7 ;; it under the terms of the GNU General Public License as published by | |
8 ;; the Free Software Foundation; either version 3, or (at your option) | |
9 ;; any later version. | |
10 ;; | |
11 ;; GCC is distributed in the hope that it will be useful, | |
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 ;; GNU General Public License for more details. | |
15 ;; | |
16 ;; You should have received a copy of the GNU General Public License | |
17 ;; along with GCC; see the file COPYING3. If not see | |
18 ;; <http://www.gnu.org/licenses/>. | |
19 | |
20 ;; Return 1 if OP is the zero constant for MODE. | |
21 (define_predicate "const0_operand" | |
111 | 22 (and (match_code "const_int,const_wide_int,const_double,const_vector") |
0 | 23 (match_test "op == CONST0_RTX (mode)"))) |
24 | |
25 ;; Returns true if OP is either the constant zero or a register. | |
26 (define_predicate "reg_or_0_operand" | |
27 (ior (match_operand 0 "register_operand") | |
28 (match_operand 0 "const0_operand"))) | |
29 | |
30 ;; Return 1 if OP is a constant in the range of 0-63 (for a shift) or | |
31 ;; any register. | |
32 (define_predicate "reg_or_6bit_operand" | |
33 (if_then_else (match_code "const_int") | |
34 (match_test "INTVAL (op) >= 0 && INTVAL (op) < 64") | |
35 (match_operand 0 "register_operand"))) | |
36 | |
37 ;; Return 1 if OP is an 8-bit constant. | |
38 (define_predicate "cint8_operand" | |
39 (and (match_code "const_int") | |
40 (match_test "INTVAL (op) >= 0 && INTVAL (op) < 256"))) | |
41 | |
42 ;; Return 1 if OP is an 8-bit constant or any register. | |
43 (define_predicate "reg_or_8bit_operand" | |
44 (if_then_else (match_code "const_int") | |
45 (match_test "INTVAL (op) >= 0 && INTVAL (op) < 256") | |
46 (match_operand 0 "register_operand"))) | |
47 | |
48 ;; Return 1 if OP is a constant or any register. | |
49 (define_predicate "reg_or_cint_operand" | |
50 (ior (match_operand 0 "register_operand") | |
51 (match_operand 0 "const_int_operand"))) | |
52 | |
53 ;; Return 1 if the operand is a valid second operand to an add insn. | |
54 (define_predicate "add_operand" | |
55 (if_then_else (match_code "const_int") | |
56 (match_test "satisfies_constraint_K (op) || satisfies_constraint_L (op)") | |
57 (match_operand 0 "register_operand"))) | |
58 | |
59 ;; Return 1 if the operand is a valid second operand to a | |
60 ;; sign-extending add insn. | |
61 (define_predicate "sext_add_operand" | |
62 (if_then_else (match_code "const_int") | |
63 (match_test "satisfies_constraint_I (op) || satisfies_constraint_O (op)") | |
64 (match_operand 0 "register_operand"))) | |
65 | |
66 ;; Return 1 if the operand is a non-symbolic constant operand that | |
67 ;; does not satisfy add_operand. | |
68 (define_predicate "non_add_const_operand" | |
111 | 69 (and (match_code "const_int,const_wide_int,const_double,const_vector") |
0 | 70 (not (match_operand 0 "add_operand")))) |
71 | |
72 ;; Return 1 if the operand is a non-symbolic, nonzero constant operand. | |
73 (define_predicate "non_zero_const_operand" | |
111 | 74 (and (match_code "const_int,const_wide_int,const_double,const_vector") |
75 (not (match_test "op == CONST0_RTX (mode)")))) | |
0 | 76 |
77 ;; Return 1 if OP is the constant 4 or 8. | |
78 (define_predicate "const48_operand" | |
79 (and (match_code "const_int") | |
80 (match_test "INTVAL (op) == 4 || INTVAL (op) == 8"))) | |
81 | |
82 ;; Return 1 if OP is a valid first operand to an AND insn. | |
83 (define_predicate "and_operand" | |
84 (if_then_else (match_code "const_int") | |
85 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 0x100 | |
86 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100 | |
87 || zap_mask (INTVAL (op))") | |
111 | 88 (match_operand 0 "register_operand"))) |
0 | 89 |
90 ;; Return 1 if OP is a valid first operand to an IOR or XOR insn. | |
91 (define_predicate "or_operand" | |
92 (if_then_else (match_code "const_int") | |
93 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 0x100 | |
94 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100") | |
95 (match_operand 0 "register_operand"))) | |
96 | |
97 ;; Return 1 if OP is a constant that is the width, in bits, of an integral | |
98 ;; mode not larger than DImode. | |
99 (define_predicate "mode_width_operand" | |
100 (match_code "const_int") | |
101 { | |
102 HOST_WIDE_INT i = INTVAL (op); | |
103 return i == 8 || i == 16 || i == 32 || i == 64; | |
104 }) | |
105 | |
106 ;; Return 1 if OP is a constant that is a mask of ones of width of an | |
107 ;; integral machine mode not larger than DImode. | |
108 (define_predicate "mode_mask_operand" | |
111 | 109 (match_code "const_int") |
0 | 110 { |
111 | 111 HOST_WIDE_INT value = INTVAL (op); |
0 | 112 |
111 | 113 if (value == 0xff) |
114 return 1; | |
115 if (value == 0xffff) | |
116 return 1; | |
117 if (value == 0xffffffff) | |
118 return 1; | |
119 if (value == -1) | |
120 return 1; | |
121 | |
0 | 122 return 0; |
123 }) | |
124 | |
125 ;; Return 1 if OP is a multiple of 8 less than 64. | |
126 (define_predicate "mul8_operand" | |
127 (match_code "const_int") | |
128 { | |
129 unsigned HOST_WIDE_INT i = INTVAL (op); | |
130 return i < 64 && i % 8 == 0; | |
131 }) | |
132 | |
133 ;; Return 1 if OP is a hard floating-point register. | |
134 (define_predicate "hard_fp_register_operand" | |
135 (match_operand 0 "register_operand") | |
136 { | |
111 | 137 if (SUBREG_P (op)) |
0 | 138 op = SUBREG_REG (op); |
139 return REGNO_REG_CLASS (REGNO (op)) == FLOAT_REGS; | |
140 }) | |
141 | |
142 ;; Return 1 if OP is a hard general register. | |
143 (define_predicate "hard_int_register_operand" | |
144 (match_operand 0 "register_operand") | |
145 { | |
111 | 146 if (SUBREG_P (op)) |
0 | 147 op = SUBREG_REG (op); |
148 return REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS; | |
149 }) | |
150 | |
151 ;; Return 1 if OP is a valid operand for the source of a move insn. | |
152 (define_predicate "input_operand" | |
111 | 153 (match_operand 0 "general_operand") |
0 | 154 { |
155 switch (GET_CODE (op)) | |
156 { | |
157 case LABEL_REF: | |
158 case SYMBOL_REF: | |
159 case CONST: | |
160 if (TARGET_EXPLICIT_RELOCS) | |
161 { | |
162 /* We don't split symbolic operands into something unintelligable | |
163 until after reload, but we do not wish non-small, non-global | |
164 symbolic operands to be reconstructed from their high/lo_sum | |
165 form. */ | |
166 return (small_symbolic_operand (op, mode) | |
167 || global_symbolic_operand (op, mode) | |
168 || gotdtp_symbolic_operand (op, mode) | |
169 || gottp_symbolic_operand (op, mode)); | |
170 } | |
111 | 171 /* VMS still has a 32-bit mode. */ |
172 return mode == ptr_mode || mode == Pmode; | |
0 | 173 |
174 case HIGH: | |
175 return (TARGET_EXPLICIT_RELOCS | |
176 && local_symbolic_operand (XEXP (op, 0), mode)); | |
177 | |
178 case REG: | |
179 return 1; | |
180 | |
181 case SUBREG: | |
182 if (register_operand (op, mode)) | |
183 return 1; | |
111 | 184 /* fall through */ |
0 | 185 case MEM: |
186 return ((TARGET_BWX || (mode != HImode && mode != QImode)) | |
187 && general_operand (op, mode)); | |
188 | |
111 | 189 case CONST_WIDE_INT: |
0 | 190 case CONST_DOUBLE: |
191 return op == CONST0_RTX (mode); | |
192 | |
193 case CONST_VECTOR: | |
194 if (reload_in_progress || reload_completed) | |
111 | 195 return alpha_legitimate_constant_p (mode, op); |
0 | 196 return op == CONST0_RTX (mode); |
197 | |
198 case CONST_INT: | |
199 if (mode == QImode || mode == HImode) | |
200 return true; | |
201 if (reload_in_progress || reload_completed) | |
111 | 202 return alpha_legitimate_constant_p (mode, op); |
0 | 203 return add_operand (op, mode); |
204 | |
205 default: | |
206 gcc_unreachable (); | |
207 } | |
208 return 0; | |
209 }) | |
210 | |
211 ;; Return 1 if OP is a SYMBOL_REF for a function known to be in this | |
212 ;; file, and in the same section as the current function. | |
213 | |
214 (define_predicate "samegp_function_operand" | |
215 (match_code "symbol_ref") | |
216 { | |
217 /* Easy test for recursion. */ | |
218 if (op == XEXP (DECL_RTL (current_function_decl), 0)) | |
219 return true; | |
220 | |
221 /* Functions that are not local can be overridden, and thus may | |
222 not share the same gp. */ | |
223 if (! SYMBOL_REF_LOCAL_P (op)) | |
224 return false; | |
225 | |
226 /* If -msmall-data is in effect, assume that there is only one GP | |
227 for the module, and so any local symbol has this property. We | |
228 need explicit relocations to be able to enforce this for symbols | |
229 not defined in this unit of translation, however. */ | |
230 if (TARGET_EXPLICIT_RELOCS && TARGET_SMALL_DATA) | |
231 return true; | |
232 | |
233 /* Functions that are not external are defined in this UoT, | |
234 and thus must share the same gp. */ | |
235 return ! SYMBOL_REF_EXTERNAL_P (op); | |
236 }) | |
237 | |
238 ;; Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. | |
239 (define_predicate "direct_call_operand" | |
240 (match_operand 0 "samegp_function_operand") | |
241 { | |
242 /* If profiling is implemented via linker tricks, we can't jump | |
243 to the nogp alternate entry point. Note that crtl->profile | |
244 would not be correct, since that doesn't indicate if the target | |
245 function uses profiling. */ | |
246 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test, | |
247 but is approximately correct for the OSF ABIs. Don't know | |
248 what to do for VMS, NT, or UMK. */ | |
249 if (!TARGET_PROFILING_NEEDS_GP && profile_flag) | |
250 return false; | |
251 | |
252 /* Must be a function. In some cases folks create thunks in static | |
253 data structures and then make calls to them. If we allow the | |
254 direct call, we'll get an error from the linker about !samegp reloc | |
255 against a symbol without a .prologue directive. */ | |
256 if (!SYMBOL_REF_FUNCTION_P (op)) | |
257 return false; | |
258 | |
259 /* Must be "near" so that the branch is assumed to reach. With | |
260 -msmall-text, this is assumed true of all local symbols. Since | |
261 we've already checked samegp, locality is already assured. */ | |
262 if (TARGET_SMALL_TEXT) | |
263 return true; | |
264 | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
265 return false; |
0 | 266 }) |
267 | |
268 ;; Return 1 if OP is a valid operand for the MEM of a CALL insn. | |
269 ;; | |
270 ;; For TARGET_ABI_OSF, we want to restrict to R27 or a pseudo. | |
271 | |
272 (define_predicate "call_operand" | |
111 | 273 (ior (match_code "symbol_ref") |
274 (and (match_code "reg") | |
275 (ior (not (match_test "TARGET_ABI_OSF")) | |
276 (not (match_test "HARD_REGISTER_P (op)")) | |
277 (match_test "REGNO (op) == R27_REG"))))) | |
0 | 278 |
279 ;; Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing | |
280 ;; a (non-tls) variable known to be defined in this file. | |
281 (define_predicate "local_symbolic_operand" | |
282 (match_code "label_ref,const,symbol_ref") | |
283 { | |
284 if (GET_CODE (op) == CONST | |
285 && GET_CODE (XEXP (op, 0)) == PLUS | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
286 && CONST_INT_P (XEXP (XEXP (op, 0), 1))) |
0 | 287 op = XEXP (XEXP (op, 0), 0); |
288 | |
289 if (GET_CODE (op) == LABEL_REF) | |
290 return 1; | |
291 | |
292 if (GET_CODE (op) != SYMBOL_REF) | |
293 return 0; | |
294 | |
295 return (SYMBOL_REF_LOCAL_P (op) | |
296 && !SYMBOL_REF_WEAK (op) | |
297 && !SYMBOL_REF_TLS_MODEL (op)); | |
298 }) | |
299 | |
300 ;; Return true if OP is a SYMBOL_REF or CONST referencing a variable | |
301 ;; known to be defined in this file in the small data area. | |
302 (define_predicate "small_symbolic_operand" | |
303 (match_code "const,symbol_ref") | |
304 { | |
111 | 305 HOST_WIDE_INT ofs = 0, max_ofs = 0; |
306 | |
0 | 307 if (! TARGET_SMALL_DATA) |
111 | 308 return false; |
0 | 309 |
310 if (GET_CODE (op) == CONST | |
311 && GET_CODE (XEXP (op, 0)) == PLUS | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
312 && CONST_INT_P (XEXP (XEXP (op, 0), 1))) |
111 | 313 { |
314 ofs = INTVAL (XEXP (XEXP (op, 0), 1)); | |
315 op = XEXP (XEXP (op, 0), 0); | |
316 } | |
0 | 317 |
318 if (GET_CODE (op) != SYMBOL_REF) | |
111 | 319 return false; |
0 | 320 |
321 /* ??? There's no encode_section_info equivalent for the rtl | |
322 constant pool, so SYMBOL_FLAG_SMALL never gets set. */ | |
323 if (CONSTANT_POOL_ADDRESS_P (op)) | |
111 | 324 { |
325 max_ofs = GET_MODE_SIZE (get_pool_mode (op)); | |
326 if (max_ofs > g_switch_value) | |
327 return false; | |
328 } | |
329 else if (SYMBOL_REF_LOCAL_P (op) | |
330 && SYMBOL_REF_SMALL_P (op) | |
331 && !SYMBOL_REF_WEAK (op) | |
332 && !SYMBOL_REF_TLS_MODEL (op)) | |
333 { | |
334 if (SYMBOL_REF_DECL (op)) | |
335 max_ofs = tree_to_uhwi (DECL_SIZE_UNIT (SYMBOL_REF_DECL (op))); | |
336 } | |
337 else | |
338 return false; | |
0 | 339 |
111 | 340 /* Given that we know that the GP is always 8 byte aligned, we can |
341 always adjust by 7 without overflowing. */ | |
342 if (max_ofs < 8) | |
343 max_ofs = 8; | |
344 | |
345 /* Since we know this is an object in a small data section, we know the | |
346 entire section is addressable via GP. We don't know where the section | |
347 boundaries are, but we know the entire object is within. */ | |
348 return IN_RANGE (ofs, 0, max_ofs - 1); | |
0 | 349 }) |
350 | |
351 ;; Return true if OP is a SYMBOL_REF or CONST referencing a variable | |
352 ;; not known (or known not) to be defined in this file. | |
353 (define_predicate "global_symbolic_operand" | |
354 (match_code "const,symbol_ref") | |
355 { | |
356 if (GET_CODE (op) == CONST | |
357 && GET_CODE (XEXP (op, 0)) == PLUS | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
358 && CONST_INT_P (XEXP (XEXP (op, 0), 1))) |
0 | 359 op = XEXP (XEXP (op, 0), 0); |
360 | |
361 if (GET_CODE (op) != SYMBOL_REF) | |
362 return 0; | |
363 | |
364 return ((!SYMBOL_REF_LOCAL_P (op) || SYMBOL_REF_WEAK (op)) | |
365 && !SYMBOL_REF_TLS_MODEL (op)); | |
366 }) | |
367 | |
368 ;; Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref, | |
369 ;; possibly with an offset. | |
370 (define_predicate "symbolic_operand" | |
371 (ior (match_code "symbol_ref,label_ref") | |
372 (and (match_code "const") | |
111 | 373 (match_code "plus" "0") |
374 (match_code "symbol_ref,label_ref" "00") | |
375 (match_code "const_int" "01")))) | |
0 | 376 |
377 ;; Return true if OP is valid for 16-bit DTP relative relocations. | |
378 (define_predicate "dtp16_symbolic_operand" | |
379 (and (match_code "const") | |
380 (match_test "tls_symbolic_operand_1 (op, 16, UNSPEC_DTPREL)"))) | |
381 | |
382 ;; Return true if OP is valid for 32-bit DTP relative relocations. | |
383 (define_predicate "dtp32_symbolic_operand" | |
384 (and (match_code "const") | |
385 (match_test "tls_symbolic_operand_1 (op, 32, UNSPEC_DTPREL)"))) | |
386 | |
387 ;; Return true if OP is valid for 64-bit DTP relative relocations. | |
388 (define_predicate "gotdtp_symbolic_operand" | |
389 (and (match_code "const") | |
390 (match_test "tls_symbolic_operand_1 (op, 64, UNSPEC_DTPREL)"))) | |
391 | |
392 ;; Return true if OP is valid for 16-bit TP relative relocations. | |
393 (define_predicate "tp16_symbolic_operand" | |
394 (and (match_code "const") | |
395 (match_test "tls_symbolic_operand_1 (op, 16, UNSPEC_TPREL)"))) | |
396 | |
397 ;; Return true if OP is valid for 32-bit TP relative relocations. | |
398 (define_predicate "tp32_symbolic_operand" | |
399 (and (match_code "const") | |
400 (match_test "tls_symbolic_operand_1 (op, 32, UNSPEC_TPREL)"))) | |
401 | |
402 ;; Return true if OP is valid for 64-bit TP relative relocations. | |
403 (define_predicate "gottp_symbolic_operand" | |
404 (and (match_code "const") | |
405 (match_test "tls_symbolic_operand_1 (op, 64, UNSPEC_TPREL)"))) | |
406 | |
407 ;; Return 1 if this memory address is a known aligned register plus | |
408 ;; a constant. It must be a valid address. This means that we can do | |
409 ;; this as an aligned reference plus some offset. | |
410 ;; | |
411 ;; Take into account what reload will do. Oh god this is awful. | |
412 ;; The horrible comma-operator construct below is to prevent genrecog | |
413 ;; from thinking that this predicate accepts REG and SUBREG. We don't | |
414 ;; use recog during reload, so pretending these codes are accepted | |
415 ;; pessimizes things a tad. | |
416 | |
417 (define_special_predicate "aligned_memory_operand" | |
418 (ior (match_test "op = resolve_reload_operand (op), 0") | |
419 (match_code "mem")) | |
420 { | |
421 rtx base; | |
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
422 int offset; |
0 | 423 |
424 if (MEM_ALIGN (op) >= 32) | |
425 return 1; | |
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
426 |
0 | 427 op = XEXP (op, 0); |
428 | |
429 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo) | |
430 sorts of constructs. Dig for the real base register. */ | |
431 if (reload_in_progress | |
432 && GET_CODE (op) == PLUS | |
433 && GET_CODE (XEXP (op, 0)) == PLUS) | |
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
434 { |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
435 base = XEXP (XEXP (op, 0), 0); |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
436 offset = INTVAL (XEXP (op, 1)); |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
437 } |
0 | 438 else |
439 { | |
440 if (! memory_address_p (mode, op)) | |
441 return 0; | |
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
442 if (GET_CODE (op) == PLUS) |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
443 { |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
444 base = XEXP (op, 0); |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
445 offset = INTVAL (XEXP (op, 1)); |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
446 } |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
447 else |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
448 { |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
449 base = op; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
450 offset = 0; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
451 } |
0 | 452 } |
453 | |
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
454 if (offset % GET_MODE_SIZE (mode)) |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
455 return 0; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
456 |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
457 return (REG_P (base) && REGNO_POINTER_ALIGN (REGNO (base)) >= 32); |
0 | 458 }) |
459 | |
460 ;; Similar, but return 1 if OP is a MEM which is not alignable. | |
461 | |
462 (define_special_predicate "unaligned_memory_operand" | |
463 (ior (match_test "op = resolve_reload_operand (op), 0") | |
464 (match_code "mem")) | |
465 { | |
466 rtx base; | |
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
467 int offset; |
0 | 468 |
469 if (MEM_ALIGN (op) >= 32) | |
470 return 0; | |
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
471 |
0 | 472 op = XEXP (op, 0); |
473 | |
474 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo) | |
475 sorts of constructs. Dig for the real base register. */ | |
476 if (reload_in_progress | |
477 && GET_CODE (op) == PLUS | |
478 && GET_CODE (XEXP (op, 0)) == PLUS) | |
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
479 { |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
480 base = XEXP (XEXP (op, 0), 0); |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
481 offset = INTVAL (XEXP (op, 1)); |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
482 } |
0 | 483 else |
484 { | |
485 if (! memory_address_p (mode, op)) | |
486 return 0; | |
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
487 if (GET_CODE (op) == PLUS) |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
488 { |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
489 base = XEXP (op, 0); |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
490 offset = INTVAL (XEXP (op, 1)); |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
491 } |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
492 else |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
493 { |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
494 base = op; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
495 offset = 0; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
496 } |
0 | 497 } |
498 | |
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
499 if (offset % GET_MODE_SIZE (mode)) |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
500 return 1; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
501 |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
502 return (REG_P (base) && REGNO_POINTER_ALIGN (REGNO (base)) < 32); |
0 | 503 }) |
504 | |
505 ;; Return 1 if OP is any memory location. During reload a pseudo matches. | |
506 (define_special_predicate "any_memory_operand" | |
507 (match_code "mem,reg,subreg") | |
508 { | |
111 | 509 if (SUBREG_P (op)) |
0 | 510 op = SUBREG_REG (op); |
511 | |
512 if (MEM_P (op)) | |
513 return true; | |
514 if (reload_in_progress && REG_P (op)) | |
515 { | |
516 unsigned regno = REGNO (op); | |
517 if (HARD_REGISTER_NUM_P (regno)) | |
518 return false; | |
519 else | |
520 return reg_renumber[regno] < 0; | |
521 } | |
522 | |
523 return false; | |
524 }) | |
525 | |
526 ;; Returns 1 if OP is not an eliminable register. | |
527 ;; | |
528 ;; This exists to cure a pathological failure in the s8addq (et al) patterns, | |
529 ;; | |
530 ;; long foo () { long t; bar(); return (long) &t * 26107; } | |
531 ;; | |
532 ;; which run afoul of a hack in reload to cure a (presumably) similar | |
533 ;; problem with lea-type instructions on other targets. But there is | |
534 ;; one of us and many of them, so work around the problem by selectively | |
535 ;; preventing combine from making the optimization. | |
536 | |
537 (define_predicate "reg_not_elim_operand" | |
538 (match_operand 0 "register_operand") | |
539 { | |
111 | 540 if (SUBREG_P (op)) |
0 | 541 op = SUBREG_REG (op); |
542 return op != frame_pointer_rtx && op != arg_pointer_rtx; | |
543 }) | |
544 | |
545 ;; Accept a register, but not a subreg of any kind. This allows us to | |
546 ;; avoid pathological cases in reload wrt data movement common in | |
547 ;; int->fp conversion. */ | |
548 (define_predicate "reg_no_subreg_operand" | |
549 (and (match_code "reg") | |
550 (match_operand 0 "register_operand"))) | |
551 | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
552 ;; Return 1 if OP is a valid Alpha comparison operator for "cbranch" |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
553 ;; instructions. |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
554 (define_predicate "alpha_cbranch_operator" |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
555 (ior (match_operand 0 "ordered_comparison_operator") |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
556 (match_code "ordered,unordered"))) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
557 |
0 | 558 ;; Return 1 if OP is a valid Alpha comparison operator for "cmp" style |
559 ;; instructions. | |
560 (define_predicate "alpha_comparison_operator" | |
561 (match_code "eq,le,lt,leu,ltu")) | |
562 | |
563 ;; Similarly, but with swapped operands. | |
564 (define_predicate "alpha_swapped_comparison_operator" | |
565 (match_code "eq,ge,gt,gtu")) | |
566 | |
567 ;; Return 1 if OP is a valid Alpha comparison operator against zero | |
568 ;; for "bcc" style instructions. | |
569 (define_predicate "alpha_zero_comparison_operator" | |
570 (match_code "eq,ne,le,lt,leu,ltu")) | |
571 | |
572 ;; Return 1 if OP is a signed comparison operation. | |
573 (define_predicate "signed_comparison_operator" | |
574 (match_code "eq,ne,le,lt,ge,gt")) | |
575 | |
576 ;; Return 1 if OP is a valid Alpha floating point comparison operator. | |
577 (define_predicate "alpha_fp_comparison_operator" | |
578 (match_code "eq,le,lt,unordered")) | |
579 | |
580 ;; Return 1 if this is a divide or modulus operator. | |
581 (define_predicate "divmod_operator" | |
582 (match_code "div,mod,udiv,umod")) | |
583 | |
584 ;; Return 1 if this is a float->int conversion operator. | |
585 (define_predicate "fix_operator" | |
586 (match_code "fix,unsigned_fix")) | |
587 | |
588 ;; Recognize an addition operation that includes a constant. Used to | |
589 ;; convince reload to canonize (plus (plus reg c1) c2) during register | |
590 ;; elimination. | |
591 | |
592 (define_predicate "addition_operation" | |
593 (and (match_code "plus") | |
594 (match_test "register_operand (XEXP (op, 0), mode) | |
595 && satisfies_constraint_K (XEXP (op, 1))"))) | |
596 | |
597 ;; For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a | |
598 ;; small symbolic operand until after reload. At which point we need | |
599 ;; to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref)) | |
600 ;; so that sched2 has the proper dependency information. */ | |
601 (define_predicate "some_small_symbolic_operand" | |
602 (match_code "set,parallel,prefetch,unspec,unspec_volatile") | |
603 { | |
604 /* Avoid search unless necessary. */ | |
605 if (!TARGET_EXPLICIT_RELOCS || !reload_completed) | |
606 return false; | |
111 | 607 return some_small_symbolic_operand_int (op); |
0 | 608 }) |
111 | 609 |
610 ;; Accept a register, or a memory if BWX is enabled. | |
611 (define_predicate "reg_or_bwx_memory_operand" | |
612 (ior (match_operand 0 "register_operand") | |
613 (and (match_test "TARGET_BWX") | |
614 (match_operand 0 "memory_operand")))) | |
615 | |
616 ;; Accept a memory whose address is only a register. | |
617 (define_predicate "mem_noofs_operand" | |
618 (and (match_code "mem") | |
619 (match_code "reg" "0"))) |