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1 ;; Pipeline description for Motorola PowerPC e500mc core.
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2 ;; Copyright (C) 2008-2017 Free Software Foundation, Inc.
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3 ;; Contributed by Edmar Wienskoski (edmar@freescale.com)
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20 ;;
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21 ;; e500mc 32-bit SU(2), LSU, FPU, BPU
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22 ;; Max issue 3 insns/clock cycle (includes 1 branch)
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23 ;; FP is half clocked, timings of other instructions are as in the e500v2.
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24
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25 (define_automaton "e500mc_most,e500mc_long,e500mc_retire")
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26 (define_cpu_unit "e500mc_decode_0,e500mc_decode_1" "e500mc_most")
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27 (define_cpu_unit "e500mc_issue_0,e500mc_issue_1" "e500mc_most")
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28 (define_cpu_unit "e500mc_retire_0,e500mc_retire_1" "e500mc_retire")
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29
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30 ;; SU.
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31 (define_cpu_unit "e500mc_su0_stage0,e500mc_su1_stage0" "e500mc_most")
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32
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33 ;; MU.
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34 (define_cpu_unit "e500mc_mu_stage0,e500mc_mu_stage1" "e500mc_most")
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35 (define_cpu_unit "e500mc_mu_stage2,e500mc_mu_stage3" "e500mc_most")
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36
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37 ;; Non-pipelined division.
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38 (define_cpu_unit "e500mc_mu_div" "e500mc_long")
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39
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40 ;; LSU.
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41 (define_cpu_unit "e500mc_lsu" "e500mc_most")
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42
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43 ;; FPU.
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44 (define_cpu_unit "e500mc_fpu" "e500mc_most")
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45
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46 ;; Branch unit.
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47 (define_cpu_unit "e500mc_bu" "e500mc_most")
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48
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49 ;; The following units are used to make the automata deterministic.
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50 (define_cpu_unit "present_e500mc_decode_0" "e500mc_most")
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51 (define_cpu_unit "present_e500mc_issue_0" "e500mc_most")
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52 (define_cpu_unit "present_e500mc_retire_0" "e500mc_retire")
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53 (define_cpu_unit "present_e500mc_su0_stage0" "e500mc_most")
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54
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55 ;; The following sets to make automata deterministic when option ndfa is used.
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56 (presence_set "present_e500mc_decode_0" "e500mc_decode_0")
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57 (presence_set "present_e500mc_issue_0" "e500mc_issue_0")
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58 (presence_set "present_e500mc_retire_0" "e500mc_retire_0")
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59 (presence_set "present_e500mc_su0_stage0" "e500mc_su0_stage0")
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60
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61 ;; Some useful abbreviations.
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62 (define_reservation "e500mc_decode"
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63 "e500mc_decode_0|e500mc_decode_1+present_e500mc_decode_0")
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64 (define_reservation "e500mc_issue"
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65 "e500mc_issue_0|e500mc_issue_1+present_e500mc_issue_0")
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66 (define_reservation "e500mc_retire"
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67 "e500mc_retire_0|e500mc_retire_1+present_e500mc_retire_0")
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68 (define_reservation "e500mc_su_stage0"
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69 "e500mc_su0_stage0|e500mc_su1_stage0+present_e500mc_su0_stage0")
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70
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71 ;; Simple SU insns.
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72 (define_insn_reservation "e500mc_su" 1
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73 (and (eq_attr "type" "integer,add,logical,insert,cmp,\
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74 shift,trap,cntlz,exts,isel")
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75 (eq_attr "cpu" "ppce500mc"))
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76 "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
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77
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78 (define_insn_reservation "e500mc_two" 1
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79 (and (eq_attr "type" "two")
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80 (eq_attr "cpu" "ppce500mc"))
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81 "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\
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82 e500mc_issue+e500mc_su_stage0+e500mc_retire")
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83
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84 (define_insn_reservation "e500mc_three" 1
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85 (and (eq_attr "type" "three")
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86 (eq_attr "cpu" "ppce500mc"))
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87 "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\
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88 e500mc_issue+e500mc_su_stage0+e500mc_retire,\
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89 e500mc_issue+e500mc_su_stage0+e500mc_retire")
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90
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91 ;; Multiply.
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92 (define_insn_reservation "e500mc_multiply" 4
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93 (and (eq_attr "type" "mul")
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94 (eq_attr "cpu" "ppce500mc"))
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95 "e500mc_decode,e500mc_issue+e500mc_mu_stage0,e500mc_mu_stage1,\
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96 e500mc_mu_stage2,e500mc_mu_stage3+e500mc_retire")
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97
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98 ;; Divide. We use the average latency time here.
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99 (define_insn_reservation "e500mc_divide" 14
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100 (and (eq_attr "type" "div")
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101 (eq_attr "cpu" "ppce500mc"))
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102 "e500mc_decode,e500mc_issue+e500mc_mu_stage0+e500mc_mu_div,\
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103 e500mc_mu_div*13")
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104
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105 ;; Branch.
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106 (define_insn_reservation "e500mc_branch" 1
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107 (and (eq_attr "type" "jmpreg,branch,isync")
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108 (eq_attr "cpu" "ppce500mc"))
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109 "e500mc_decode,e500mc_bu,e500mc_retire")
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110
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111 ;; CR logical.
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112 (define_insn_reservation "e500mc_cr_logical" 1
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113 (and (eq_attr "type" "cr_logical,delayed_cr")
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114 (eq_attr "cpu" "ppce500mc"))
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115 "e500mc_decode,e500mc_bu,e500mc_retire")
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116
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117 ;; Mfcr.
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118 (define_insn_reservation "e500mc_mfcr" 1
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119 (and (eq_attr "type" "mfcr")
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120 (eq_attr "cpu" "ppce500mc"))
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121 "e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire")
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122
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123 ;; Mtcrf.
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124 (define_insn_reservation "e500mc_mtcrf" 1
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125 (and (eq_attr "type" "mtcr")
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126 (eq_attr "cpu" "ppce500mc"))
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127 "e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire")
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128
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129 ;; Mtjmpr.
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130 (define_insn_reservation "e500mc_mtjmpr" 1
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131 (and (eq_attr "type" "mtjmpr,mfjmpr")
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132 (eq_attr "cpu" "ppce500mc"))
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133 "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
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134
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135 ;; Loads.
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136 (define_insn_reservation "e500mc_load" 3
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137 (and (eq_attr "type" "load,load_l,sync")
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138 (eq_attr "cpu" "ppce500mc"))
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139 "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
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140
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141 (define_insn_reservation "e500mc_fpload" 4
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142 (and (eq_attr "type" "fpload")
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143 (eq_attr "cpu" "ppce500mc"))
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144 "e500mc_decode,e500mc_issue+e500mc_lsu,nothing*2,e500mc_retire")
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145
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146 ;; Stores.
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147 (define_insn_reservation "e500mc_store" 3
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148 (and (eq_attr "type" "store,store_c")
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149 (eq_attr "cpu" "ppce500mc"))
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150 "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
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151
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152 (define_insn_reservation "e500mc_fpstore" 3
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153 (and (eq_attr "type" "fpstore")
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154 (eq_attr "cpu" "ppce500mc"))
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155 "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
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156
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157 ;; The following ignores the retire unit to avoid a large automata.
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158
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159 ;; Simple FP.
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160 (define_insn_reservation "e500mc_simple_float" 8
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161 (and (eq_attr "type" "fpsimple")
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162 (eq_attr "cpu" "ppce500mc"))
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163 "e500mc_decode,e500mc_issue+e500mc_fpu")
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164 ; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire")
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165
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166 ;; FP.
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167 (define_insn_reservation "e500mc_float" 8
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168 (and (eq_attr "type" "fp")
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169 (eq_attr "cpu" "ppce500mc"))
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170 "e500mc_decode,e500mc_issue+e500mc_fpu")
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171 ; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire")
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172
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173 (define_insn_reservation "e500mc_fpcompare" 8
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174 (and (eq_attr "type" "fpcompare")
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175 (eq_attr "cpu" "ppce500mc"))
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176 "e500mc_decode,e500mc_issue+e500mc_fpu")
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177
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178 (define_insn_reservation "e500mc_dmul" 10
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179 (and (eq_attr "type" "dmul")
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180 (eq_attr "cpu" "ppce500mc"))
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181 "e500mc_decode,e500mc_issue+e500mc_fpu")
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182
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183 ;; FP divides are not pipelined.
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184 (define_insn_reservation "e500mc_sdiv" 36
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185 (and (eq_attr "type" "sdiv")
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186 (eq_attr "cpu" "ppce500mc"))
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187 "e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*35")
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188
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189 (define_insn_reservation "e500mc_ddiv" 66
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190 (and (eq_attr "type" "ddiv")
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191 (eq_attr "cpu" "ppce500mc"))
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192 "e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*65")
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