Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/arm/predicates.md @ 145:1830386684a0
gcc-9.2.0
| author | anatofuz |
|---|---|
| date | Thu, 13 Feb 2020 11:34:05 +0900 |
| parents | 84e7813d76e9 |
| children |
| rev | line source |
|---|---|
| 0 | 1 ;; Predicate definitions for ARM and Thumb |
| 145 | 2 ;; Copyright (C) 2004-2020 Free Software Foundation, Inc. |
| 0 | 3 ;; Contributed by ARM Ltd. |
| 4 | |
| 5 ;; This file is part of GCC. | |
| 6 | |
| 7 ;; GCC is free software; you can redistribute it and/or modify it | |
| 8 ;; under the terms of the GNU General Public License as published | |
| 9 ;; by the Free Software Foundation; either version 3, or (at your | |
| 10 ;; option) any later version. | |
| 11 | |
| 12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
| 13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 15 ;; License for more details. | |
| 16 | |
| 17 ;; You should have received a copy of the GNU General Public License | |
| 18 ;; along with GCC; see the file COPYING3. If not see | |
| 19 ;; <http://www.gnu.org/licenses/>. | |
| 20 | |
| 21 (define_predicate "s_register_operand" | |
| 22 (match_code "reg,subreg") | |
| 23 { | |
| 24 if (GET_CODE (op) == SUBREG) | |
| 25 op = SUBREG_REG (op); | |
| 26 /* We don't consider registers whose class is NO_REGS | |
| 27 to be a register operand. */ | |
| 28 /* XXX might have to check for lo regs only for thumb ??? */ | |
| 111 | 29 return (REG_P (op) |
| 0 | 30 && (REGNO (op) >= FIRST_PSEUDO_REGISTER |
| 31 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
| 32 }) | |
| 33 | |
| 145 | 34 ; Predicate for stack protector guard's address in |
| 35 ; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns | |
| 36 (define_predicate "guard_addr_operand" | |
| 37 (match_test "true") | |
| 38 { | |
| 39 return (CONSTANT_ADDRESS_P (op) | |
| 40 || !targetm.cannot_force_const_mem (mode, op)); | |
| 41 }) | |
| 42 | |
| 43 ; Predicate for stack protector guard in stack_protect_combined_set and | |
| 44 ; stack_protect_combined_test patterns | |
| 45 (define_predicate "guard_operand" | |
| 46 (match_code "mem") | |
| 47 { | |
| 48 return guard_addr_operand (XEXP (op, 0), mode); | |
| 49 }) | |
| 50 | |
| 111 | 51 (define_predicate "imm_for_neon_inv_logic_operand" |
| 52 (match_code "const_vector") | |
| 53 { | |
| 54 return (TARGET_NEON | |
| 55 && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); | |
| 56 }) | |
| 57 | |
| 58 (define_predicate "neon_inv_logic_op2" | |
| 59 (ior (match_operand 0 "imm_for_neon_inv_logic_operand") | |
| 60 (match_operand 0 "s_register_operand"))) | |
| 61 | |
| 62 (define_predicate "imm_for_neon_logic_operand" | |
| 63 (match_code "const_vector") | |
| 64 { | |
| 65 return (TARGET_NEON | |
| 66 && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); | |
| 67 }) | |
| 68 | |
| 69 (define_predicate "neon_logic_op2" | |
| 70 (ior (match_operand 0 "imm_for_neon_logic_operand") | |
| 71 (match_operand 0 "s_register_operand"))) | |
| 72 | |
| 73 ;; Any general register. | |
| 74 (define_predicate "arm_hard_general_register_operand" | |
| 0 | 75 (match_code "reg") |
| 76 { | |
| 111 | 77 return REGNO (op) <= LAST_ARM_REGNUM; |
| 0 | 78 }) |
| 79 | |
| 80 ;; A low register. | |
| 81 (define_predicate "low_register_operand" | |
| 82 (and (match_code "reg") | |
| 83 (match_test "REGNO (op) <= LAST_LO_REGNUM"))) | |
| 84 | |
| 85 ;; A low register or const_int. | |
| 86 (define_predicate "low_reg_or_int_operand" | |
| 87 (ior (match_code "const_int") | |
| 88 (match_operand 0 "low_register_operand"))) | |
| 89 | |
| 90 ;; Any core register, or any pseudo. */ | |
| 91 (define_predicate "arm_general_register_operand" | |
| 92 (match_code "reg,subreg") | |
| 93 { | |
| 94 if (GET_CODE (op) == SUBREG) | |
| 95 op = SUBREG_REG (op); | |
| 96 | |
| 111 | 97 return (REG_P (op) |
| 0 | 98 && (REGNO (op) <= LAST_ARM_REGNUM |
| 99 || REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
| 100 }) | |
| 101 | |
| 111 | 102 (define_predicate "arm_general_adddi_operand" |
| 103 (ior (match_operand 0 "arm_general_register_operand") | |
| 104 (and (match_code "const_int") | |
| 105 (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)")))) | |
| 0 | 106 |
|
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107 (define_predicate "vfp_register_operand" |
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108 (match_code "reg,subreg") |
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109 { |
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110 if (GET_CODE (op) == SUBREG) |
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111 op = SUBREG_REG (op); |
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112 |
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113 /* We don't consider registers whose class is NO_REGS |
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114 to be a register operand. */ |
| 111 | 115 return (REG_P (op) |
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116 && (REGNO (op) >= FIRST_PSEUDO_REGISTER |
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117 || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS |
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118 || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS |
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119 || (TARGET_VFPD32 |
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120 && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS))); |
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121 }) |
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122 |
| 111 | 123 (define_predicate "vfp_hard_register_operand" |
| 124 (match_code "reg") | |
| 125 { | |
| 126 return (IS_VFP_REGNUM (REGNO (op))); | |
| 127 }) | |
| 128 | |
| 129 (define_predicate "zero_operand" | |
| 130 (and (match_code "const_int,const_double,const_vector") | |
| 131 (match_test "op == CONST0_RTX (mode)"))) | |
| 132 | |
| 133 ;; Match a register, or zero in the appropriate mode. | |
| 134 (define_predicate "reg_or_zero_operand" | |
| 135 (ior (match_operand 0 "s_register_operand") | |
| 136 (match_operand 0 "zero_operand"))) | |
| 137 | |
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138 (define_special_predicate "subreg_lowpart_operator" |
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139 (and (match_code "subreg") |
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140 (match_test "subreg_lowpart_p (op)"))) |
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141 |
| 0 | 142 ;; Reg, subreg(reg) or const_int. |
| 143 (define_predicate "reg_or_int_operand" | |
| 144 (ior (match_code "const_int") | |
| 145 (match_operand 0 "s_register_operand"))) | |
| 146 | |
| 147 (define_predicate "arm_immediate_operand" | |
| 148 (and (match_code "const_int") | |
| 149 (match_test "const_ok_for_arm (INTVAL (op))"))) | |
| 150 | |
|
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151 ;; A constant value which fits into two instructions, each taking |
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152 ;; an arithmetic constant operand for one of the words. |
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153 (define_predicate "arm_immediate_di_operand" |
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154 (and (match_code "const_int,const_double") |
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155 (match_test "arm_const_double_by_immediates (op)"))) |
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156 |
| 0 | 157 (define_predicate "arm_neg_immediate_operand" |
| 158 (and (match_code "const_int") | |
| 159 (match_test "const_ok_for_arm (-INTVAL (op))"))) | |
| 160 | |
| 161 (define_predicate "arm_not_immediate_operand" | |
| 162 (and (match_code "const_int") | |
| 163 (match_test "const_ok_for_arm (~INTVAL (op))"))) | |
| 164 | |
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165 (define_predicate "const0_operand" |
| 111 | 166 (match_test "op == CONST0_RTX (mode)")) |
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167 |
| 0 | 168 ;; Something valid on the RHS of an ARM data-processing instruction |
| 169 (define_predicate "arm_rhs_operand" | |
| 170 (ior (match_operand 0 "s_register_operand") | |
| 171 (match_operand 0 "arm_immediate_operand"))) | |
| 172 | |
| 173 (define_predicate "arm_rhsm_operand" | |
| 174 (ior (match_operand 0 "arm_rhs_operand") | |
| 175 (match_operand 0 "memory_operand"))) | |
| 176 | |
| 111 | 177 (define_predicate "const_int_I_operand" |
| 178 (and (match_operand 0 "const_int_operand") | |
| 179 (match_test "satisfies_constraint_I (op)"))) | |
| 180 | |
| 181 (define_predicate "const_int_M_operand" | |
| 182 (and (match_operand 0 "const_int_operand") | |
| 183 (match_test "satisfies_constraint_M (op)"))) | |
| 184 | |
| 185 ;; This doesn't have to do much because the constant is already checked | |
| 186 ;; in the shift_operator predicate. | |
|
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187 (define_predicate "shift_amount_operand" |
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188 (ior (and (match_test "TARGET_ARM") |
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189 (match_operand 0 "s_register_operand")) |
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190 (match_operand 0 "const_int_operand"))) |
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191 |
| 111 | 192 (define_predicate "const_neon_scalar_shift_amount_operand" |
| 193 (and (match_code "const_int") | |
| 194 (match_test "IN_RANGE (UINTVAL (op), 1, GET_MODE_BITSIZE (mode))"))) | |
| 195 | |
| 145 | 196 (define_predicate "ssat16_imm" |
| 197 (and (match_code "const_int") | |
| 198 (match_test "IN_RANGE (INTVAL (op), 1, 16)"))) | |
| 199 | |
| 200 (define_predicate "usat16_imm" | |
| 201 (and (match_code "const_int") | |
| 202 (match_test "IN_RANGE (INTVAL (op), 0, 15)"))) | |
| 203 | |
| 111 | 204 (define_predicate "ldrd_strd_offset_operand" |
| 205 (and (match_operand 0 "const_int_operand") | |
| 206 (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (INTVAL (op))"))) | |
| 207 | |
| 0 | 208 (define_predicate "arm_add_operand" |
| 209 (ior (match_operand 0 "arm_rhs_operand") | |
| 210 (match_operand 0 "arm_neg_immediate_operand"))) | |
| 211 | |
| 145 | 212 (define_predicate "arm_adddi_operand" |
| 111 | 213 (ior (match_operand 0 "s_register_operand") |
| 214 (and (match_code "const_int") | |
| 145 | 215 (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)")))) |
| 111 | 216 |
| 145 | 217 (define_predicate "arm_anddi_operand" |
| 111 | 218 (ior (match_operand 0 "s_register_operand") |
| 219 (and (match_code "const_int") | |
| 145 | 220 (match_test "const_ok_for_dimode_op (INTVAL (op), AND)")))) |
| 221 | |
| 222 (define_predicate "arm_iordi_operand" | |
| 223 (ior (match_operand 0 "s_register_operand") | |
| 224 (and (match_code "const_int") | |
| 225 (match_test "const_ok_for_dimode_op (INTVAL (op), IOR)")))) | |
| 111 | 226 |
| 227 (define_predicate "arm_xordi_operand" | |
| 228 (ior (match_operand 0 "s_register_operand") | |
| 229 (and (match_code "const_int") | |
| 230 (match_test "const_ok_for_dimode_op (INTVAL (op), XOR)")))) | |
| 231 | |
| 0 | 232 (define_predicate "arm_addimm_operand" |
| 233 (ior (match_operand 0 "arm_immediate_operand") | |
| 234 (match_operand 0 "arm_neg_immediate_operand"))) | |
| 235 | |
| 236 (define_predicate "arm_not_operand" | |
| 237 (ior (match_operand 0 "arm_rhs_operand") | |
| 238 (match_operand 0 "arm_not_immediate_operand"))) | |
| 239 | |
| 145 | 240 ;; A constant that can be used with ADC(SBC) or SBC(ADC) when bit-wise |
| 241 ;; inverted. Similar to arm_not_operand, but excludes registers. | |
| 242 (define_predicate "arm_adcimm_operand" | |
| 243 (ior (match_operand 0 "arm_immediate_operand") | |
| 244 (match_operand 0 "arm_not_immediate_operand"))) | |
| 245 | |
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246 (define_predicate "arm_di_operand" |
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247 (ior (match_operand 0 "s_register_operand") |
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248 (match_operand 0 "arm_immediate_di_operand"))) |
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249 |
| 0 | 250 ;; True if the operand is a memory reference which contains an |
| 251 ;; offsettable address. | |
| 252 (define_predicate "offsettable_memory_operand" | |
| 253 (and (match_code "mem") | |
| 254 (match_test | |
| 255 "offsettable_address_p (reload_completed | reload_in_progress, | |
| 256 mode, XEXP (op, 0))"))) | |
| 257 | |
| 258 ;; True if the operand is a memory operand that does not have an | |
| 259 ;; automodified base register (and thus will not generate output reloads). | |
| 260 (define_predicate "call_memory_operand" | |
| 261 (and (match_code "mem") | |
| 262 (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) | |
| 263 != RTX_AUTOINC") | |
| 264 (match_operand 0 "memory_operand")))) | |
| 265 | |
| 266 (define_predicate "arm_reload_memory_operand" | |
| 267 (and (match_code "mem,reg,subreg") | |
| 268 (match_test "(!CONSTANT_P (op) | |
| 269 && (true_regnum(op) == -1 | |
| 111 | 270 || (REG_P (op) |
| 0 | 271 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))"))) |
| 272 | |
| 273 (define_predicate "vfp_compare_operand" | |
| 274 (ior (match_operand 0 "s_register_operand") | |
| 275 (and (match_code "const_double") | |
| 276 (match_test "arm_const_double_rtx (op)")))) | |
| 277 | |
| 278 ;; True for valid index operands. | |
| 279 (define_predicate "index_operand" | |
| 280 (ior (match_operand 0 "s_register_operand") | |
| 281 (and (match_operand 0 "immediate_operand") | |
| 111 | 282 (match_test "(!CONST_INT_P (op) |
| 0 | 283 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))")))) |
| 284 | |
| 285 ;; True for operators that can be combined with a shift in ARM state. | |
| 286 (define_special_predicate "shiftable_operator" | |
| 287 (and (match_code "plus,minus,ior,xor,and") | |
| 288 (match_test "mode == GET_MODE (op)"))) | |
| 289 | |
| 111 | 290 (define_special_predicate "shiftable_operator_strict_it" |
| 291 (and (match_code "plus,and") | |
| 292 (match_test "mode == GET_MODE (op)"))) | |
| 293 | |
| 0 | 294 ;; True for logical binary operators. |
| 295 (define_special_predicate "logical_binary_operator" | |
| 296 (and (match_code "ior,xor,and") | |
| 297 (match_test "mode == GET_MODE (op)"))) | |
| 298 | |
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299 ;; True for commutative operators |
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300 (define_special_predicate "commutative_binary_operator" |
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301 (and (match_code "ior,xor,and,plus") |
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302 (match_test "mode == GET_MODE (op)"))) |
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303 |
| 0 | 304 ;; True for shift operators. |
| 111 | 305 ;; Notes: |
| 306 ;; * mult is only permitted with a constant shift amount | |
| 307 ;; * patterns that permit register shift amounts only in ARM mode use | |
| 308 ;; shift_amount_operand, patterns that always allow registers do not, | |
| 309 ;; so we don't have to worry about that sort of thing here. | |
| 0 | 310 (define_special_predicate "shift_operator" |
| 311 (and (ior (ior (and (match_code "mult") | |
| 312 (match_test "power_of_two_operand (XEXP (op, 1), mode)")) | |
| 313 (and (match_code "rotate") | |
| 111 | 314 (match_test "CONST_INT_P (XEXP (op, 1)) |
| 315 && (UINTVAL (XEXP (op, 1))) < 32"))) | |
| 316 (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") | |
| 317 (match_test "!CONST_INT_P (XEXP (op, 1)) | |
| 318 || (UINTVAL (XEXP (op, 1))) < 32"))) | |
| 319 (match_test "mode == GET_MODE (op)"))) | |
| 320 | |
| 321 (define_special_predicate "shift_nomul_operator" | |
| 322 (and (ior (and (match_code "rotate") | |
| 323 (match_test "CONST_INT_P (XEXP (op, 1)) | |
| 324 && (UINTVAL (XEXP (op, 1))) < 32")) | |
| 325 (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") | |
| 326 (match_test "!CONST_INT_P (XEXP (op, 1)) | |
| 327 || (UINTVAL (XEXP (op, 1))) < 32"))) | |
| 328 (match_test "mode == GET_MODE (op)"))) | |
| 329 | |
| 330 ;; True for shift operators which can be used with saturation instructions. | |
| 331 (define_special_predicate "sat_shift_operator" | |
| 332 (and (ior (and (match_code "mult") | |
| 333 (match_test "power_of_two_operand (XEXP (op, 1), mode)")) | |
| 334 (and (match_code "ashift,ashiftrt") | |
| 335 (match_test "CONST_INT_P (XEXP (op, 1)) | |
| 336 && (UINTVAL (XEXP (op, 1)) < 32)"))) | |
| 0 | 337 (match_test "mode == GET_MODE (op)"))) |
| 338 | |
| 145 | 339 ;; True for Armv8.1-M Mainline long shift instructions. |
| 340 (define_predicate "long_shift_imm" | |
| 341 (match_test "satisfies_constraint_Pg (op)")) | |
| 342 | |
| 343 (define_predicate "arm_reg_or_long_shift_imm" | |
| 344 (ior (match_test "TARGET_THUMB2 | |
| 345 && arm_general_register_operand (op, GET_MODE (op))") | |
| 346 (match_test "satisfies_constraint_Pg (op)"))) | |
| 347 | |
|
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348 ;; True for MULT, to identify which variant of shift_operator is in use. |
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349 (define_special_predicate "mult_operator" |
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350 (match_code "mult")) |
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351 |
| 0 | 352 ;; True for operators that have 16-bit thumb variants. */ |
| 353 (define_special_predicate "thumb_16bit_operator" | |
| 354 (match_code "plus,minus,and,ior,xor")) | |
| 355 | |
| 356 ;; True for EQ & NE | |
| 357 (define_special_predicate "equality_operator" | |
| 358 (match_code "eq,ne")) | |
| 359 | |
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360 ;; True for integer comparisons and, if FP is active, for comparisons |
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361 ;; other than LTGT or UNEQ. |
| 111 | 362 (define_special_predicate "expandable_comparison_operator" |
| 363 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu, | |
| 364 unordered,ordered,unlt,unle,unge,ungt")) | |
| 365 | |
| 366 ;; Likewise, but only accept comparisons that are directly supported | |
| 367 ;; by ARM condition codes. | |
| 0 | 368 (define_special_predicate "arm_comparison_operator" |
| 111 | 369 (and (match_operand 0 "expandable_comparison_operator") |
| 370 (match_test "maybe_get_arm_condition_code (op) != ARM_NV"))) | |
| 371 | |
| 372 ;; Likewise, but don't ignore the mode. | |
| 373 ;; RTL SET operations require their operands source and destination have | |
| 374 ;; the same modes, so we can't ignore the modes there. See PR target/69161. | |
| 375 (define_predicate "arm_comparison_operator_mode" | |
| 376 (and (match_operand 0 "expandable_comparison_operator") | |
| 377 (match_test "maybe_get_arm_condition_code (op) != ARM_NV"))) | |
| 0 | 378 |
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379 (define_special_predicate "lt_ge_comparison_operator" |
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380 (match_code "lt,ge")) |
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381 |
| 145 | 382 (define_special_predicate "arm_carry_operation" |
| 383 (match_code "geu,ltu") | |
| 384 { | |
| 385 if (XEXP (op, 1) != const0_rtx) | |
| 386 return false; | |
| 387 | |
| 388 rtx op0 = XEXP (op, 0); | |
| 389 | |
| 390 if (!REG_P (op0) || REGNO (op0) != CC_REGNUM) | |
| 391 return false; | |
| 392 | |
| 393 machine_mode ccmode = GET_MODE (op0); | |
| 394 if (ccmode == CC_Cmode) | |
| 395 return GET_CODE (op) == LTU; | |
| 396 else if (ccmode == CCmode || ccmode == CC_RSBmode || ccmode == CC_ADCmode) | |
| 397 return GET_CODE (op) == GEU; | |
| 398 | |
| 399 return false; | |
| 400 } | |
| 401 ) | |
| 402 | |
| 403 ;; Match a "borrow" operation for use with SBC. The precise code will | |
| 404 ;; depend on the form of the comparison. This is generally the inverse of | |
| 405 ;; a carry operation, since the logic of SBC uses "not borrow" in it's | |
| 406 ;; calculation. | |
| 407 (define_special_predicate "arm_borrow_operation" | |
| 408 (match_code "geu,ltu") | |
| 409 { | |
| 410 if (XEXP (op, 1) != const0_rtx) | |
| 411 return false; | |
| 412 rtx op0 = XEXP (op, 0); | |
| 413 if (!REG_P (op0) || REGNO (op0) != CC_REGNUM) | |
| 414 return false; | |
| 415 machine_mode ccmode = GET_MODE (op0); | |
| 416 if (ccmode == CC_Cmode) | |
| 417 return GET_CODE (op) == GEU; | |
| 418 else if (ccmode == CCmode || ccmode == CC_RSBmode || ccmode == CC_ADCmode) | |
| 419 return GET_CODE (op) == LTU; | |
| 420 return false; | |
| 421 } | |
| 422 ) | |
| 423 | |
| 111 | 424 ;; The vsel instruction only accepts the ARM condition codes listed below. |
| 425 (define_special_predicate "arm_vsel_comparison_operator" | |
| 426 (and (match_operand 0 "expandable_comparison_operator") | |
| 427 (match_test "maybe_get_arm_condition_code (op) == ARM_GE | |
| 428 || maybe_get_arm_condition_code (op) == ARM_GT | |
| 429 || maybe_get_arm_condition_code (op) == ARM_EQ | |
| 430 || maybe_get_arm_condition_code (op) == ARM_VS | |
| 431 || maybe_get_arm_condition_code (op) == ARM_LT | |
| 432 || maybe_get_arm_condition_code (op) == ARM_LE | |
| 433 || maybe_get_arm_condition_code (op) == ARM_NE | |
| 434 || maybe_get_arm_condition_code (op) == ARM_VC"))) | |
| 435 | |
| 436 (define_special_predicate "arm_cond_move_operator" | |
| 437 (if_then_else (match_test "arm_restrict_it") | |
| 438 (and (match_test "TARGET_VFP5") | |
| 439 (match_operand 0 "arm_vsel_comparison_operator")) | |
| 440 (match_operand 0 "expandable_comparison_operator"))) | |
| 441 | |
| 145 | 442 (define_special_predicate "nz_comparison_operator" |
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443 (match_code "lt,ge,eq,ne")) |
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444 |
| 0 | 445 (define_special_predicate "minmax_operator" |
| 446 (and (match_code "smin,smax,umin,umax") | |
| 447 (match_test "mode == GET_MODE (op)"))) | |
| 448 | |
| 449 (define_special_predicate "cc_register" | |
| 450 (and (match_code "reg") | |
| 451 (and (match_test "REGNO (op) == CC_REGNUM") | |
| 452 (ior (match_test "mode == GET_MODE (op)") | |
| 453 (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))) | |
| 454 | |
| 455 (define_special_predicate "dominant_cc_register" | |
| 456 (match_code "reg") | |
| 457 { | |
| 458 if (mode == VOIDmode) | |
| 459 { | |
| 460 mode = GET_MODE (op); | |
| 461 | |
| 462 if (GET_MODE_CLASS (mode) != MODE_CC) | |
| 463 return false; | |
| 464 } | |
| 465 | |
| 466 return (cc_register (op, mode) | |
| 467 && (mode == CC_DNEmode | |
| 468 || mode == CC_DEQmode | |
| 469 || mode == CC_DLEmode | |
| 470 || mode == CC_DLTmode | |
| 471 || mode == CC_DGEmode | |
| 472 || mode == CC_DGTmode | |
| 473 || mode == CC_DLEUmode | |
| 474 || mode == CC_DLTUmode | |
| 475 || mode == CC_DGEUmode | |
| 476 || mode == CC_DGTUmode)); | |
| 477 }) | |
| 478 | |
| 111 | 479 ;; Any register, including CC |
| 480 (define_predicate "cc_register_operand" | |
| 481 (and (match_code "reg") | |
| 482 (ior (match_operand 0 "s_register_operand") | |
| 483 (match_operand 0 "cc_register")))) | |
| 484 | |
| 0 | 485 (define_special_predicate "arm_extendqisi_mem_op" |
| 486 (and (match_operand 0 "memory_operand") | |
| 111 | 487 (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode, |
| 488 XEXP (op, 0), | |
| 489 SIGN_EXTEND, | |
| 490 0) | |
| 491 : memory_address_p (QImode, XEXP (op, 0))"))) | |
| 0 | 492 |
| 493 (define_special_predicate "arm_reg_or_extendqisi_mem_op" | |
| 494 (ior (match_operand 0 "arm_extendqisi_mem_op") | |
| 495 (match_operand 0 "s_register_operand"))) | |
| 496 | |
| 497 (define_predicate "power_of_two_operand" | |
| 498 (match_code "const_int") | |
| 499 { | |
|
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500 unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff; |
| 0 | 501 |
| 502 return value != 0 && (value & (value - 1)) == 0; | |
| 503 }) | |
| 504 | |
| 505 (define_predicate "nonimmediate_di_operand" | |
| 506 (match_code "reg,subreg,mem") | |
| 507 { | |
| 508 if (s_register_operand (op, mode)) | |
| 509 return true; | |
| 510 | |
| 511 if (GET_CODE (op) == SUBREG) | |
| 512 op = SUBREG_REG (op); | |
| 513 | |
| 111 | 514 return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0)); |
| 0 | 515 }) |
| 516 | |
| 517 (define_predicate "di_operand" | |
| 518 (ior (match_code "const_int,const_double") | |
| 519 (and (match_code "reg,subreg,mem") | |
| 520 (match_operand 0 "nonimmediate_di_operand")))) | |
| 521 | |
| 522 (define_predicate "nonimmediate_soft_df_operand" | |
| 523 (match_code "reg,subreg,mem") | |
| 524 { | |
| 525 if (s_register_operand (op, mode)) | |
| 526 return true; | |
| 527 | |
| 528 if (GET_CODE (op) == SUBREG) | |
| 529 op = SUBREG_REG (op); | |
| 530 | |
| 111 | 531 return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0)); |
| 0 | 532 }) |
| 533 | |
| 534 (define_predicate "soft_df_operand" | |
| 535 (ior (match_code "const_double") | |
| 536 (and (match_code "reg,subreg,mem") | |
| 537 (match_operand 0 "nonimmediate_soft_df_operand")))) | |
| 538 | |
| 145 | 539 ;; Predicate for thumb2_movsf_vfp. Compared to general_operand, this |
| 540 ;; forbids constant loaded via literal pool iff literal pools are disabled. | |
| 541 (define_predicate "hard_sf_operand" | |
| 542 (and (match_operand 0 "general_operand") | |
| 543 (ior (not (match_code "const_double")) | |
| 544 (not (match_test "arm_disable_literal_pool")) | |
| 545 (match_test "satisfies_constraint_Dv (op)")))) | |
| 546 | |
| 547 ;; Predicate for thumb2_movdf_vfp. Compared to soft_df_operand used in | |
| 548 ;; movdf_soft_insn, this forbids constant loaded via literal pool iff | |
| 549 ;; literal pools are disabled. | |
| 550 (define_predicate "hard_df_operand" | |
| 551 (and (match_operand 0 "soft_df_operand") | |
| 552 (ior (not (match_code "const_double")) | |
| 553 (not (match_test "arm_disable_literal_pool")) | |
| 554 (match_test "satisfies_constraint_Dy (op)") | |
| 555 (match_test "satisfies_constraint_G (op)")))) | |
| 556 | |
| 557 (define_special_predicate "clear_multiple_operation" | |
| 558 (match_code "parallel") | |
| 559 { | |
| 560 return clear_operation_p (op, /*vfp*/false); | |
| 561 }) | |
| 562 | |
| 563 (define_special_predicate "clear_vfp_multiple_operation" | |
| 564 (match_code "parallel") | |
| 565 { | |
| 566 return clear_operation_p (op, /*vfp*/true); | |
| 567 }) | |
| 568 | |
| 0 | 569 (define_special_predicate "load_multiple_operation" |
| 570 (match_code "parallel") | |
| 571 { | |
| 111 | 572 return ldm_stm_operation_p (op, /*load=*/true, SImode, |
| 573 /*consecutive=*/false, | |
| 574 /*return_pc=*/false); | |
| 0 | 575 }) |
| 576 | |
| 577 (define_special_predicate "store_multiple_operation" | |
| 578 (match_code "parallel") | |
| 579 { | |
| 111 | 580 return ldm_stm_operation_p (op, /*load=*/false, SImode, |
| 581 /*consecutive=*/false, | |
| 582 /*return_pc=*/false); | |
| 583 }) | |
| 0 | 584 |
| 111 | 585 (define_special_predicate "pop_multiple_return" |
| 586 (match_code "parallel") | |
| 587 { | |
| 588 return ldm_stm_operation_p (op, /*load=*/true, SImode, | |
| 589 /*consecutive=*/false, | |
| 590 /*return_pc=*/true); | |
| 591 }) | |
| 0 | 592 |
| 111 | 593 (define_special_predicate "pop_multiple_fp" |
| 594 (match_code "parallel") | |
| 595 { | |
| 596 return ldm_stm_operation_p (op, /*load=*/true, DFmode, | |
| 597 /*consecutive=*/true, | |
| 598 /*return_pc=*/false); | |
| 0 | 599 }) |
| 600 | |
| 601 (define_special_predicate "multi_register_push" | |
| 602 (match_code "parallel") | |
| 603 { | |
| 604 if ((GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
| 605 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC) | |
| 606 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT)) | |
| 607 return false; | |
| 608 | |
| 609 return true; | |
| 610 }) | |
| 611 | |
| 111 | 612 (define_predicate "push_mult_memory_operand" |
| 613 (match_code "mem") | |
| 614 { | |
| 615 /* ??? Given how PUSH_MULT is generated in the prologues, is there | |
| 616 any point in testing for thumb1 specially? All of the variants | |
| 617 use the same form. */ | |
| 618 if (TARGET_THUMB1) | |
| 619 { | |
| 620 /* ??? No attempt is made to represent STMIA, or validate that | |
| 621 the stack adjustment matches the register count. This is | |
| 622 true of the ARM/Thumb2 path as well. */ | |
| 623 rtx x = XEXP (op, 0); | |
| 624 if (GET_CODE (x) != PRE_MODIFY) | |
| 625 return false; | |
| 626 if (XEXP (x, 0) != stack_pointer_rtx) | |
| 627 return false; | |
| 628 x = XEXP (x, 1); | |
| 629 if (GET_CODE (x) != PLUS) | |
| 630 return false; | |
| 631 if (XEXP (x, 0) != stack_pointer_rtx) | |
| 632 return false; | |
| 633 return CONST_INT_P (XEXP (x, 1)); | |
| 634 } | |
| 635 | |
| 636 /* ARM and Thumb2 handle pre-modify in their legitimate_address. */ | |
| 637 return memory_operand (op, mode); | |
| 638 }) | |
| 639 | |
| 0 | 640 ;;------------------------------------------------------------------------- |
| 641 ;; | |
| 642 ;; Thumb predicates | |
| 643 ;; | |
| 644 | |
| 645 (define_predicate "thumb1_cmp_operand" | |
| 646 (ior (and (match_code "reg,subreg") | |
| 647 (match_operand 0 "s_register_operand")) | |
| 648 (and (match_code "const_int") | |
| 111 | 649 (match_test "(UINTVAL (op)) < 256")))) |
| 0 | 650 |
| 651 (define_predicate "thumb1_cmpneg_operand" | |
| 652 (and (match_code "const_int") | |
| 653 (match_test "INTVAL (op) < 0 && INTVAL (op) > -256"))) | |
| 654 | |
| 655 ;; Return TRUE if a result can be stored in OP without clobbering the | |
| 656 ;; condition code register. Prior to reload we only accept a | |
| 657 ;; register. After reload we have to be able to handle memory as | |
| 658 ;; well, since a pseudo may not get a hard reg and reload cannot | |
| 659 ;; handle output-reloads on jump insns. | |
| 660 | |
| 661 ;; We could possibly handle mem before reload as well, but that might | |
| 662 ;; complicate things with the need to handle increment | |
| 663 ;; side-effects. | |
| 664 (define_predicate "thumb_cbrch_target_operand" | |
| 665 (and (match_code "reg,subreg,mem") | |
| 666 (ior (match_operand 0 "s_register_operand") | |
| 667 (and (match_test "reload_in_progress || reload_completed") | |
| 668 (match_operand 0 "memory_operand"))))) | |
| 669 | |
| 670 ;;------------------------------------------------------------------------- | |
| 671 ;; | |
| 111 | 672 ;; iWMMXt predicates |
| 0 | 673 ;; |
| 674 | |
| 111 | 675 (define_predicate "imm_or_reg_operand" |
| 676 (ior (match_operand 0 "immediate_operand") | |
| 677 (match_operand 0 "register_operand"))) | |
| 0 | 678 |
| 679 ;; Neon predicates | |
| 680 | |
| 681 (define_predicate "const_multiple_of_8_operand" | |
| 682 (match_code "const_int") | |
| 683 { | |
| 684 unsigned HOST_WIDE_INT val = INTVAL (op); | |
| 685 return (val & 7) == 0; | |
| 686 }) | |
| 687 | |
| 688 (define_predicate "imm_for_neon_mov_operand" | |
| 111 | 689 (match_code "const_vector,const_int") |
| 0 | 690 { |
| 691 return neon_immediate_valid_for_move (op, mode, NULL, NULL); | |
| 692 }) | |
| 693 | |
| 111 | 694 (define_predicate "imm_for_neon_lshift_operand" |
| 0 | 695 (match_code "const_vector") |
| 696 { | |
| 111 | 697 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true); |
| 0 | 698 }) |
| 699 | |
| 111 | 700 (define_predicate "imm_for_neon_rshift_operand" |
| 0 | 701 (match_code "const_vector") |
| 702 { | |
| 111 | 703 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false); |
| 0 | 704 }) |
| 705 | |
| 111 | 706 (define_predicate "imm_lshift_or_reg_neon" |
| 707 (ior (match_operand 0 "s_register_operand") | |
| 708 (match_operand 0 "imm_for_neon_lshift_operand"))) | |
| 0 | 709 |
| 111 | 710 (define_predicate "imm_rshift_or_reg_neon" |
| 711 (ior (match_operand 0 "s_register_operand") | |
| 712 (match_operand 0 "imm_for_neon_rshift_operand"))) | |
| 0 | 713 |
|
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714 ;; Predicates for named expanders that overlap multiple ISAs. |
| 0 | 715 |
|
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716 (define_predicate "cmpdi_operand" |
| 111 | 717 (and (match_test "TARGET_32BIT") |
| 718 (match_operand 0 "arm_di_operand"))) | |
|
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719 |
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720 ;; True if the operand is memory reference suitable for a ldrex/strex. |
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721 (define_predicate "arm_sync_memory_operand" |
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722 (and (match_operand 0 "memory_operand") |
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723 (match_code "reg" "0"))) |
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724 |
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725 ;; Predicates for parallel expanders based on mode. |
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726 (define_special_predicate "vect_par_constant_high" |
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727 (match_code "parallel") |
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728 { |
| 111 | 729 return arm_simd_check_vect_par_cnst_half_p (op, mode, true); |
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730 }) |
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731 |
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732 (define_special_predicate "vect_par_constant_low" |
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733 (match_code "parallel") |
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734 { |
| 111 | 735 return arm_simd_check_vect_par_cnst_half_p (op, mode, false); |
| 736 }) | |
| 737 | |
| 738 (define_predicate "const_double_vcvt_power_of_two_reciprocal" | |
| 739 (and (match_code "const_double") | |
| 740 (match_test "TARGET_32BIT | |
| 741 && vfp3_const_double_for_fract_bits (op)"))) | |
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742 |
| 111 | 743 (define_predicate "const_double_vcvt_power_of_two" |
| 744 (and (match_code "const_double") | |
| 745 (match_test "TARGET_32BIT | |
| 746 && vfp3_const_double_for_bits (op) > 0"))) | |
| 747 | |
| 748 (define_predicate "neon_struct_operand" | |
| 749 (and (match_code "mem") | |
| 750 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)"))) | |
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751 |
| 111 | 752 (define_predicate "neon_permissive_struct_operand" |
| 753 (and (match_code "mem") | |
| 754 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, false)"))) | |
| 755 | |
| 756 (define_predicate "neon_perm_struct_or_reg_operand" | |
| 757 (ior (match_operand 0 "neon_permissive_struct_operand") | |
| 758 (match_operand 0 "s_register_operand"))) | |
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759 |
| 111 | 760 (define_special_predicate "add_operator" |
| 761 (match_code "plus")) | |
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762 |
| 111 | 763 (define_predicate "mem_noofs_operand" |
| 764 (and (match_code "mem") | |
| 765 (match_code "reg" "0"))) | |
| 766 | |
| 767 (define_predicate "call_insn_operand" | |
| 768 (ior (and (match_code "symbol_ref") | |
| 769 (match_test "!arm_is_long_call_p (SYMBOL_REF_DECL (op))")) | |
| 770 (match_operand 0 "s_register_operand"))) | |
| 145 | 771 |
| 772 (define_special_predicate "aligned_operand" | |
| 773 (ior (not (match_code "mem")) | |
| 774 (match_test "MEM_ALIGN (op) >= GET_MODE_ALIGNMENT (mode)"))) |