Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/sh/sh.opt @ 145:1830386684a0
gcc-9.2.0
| author | anatofuz |
|---|---|
| date | Thu, 13 Feb 2020 11:34:05 +0900 |
| parents | 84e7813d76e9 |
| children |
| rev | line source |
|---|---|
| 0 | 1 ; Options for the SH port of the compiler. |
| 2 | |
| 145 | 3 ; Copyright (C) 2005-2020 Free Software Foundation, Inc. |
| 0 | 4 ; |
| 5 ; This file is part of GCC. | |
| 6 ; | |
| 7 ; GCC is free software; you can redistribute it and/or modify it under | |
| 8 ; the terms of the GNU General Public License as published by the Free | |
| 9 ; Software Foundation; either version 3, or (at your option) any later | |
| 10 ; version. | |
| 11 ; | |
| 12 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
| 13 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 14 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 15 ; for more details. | |
| 16 ; | |
| 17 ; You should have received a copy of the GNU General Public License | |
| 18 ; along with GCC; see the file COPYING3. If not see | |
| 19 ; <http://www.gnu.org/licenses/>. | |
| 20 | |
| 21 ;; Used for various architecture options. | |
| 22 Mask(SH_E) | |
| 23 | |
| 111 | 24 ;; Set if the default precision of the FPU is single. |
| 0 | 25 Mask(FPU_SINGLE) |
| 26 | |
| 111 | 27 ;; Set if the a double-precision FPU is present but is restricted to |
| 28 ;; single precision usage only. | |
| 29 Mask(FPU_SINGLE_ONLY) | |
| 30 | |
| 0 | 31 ;; Set if we should generate code using type 2A insns. |
| 32 Mask(HARD_SH2A) | |
| 33 | |
| 34 ;; Set if we should generate code using type 2A DF insns. | |
| 35 Mask(HARD_SH2A_DOUBLE) | |
| 36 | |
| 37 ;; Set if compiling for SH4 hardware (to be used for insn costs etc.) | |
| 38 Mask(HARD_SH4) | |
| 39 | |
| 40 m1 | |
| 41 Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1) | |
| 111 | 42 Generate SH1 code. |
| 0 | 43 |
| 44 m2 | |
| 45 Target RejectNegative Mask(SH2) Condition(SUPPORT_SH2) | |
| 111 | 46 Generate SH2 code. |
| 0 | 47 |
| 48 m2a | |
| 49 Target RejectNegative Condition(SUPPORT_SH2A) | |
| 111 | 50 Generate default double-precision SH2a-FPU code. |
| 0 | 51 |
| 52 m2a-nofpu | |
| 53 Target RejectNegative Condition(SUPPORT_SH2A_NOFPU) | |
| 111 | 54 Generate SH2a FPU-less code. |
| 0 | 55 |
| 56 m2a-single | |
| 57 Target RejectNegative Condition(SUPPORT_SH2A_SINGLE) | |
| 111 | 58 Generate default single-precision SH2a-FPU code. |
| 0 | 59 |
| 60 m2a-single-only | |
| 61 Target RejectNegative Condition(SUPPORT_SH2A_SINGLE_ONLY) | |
| 111 | 62 Generate only single-precision SH2a-FPU code. |
| 0 | 63 |
| 64 m2e | |
| 65 Target RejectNegative Condition(SUPPORT_SH2E) | |
| 111 | 66 Generate SH2e code. |
| 0 | 67 |
| 68 m3 | |
| 69 Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) | |
| 111 | 70 Generate SH3 code. |
| 0 | 71 |
| 72 m3e | |
| 73 Target RejectNegative Condition(SUPPORT_SH3E) | |
| 111 | 74 Generate SH3e code. |
| 0 | 75 |
| 76 m4 | |
| 77 Target RejectNegative Mask(SH4) Condition(SUPPORT_SH4) | |
| 111 | 78 Generate SH4 code. |
| 0 | 79 |
| 80 m4-100 | |
| 81 Target RejectNegative Condition(SUPPORT_SH4) | |
| 111 | 82 Generate SH4-100 code. |
| 0 | 83 |
| 84 m4-200 | |
| 85 Target RejectNegative Condition(SUPPORT_SH4) | |
| 111 | 86 Generate SH4-200 code. |
| 0 | 87 |
| 88 ;; TARGET_SH4_300 indicates if we have the ST40-300 instruction set and | |
| 89 ;; pipeline - irrespective of ABI. | |
| 90 m4-300 | |
| 91 Target RejectNegative Condition(SUPPORT_SH4) Var(TARGET_SH4_300) | |
| 111 | 92 Generate SH4-300 code. |
| 0 | 93 |
| 94 m4-nofpu | |
| 95 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) | |
| 111 | 96 Generate SH4 FPU-less code. |
| 0 | 97 |
| 98 m4-100-nofpu | |
| 99 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) | |
| 111 | 100 Generate SH4-100 FPU-less code. |
| 0 | 101 |
| 102 m4-200-nofpu | |
| 103 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) | |
| 111 | 104 Generate SH4-200 FPU-less code. |
| 0 | 105 |
| 106 m4-300-nofpu | |
|
67
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
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107 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) |
| 111 | 108 Generate SH4-300 FPU-less code. |
| 0 | 109 |
| 110 m4-340 | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
111 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) |
| 111 | 112 Generate code for SH4 340 series (MMU/FPU-less). |
| 0 | 113 ;; passes -isa=sh4-nommu-nofpu to the assembler. |
| 114 | |
| 115 m4-400 | |
| 116 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) | |
| 111 | 117 Generate code for SH4 400 series (MMU/FPU-less). |
| 0 | 118 ;; passes -isa=sh4-nommu-nofpu to the assembler. |
| 119 | |
| 120 m4-500 | |
| 121 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) | |
| 122 Generate code for SH4 500 series (FPU-less). | |
| 123 ;; passes -isa=sh4-nofpu to the assembler. | |
| 124 | |
| 125 m4-single | |
| 126 Target RejectNegative Condition(SUPPORT_SH4_SINGLE) | |
| 111 | 127 Generate default single-precision SH4 code. |
| 0 | 128 |
| 129 m4-100-single | |
| 130 Target RejectNegative Condition(SUPPORT_SH4_SINGLE) | |
| 111 | 131 Generate default single-precision SH4-100 code. |
| 0 | 132 |
| 133 m4-200-single | |
| 134 Target RejectNegative Condition(SUPPORT_SH4_SINGLE) | |
| 111 | 135 Generate default single-precision SH4-200 code. |
| 0 | 136 |
| 137 m4-300-single | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
138 Target RejectNegative Condition(SUPPORT_SH4_SINGLE) Var(TARGET_SH4_300) |
| 111 | 139 Generate default single-precision SH4-300 code. |
| 0 | 140 |
| 141 m4-single-only | |
| 142 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) | |
| 111 | 143 Generate only single-precision SH4 code. |
| 0 | 144 |
| 145 m4-100-single-only | |
| 146 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) | |
| 111 | 147 Generate only single-precision SH4-100 code. |
| 0 | 148 |
| 149 m4-200-single-only | |
| 150 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) | |
| 111 | 151 Generate only single-precision SH4-200 code. |
| 0 | 152 |
| 153 m4-300-single-only | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
154 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Var(TARGET_SH4_300) |
| 111 | 155 Generate only single-precision SH4-300 code. |
| 0 | 156 |
| 157 m4a | |
| 158 Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A) | |
| 111 | 159 Generate SH4a code. |
| 0 | 160 |
| 161 m4a-nofpu | |
| 162 Target RejectNegative Condition(SUPPORT_SH4A_NOFPU) | |
| 111 | 163 Generate SH4a FPU-less code. |
| 0 | 164 |
| 165 m4a-single | |
| 166 Target RejectNegative Condition(SUPPORT_SH4A_SINGLE) | |
| 111 | 167 Generate default single-precision SH4a code. |
| 0 | 168 |
| 169 m4a-single-only | |
| 170 Target RejectNegative Condition(SUPPORT_SH4A_SINGLE_ONLY) | |
| 111 | 171 Generate only single-precision SH4a code. |
| 0 | 172 |
| 173 m4al | |
| 174 Target RejectNegative Condition(SUPPORT_SH4AL) | |
| 111 | 175 Generate SH4al-dsp code. |
| 0 | 176 |
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parents:
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177 maccumulate-outgoing-args |
| 111 | 178 Target Report Var(TARGET_ACCUMULATE_OUTGOING_ARGS) Init(1) |
| 179 Reserve space for outgoing arguments in the function prologue. | |
| 0 | 180 |
| 181 mb | |
| 182 Target Report RejectNegative InverseMask(LITTLE_ENDIAN) | |
| 111 | 183 Generate code in big endian mode. |
| 0 | 184 |
| 185 mbigtable | |
| 186 Target Report RejectNegative Mask(BIGTABLE) | |
| 111 | 187 Generate 32-bit offsets in switch tables. |
| 0 | 188 |
| 189 mbitops | |
| 190 Target Report RejectNegative Mask(BITOPS) | |
| 111 | 191 Generate bit instructions. |
| 0 | 192 |
| 193 mbranch-cost= | |
| 194 Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1) | |
| 111 | 195 Cost to assume for a branch insn. |
| 0 | 196 |
| 111 | 197 mzdcbranch |
| 198 Target Report Var(TARGET_ZDCBRANCH) | |
| 199 Assume that zero displacement conditional branches are fast. | |
| 0 | 200 |
| 111 | 201 mcbranch-force-delay-slot |
| 202 Target Report RejectNegative Var(TARGET_CBRANCH_FORCE_DELAY_SLOT) Init(0) | |
| 203 Force the usage of delay slots for conditional branches. | |
| 0 | 204 |
| 205 mdalign | |
| 206 Target Report RejectNegative Mask(ALIGN_DOUBLE) | |
| 111 | 207 Align doubles at 64-bit boundaries. |
| 0 | 208 |
| 209 mdiv= | |
| 210 Target RejectNegative Joined Var(sh_div_str) Init("") | |
| 111 | 211 Division strategy, one of: call-div1, call-fp, call-table. |
| 0 | 212 |
| 213 mdivsi3_libfunc= | |
| 214 Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("") | |
| 111 | 215 Specify name for 32 bit signed division function. |
| 216 | |
| 217 mfdpic | |
| 218 Target Report Var(TARGET_FDPIC) Init(0) | |
| 219 Generate ELF FDPIC code. | |
| 0 | 220 |
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221 mfmovd |
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222 Target RejectNegative Mask(FMOVD) |
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223 Enable the use of 64-bit floating point registers in fmov instructions. See -mdalign if 64-bit alignment is required. |
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224 |
| 0 | 225 mfixed-range= |
| 226 Target RejectNegative Joined Var(sh_fixed_range_str) | |
| 111 | 227 Specify range of registers to make fixed. |
| 0 | 228 |
| 229 mhitachi | |
| 230 Target Report RejectNegative Mask(HITACHI) | |
| 111 | 231 Follow Renesas (formerly Hitachi) / SuperH calling conventions. |
| 0 | 232 |
| 233 mieee | |
| 111 | 234 Target Var(TARGET_IEEE) |
| 235 Increase the IEEE compliance for floating-point comparisons. | |
| 0 | 236 |
| 237 minline-ic_invalidate | |
| 238 Target Report Var(TARGET_INLINE_IC_INVALIDATE) | |
| 145 | 239 Inline code to invalidate instruction cache entries after setting up nested function trampolines. |
| 0 | 240 |
| 241 misize | |
| 242 Target Report RejectNegative Mask(DUMPISIZE) | |
| 111 | 243 Annotate assembler instructions with estimated addresses. |
| 0 | 244 |
| 245 ml | |
| 246 Target Report RejectNegative Mask(LITTLE_ENDIAN) | |
| 111 | 247 Generate code in little endian mode. |
| 0 | 248 |
| 249 mnomacsave | |
| 250 Target Report RejectNegative Mask(NOMACSAVE) | |
| 111 | 251 Mark MAC register as call-clobbered. |
| 0 | 252 |
| 253 ;; ??? This option is not useful, but is retained in case there are people | |
| 254 ;; who are still relying on it. It may be deleted in the future. | |
| 255 mpadstruct | |
| 256 Target Report RejectNegative Mask(PADSTRUCT) | |
| 111 | 257 Make structs a multiple of 4 bytes (warning: ABI altered). |
| 0 | 258 |
| 259 mprefergot | |
| 260 Target Report RejectNegative Mask(PREFERGOT) | |
| 111 | 261 Emit function-calls using global offset table when generating PIC. |
| 0 | 262 |
| 263 mrelax | |
| 264 Target Report RejectNegative Mask(RELAX) | |
| 111 | 265 Shorten address references during linking. |
| 0 | 266 |
| 267 mrenesas | |
| 111 | 268 Target Mask(HITACHI) |
| 269 Follow Renesas (formerly Hitachi) / SuperH calling conventions. | |
| 0 | 270 |
| 111 | 271 matomic-model= |
| 272 Target Report RejectNegative Joined Var(sh_atomic_model_str) | |
| 273 Specify the model for atomic operations. | |
| 274 | |
| 275 mtas | |
| 276 Target Report RejectNegative Var(TARGET_ENABLE_TAS) | |
| 277 Use tas.b instruction for __atomic_test_and_set. | |
| 0 | 278 |
| 279 multcost= | |
| 280 Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1) | |
| 111 | 281 Cost to assume for a multiply insn. |
| 0 | 282 |
| 283 musermode | |
| 111 | 284 Target Var(TARGET_USERMODE) |
| 0 | 285 Don't generate privileged-mode only code; implies -mno-inline-ic_invalidate if the inline code would not work in user mode. |
| 286 | |
| 287 ;; We might want to enable this by default for TARGET_HARD_SH4, because | |
| 288 ;; zero-offset branches have zero latency. Needs some benchmarking. | |
| 289 mpretend-cmove | |
| 290 Target Var(TARGET_PRETEND_CMOVE) | |
| 291 Pretend a branch-around-a-move is a conditional move. | |
| 111 | 292 |
| 293 mfsca | |
| 294 Target Var(TARGET_FSCA) | |
| 295 Enable the use of the fsca instruction. | |
| 296 | |
| 297 mfsrra | |
| 298 Target Var(TARGET_FSRRA) | |
| 299 Enable the use of the fsrra instruction. | |
| 300 | |
| 301 mlra | |
| 302 Target Report Var(sh_lra_flag) Init(0) Save | |
| 303 Use LRA instead of reload (transitional). |