Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/avr/avr.md @ 55:77e2b8dfacca gcc-4.4.5
update it from 4.4.3 to 4.5.0
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Fri, 12 Feb 2010 23:39:51 +0900 |
| parents | a06113de4d67 |
| children | b7f97abdc517 |
| rev | line source |
|---|---|
| 0 | 1 ;; -*- Mode: Scheme -*- |
| 2 ;; Machine description for GNU compiler, | |
| 3 ;; for ATMEL AVR micro controllers. | |
| 4 ;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2007, 2008, | |
| 5 ;; 2009 Free Software Foundation, Inc. | |
|
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6 ;; Contributed by Denis Chertykov (chertykov@gmail.com) |
| 0 | 7 |
| 8 ;; This file is part of GCC. | |
| 9 | |
| 10 ;; GCC is free software; you can redistribute it and/or modify | |
| 11 ;; it under the terms of the GNU General Public License as published by | |
| 12 ;; the Free Software Foundation; either version 3, or (at your option) | |
| 13 ;; any later version. | |
| 14 | |
| 15 ;; GCC is distributed in the hope that it will be useful, | |
| 16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 18 ;; GNU General Public License for more details. | |
| 19 | |
| 20 ;; You should have received a copy of the GNU General Public License | |
| 21 ;; along with GCC; see the file COPYING3. If not see | |
| 22 ;; <http://www.gnu.org/licenses/>. | |
| 23 | |
| 24 ;; Special characters after '%': | |
| 25 ;; A No effect (add 0). | |
| 26 ;; B Add 1 to REG number, MEM address or CONST_INT. | |
| 27 ;; C Add 2. | |
| 28 ;; D Add 3. | |
| 29 ;; j Branch condition. | |
| 30 ;; k Reverse branch condition. | |
|
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31 ;;..m..Constant Direct Data memory address. |
| 0 | 32 ;; o Displacement for (mem (plus (reg) (const_int))) operands. |
| 33 ;; p POST_INC or PRE_DEC address as a pointer (X, Y, Z) | |
| 34 ;; r POST_INC or PRE_DEC address as a register (r26, r28, r30) | |
|
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35 ;;..x..Constant Direct Program memory address. |
| 0 | 36 ;; ~ Output 'r' if not AVR_HAVE_JMP_CALL. |
| 37 ;; ! Output 'e' if AVR_HAVE_EIJMP_EICALL. | |
| 38 | |
| 39 ;; UNSPEC usage: | |
| 40 ;; 0 Length of a string, see "strlenhi". | |
| 41 ;; 1 Jump by register pair Z or by table addressed by Z, see "casesi". | |
| 42 | |
| 43 (define_constants | |
| 44 [(REG_X 26) | |
| 45 (REG_Y 28) | |
| 46 (REG_Z 30) | |
| 47 (REG_W 24) | |
| 48 (REG_SP 32) | |
| 49 (TMP_REGNO 0) ; temporary register r0 | |
| 50 (ZERO_REGNO 1) ; zero register r1 | |
| 51 | |
| 52 (SREG_ADDR 0x5F) | |
| 53 (RAMPZ_ADDR 0x5B) | |
| 54 | |
| 55 (UNSPEC_STRLEN 0) | |
| 56 (UNSPEC_INDEX_JMP 1) | |
| 57 (UNSPEC_SEI 2) | |
| 58 (UNSPEC_CLI 3) | |
| 59 | |
| 60 (UNSPECV_PROLOGUE_SAVES 0) | |
| 61 (UNSPECV_EPILOGUE_RESTORES 1) | |
| 62 (UNSPECV_WRITE_SP_IRQ_ON 2) | |
| 63 (UNSPECV_WRITE_SP_IRQ_OFF 3) | |
| 64 (UNSPECV_GOTO_RECEIVER 4)]) | |
| 65 | |
| 66 (include "predicates.md") | |
| 67 (include "constraints.md") | |
| 68 | |
| 69 ;; Condition code settings. | |
| 70 (define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber" | |
| 71 (const_string "none")) | |
| 72 | |
| 73 (define_attr "type" "branch,branch1,arith,xcall" | |
| 74 (const_string "arith")) | |
| 75 | |
| 76 (define_attr "mcu_have_movw" "yes,no" | |
| 77 (const (if_then_else (symbol_ref "AVR_HAVE_MOVW") | |
| 78 (const_string "yes") | |
| 79 (const_string "no")))) | |
| 80 | |
| 81 (define_attr "mcu_mega" "yes,no" | |
| 82 (const (if_then_else (symbol_ref "AVR_HAVE_JMP_CALL") | |
| 83 (const_string "yes") | |
| 84 (const_string "no")))) | |
| 85 | |
| 86 | |
| 87 ;; The size of instructions in bytes. | |
| 88 ;; XXX may depend from "cc" | |
| 89 | |
| 90 (define_attr "length" "" | |
| 91 (cond [(eq_attr "type" "branch") | |
| 92 (if_then_else (and (ge (minus (pc) (match_dup 0)) | |
| 93 (const_int -63)) | |
| 94 (le (minus (pc) (match_dup 0)) | |
| 95 (const_int 62))) | |
| 96 (const_int 1) | |
| 97 (if_then_else (and (ge (minus (pc) (match_dup 0)) | |
| 98 (const_int -2045)) | |
| 99 (le (minus (pc) (match_dup 0)) | |
| 100 (const_int 2045))) | |
| 101 (const_int 2) | |
| 102 (const_int 3))) | |
| 103 (eq_attr "type" "branch1") | |
| 104 (if_then_else (and (ge (minus (pc) (match_dup 0)) | |
| 105 (const_int -62)) | |
| 106 (le (minus (pc) (match_dup 0)) | |
| 107 (const_int 61))) | |
| 108 (const_int 2) | |
| 109 (if_then_else (and (ge (minus (pc) (match_dup 0)) | |
| 110 (const_int -2044)) | |
| 111 (le (minus (pc) (match_dup 0)) | |
| 112 (const_int 2043))) | |
| 113 (const_int 3) | |
| 114 (const_int 4))) | |
| 115 (eq_attr "type" "xcall") | |
| 116 (if_then_else (eq_attr "mcu_mega" "no") | |
| 117 (const_int 1) | |
| 118 (const_int 2))] | |
| 119 (const_int 2))) | |
| 120 | |
| 121 ;; Define mode iterator | |
| 122 (define_mode_iterator QISI [(QI "") (HI "") (SI "")]) | |
|
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123 (define_mode_iterator QIDI [(QI "") (HI "") (SI "") (DI "")]) |
| 0 | 124 |
| 125 ;;======================================================================== | |
| 126 ;; The following is used by nonlocal_goto and setjmp. | |
| 127 ;; The receiver pattern will create no instructions since internally | |
| 128 ;; virtual_stack_vars = hard_frame_pointer + 1 so the RTL become R28=R28 | |
| 129 ;; This avoids creating add/sub offsets in frame_pointer save/resore. | |
| 130 ;; The 'null' receiver also avoids problems with optimisation | |
| 131 ;; not recognising incoming jmp and removing code that resets frame_pointer. | |
| 132 ;; The code derived from builtins.c. | |
| 133 | |
| 134 (define_expand "nonlocal_goto_receiver" | |
| 135 [(set (reg:HI REG_Y) | |
| 136 (unspec_volatile:HI [(const_int 0)] UNSPECV_GOTO_RECEIVER))] | |
| 137 "" | |
| 138 { | |
| 139 emit_move_insn (virtual_stack_vars_rtx, | |
| 140 gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, | |
| 141 gen_int_mode (STARTING_FRAME_OFFSET, | |
| 142 Pmode))); | |
| 143 /* This might change the hard frame pointer in ways that aren't | |
| 144 apparent to early optimization passes, so force a clobber. */ | |
| 145 emit_clobber (hard_frame_pointer_rtx); | |
| 146 DONE; | |
| 147 }) | |
| 148 | |
| 149 | |
| 150 ;; Defining nonlocal_goto_receiver means we must also define this. | |
| 151 ;; even though its function is identical to that in builtins.c | |
| 152 | |
| 153 (define_expand "nonlocal_goto" | |
| 154 [ | |
| 155 (use (match_operand 0 "general_operand")) | |
| 156 (use (match_operand 1 "general_operand")) | |
| 157 (use (match_operand 2 "general_operand")) | |
| 158 (use (match_operand 3 "general_operand")) | |
| 159 ] | |
| 160 "" | |
| 161 { | |
| 162 rtx r_label = copy_to_reg (operands[1]); | |
| 163 rtx r_fp = operands[3]; | |
| 164 rtx r_sp = operands[2]; | |
| 165 | |
| 166 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode))); | |
| 167 | |
| 168 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx)); | |
| 169 | |
| 170 emit_move_insn (hard_frame_pointer_rtx, r_fp); | |
| 171 emit_stack_restore (SAVE_NONLOCAL, r_sp, NULL_RTX); | |
| 172 | |
| 173 emit_use (hard_frame_pointer_rtx); | |
| 174 emit_use (stack_pointer_rtx); | |
| 175 | |
| 176 emit_indirect_jump (r_label); | |
| 177 | |
| 178 DONE; | |
| 179 }) | |
| 180 | |
| 181 | |
| 182 (define_insn "*pushqi" | |
| 183 [(set (mem:QI (post_dec (reg:HI REG_SP))) | |
| 184 (match_operand:QI 0 "reg_or_0_operand" "r,L"))] | |
| 185 "" | |
| 186 "@ | |
| 187 push %0 | |
| 188 push __zero_reg__" | |
| 189 [(set_attr "length" "1,1")]) | |
| 190 | |
| 191 | |
| 192 (define_insn "*pushhi" | |
| 193 [(set (mem:HI (post_dec (reg:HI REG_SP))) | |
| 194 (match_operand:HI 0 "reg_or_0_operand" "r,L"))] | |
| 195 "" | |
| 196 "@ | |
| 197 push %B0\;push %A0 | |
| 198 push __zero_reg__\;push __zero_reg__" | |
| 199 [(set_attr "length" "2,2")]) | |
| 200 | |
| 201 (define_insn "*pushsi" | |
| 202 [(set (mem:SI (post_dec (reg:HI REG_SP))) | |
| 203 (match_operand:SI 0 "reg_or_0_operand" "r,L"))] | |
| 204 "" | |
| 205 "@ | |
| 206 push %D0\;push %C0\;push %B0\;push %A0 | |
| 207 push __zero_reg__\;push __zero_reg__\;push __zero_reg__\;push __zero_reg__" | |
| 208 [(set_attr "length" "4,4")]) | |
| 209 | |
| 210 (define_insn "*pushsf" | |
| 211 [(set (mem:SF (post_dec (reg:HI REG_SP))) | |
| 212 (match_operand:SF 0 "register_operand" "r"))] | |
| 213 "" | |
| 214 "push %D0 | |
| 215 push %C0 | |
| 216 push %B0 | |
| 217 push %A0" | |
| 218 [(set_attr "length" "4")]) | |
| 219 | |
| 220 ;;======================================================================== | |
| 221 ;; move byte | |
| 222 ;; The last alternative (any immediate constant to any register) is | |
| 223 ;; very expensive. It should be optimized by peephole2 if a scratch | |
| 224 ;; register is available, but then that register could just as well be | |
| 225 ;; allocated for the variable we are loading. But, most of NO_LD_REGS | |
| 226 ;; are call-saved registers, and most of LD_REGS are call-used registers, | |
| 227 ;; so this may still be a win for registers live across function calls. | |
| 228 | |
| 229 (define_expand "movqi" | |
| 230 [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
| 231 (match_operand:QI 1 "general_operand" ""))] | |
| 232 "" | |
| 233 "/* One of the ops has to be in a register. */ | |
| 234 if (!register_operand(operand0, QImode) | |
| 235 && ! (register_operand(operand1, QImode) || const0_rtx == operand1)) | |
| 236 operands[1] = copy_to_mode_reg(QImode, operand1); | |
| 237 ") | |
| 238 | |
| 239 (define_insn "*movqi" | |
| 240 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,d,Qm,r,q,r,*r") | |
|
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
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241 (match_operand:QI 1 "general_operand" "rL,i,rL,Qm,r,q,i"))] |
| 0 | 242 "(register_operand (operands[0],QImode) |
| 243 || register_operand (operands[1], QImode) || const0_rtx == operands[1])" | |
| 244 "* return output_movqi (insn, operands, NULL);" | |
| 245 [(set_attr "length" "1,1,5,5,1,1,4") | |
| 246 (set_attr "cc" "none,none,clobber,clobber,none,none,clobber")]) | |
| 247 | |
| 248 ;; This is used in peephole2 to optimize loading immediate constants | |
| 249 ;; if a scratch register from LD_REGS happens to be available. | |
| 250 | |
| 251 (define_insn "*reload_inqi" | |
| 252 [(set (match_operand:QI 0 "register_operand" "=l") | |
| 253 (match_operand:QI 1 "immediate_operand" "i")) | |
| 254 (clobber (match_operand:QI 2 "register_operand" "=&d"))] | |
| 255 "reload_completed" | |
| 256 "ldi %2,lo8(%1) | |
| 257 mov %0,%2" | |
| 258 [(set_attr "length" "2") | |
| 259 (set_attr "cc" "none")]) | |
| 260 | |
| 261 (define_peephole2 | |
| 262 [(match_scratch:QI 2 "d") | |
| 263 (set (match_operand:QI 0 "l_register_operand" "") | |
| 264 (match_operand:QI 1 "immediate_operand" ""))] | |
| 265 "(operands[1] != const0_rtx | |
| 266 && operands[1] != const1_rtx | |
| 267 && operands[1] != constm1_rtx)" | |
| 268 [(parallel [(set (match_dup 0) (match_dup 1)) | |
| 269 (clobber (match_dup 2))])] | |
| 270 "") | |
| 271 | |
| 272 ;;============================================================================ | |
| 273 ;; move word (16 bit) | |
| 274 | |
| 275 (define_expand "movhi" | |
| 276 [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
| 277 (match_operand:HI 1 "general_operand" ""))] | |
| 278 "" | |
| 279 " | |
| 280 { | |
| 281 /* One of the ops has to be in a register. */ | |
| 282 if (!register_operand(operand0, HImode) | |
| 283 && !(register_operand(operand1, HImode) || const0_rtx == operands[1])) | |
| 284 { | |
| 285 operands[1] = copy_to_mode_reg(HImode, operand1); | |
| 286 } | |
| 287 }") | |
| 288 | |
| 289 (define_insn "*movhi_sp" | |
| 290 [(set (match_operand:HI 0 "register_operand" "=q,r") | |
| 291 (match_operand:HI 1 "register_operand" "r,q"))] | |
| 292 "((stack_register_operand(operands[0], HImode) && register_operand (operands[1], HImode)) | |
| 293 || (register_operand (operands[0], HImode) && stack_register_operand(operands[1], HImode)))" | |
| 294 "* return output_movhi (insn, operands, NULL);" | |
| 295 [(set_attr "length" "5,2") | |
| 296 (set_attr "cc" "none,none")]) | |
| 297 | |
| 298 (define_insn "movhi_sp_r_irq_off" | |
| 299 [(set (match_operand:HI 0 "stack_register_operand" "=q") | |
| 300 (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r")] | |
| 301 UNSPECV_WRITE_SP_IRQ_OFF))] | |
| 302 "" | |
| 303 "out __SP_H__, %B1 | |
| 304 out __SP_L__, %A1" | |
| 305 [(set_attr "length" "2") | |
| 306 (set_attr "cc" "none")]) | |
| 307 | |
| 308 (define_insn "movhi_sp_r_irq_on" | |
| 309 [(set (match_operand:HI 0 "stack_register_operand" "=q") | |
| 310 (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r")] | |
| 311 UNSPECV_WRITE_SP_IRQ_ON))] | |
| 312 "" | |
| 313 "cli | |
| 314 out __SP_H__, %B1 | |
| 315 sei | |
| 316 out __SP_L__, %A1" | |
| 317 [(set_attr "length" "4") | |
| 318 (set_attr "cc" "none")]) | |
| 319 | |
| 320 (define_peephole2 | |
| 321 [(match_scratch:QI 2 "d") | |
| 322 (set (match_operand:HI 0 "l_register_operand" "") | |
| 323 (match_operand:HI 1 "immediate_operand" ""))] | |
| 324 "(operands[1] != const0_rtx | |
| 325 && operands[1] != constm1_rtx)" | |
| 326 [(parallel [(set (match_dup 0) (match_dup 1)) | |
| 327 (clobber (match_dup 2))])] | |
| 328 "") | |
| 329 | |
| 330 ;; '*' because it is not used in rtl generation, only in above peephole | |
| 331 (define_insn "*reload_inhi" | |
| 332 [(set (match_operand:HI 0 "register_operand" "=r") | |
| 333 (match_operand:HI 1 "immediate_operand" "i")) | |
| 334 (clobber (match_operand:QI 2 "register_operand" "=&d"))] | |
| 335 "reload_completed" | |
| 336 "* return output_reload_inhi (insn, operands, NULL);" | |
| 337 [(set_attr "length" "4") | |
| 338 (set_attr "cc" "none")]) | |
| 339 | |
| 340 (define_insn "*movhi" | |
| 341 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,d,*r,q,r") | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
342 (match_operand:HI 1 "general_operand" "rL,m,rL,i,i,r,q"))] |
| 0 | 343 "(register_operand (operands[0],HImode) |
| 344 || register_operand (operands[1],HImode) || const0_rtx == operands[1])" | |
| 345 "* return output_movhi (insn, operands, NULL);" | |
| 346 [(set_attr "length" "2,6,7,2,6,5,2") | |
| 347 (set_attr "cc" "none,clobber,clobber,none,clobber,none,none")]) | |
| 348 | |
| 349 (define_peephole2 ; movw | |
| 350 [(set (match_operand:QI 0 "even_register_operand" "") | |
| 351 (match_operand:QI 1 "even_register_operand" "")) | |
| 352 (set (match_operand:QI 2 "odd_register_operand" "") | |
| 353 (match_operand:QI 3 "odd_register_operand" ""))] | |
| 354 "(AVR_HAVE_MOVW | |
| 355 && REGNO (operands[0]) == REGNO (operands[2]) - 1 | |
| 356 && REGNO (operands[1]) == REGNO (operands[3]) - 1)" | |
| 357 [(set (match_dup 4) (match_dup 5))] | |
| 358 { | |
| 359 operands[4] = gen_rtx_REG (HImode, REGNO (operands[0])); | |
| 360 operands[5] = gen_rtx_REG (HImode, REGNO (operands[1])); | |
| 361 }) | |
| 362 | |
| 363 (define_peephole2 ; movw_r | |
| 364 [(set (match_operand:QI 0 "odd_register_operand" "") | |
| 365 (match_operand:QI 1 "odd_register_operand" "")) | |
| 366 (set (match_operand:QI 2 "even_register_operand" "") | |
| 367 (match_operand:QI 3 "even_register_operand" ""))] | |
| 368 "(AVR_HAVE_MOVW | |
| 369 && REGNO (operands[2]) == REGNO (operands[0]) - 1 | |
| 370 && REGNO (operands[3]) == REGNO (operands[1]) - 1)" | |
| 371 [(set (match_dup 4) (match_dup 5))] | |
| 372 { | |
| 373 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2])); | |
| 374 operands[5] = gen_rtx_REG (HImode, REGNO (operands[3])); | |
| 375 }) | |
| 376 | |
| 377 ;;========================================================================== | |
| 378 ;; move double word (32 bit) | |
| 379 | |
| 380 (define_expand "movsi" | |
| 381 [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
| 382 (match_operand:SI 1 "general_operand" ""))] | |
| 383 "" | |
| 384 " | |
| 385 { | |
| 386 /* One of the ops has to be in a register. */ | |
| 387 if (!register_operand (operand0, SImode) | |
| 388 && !(register_operand (operand1, SImode) || const0_rtx == operand1)) | |
| 389 { | |
| 390 operands[1] = copy_to_mode_reg (SImode, operand1); | |
| 391 } | |
| 392 }") | |
| 393 | |
| 394 | |
| 395 | |
| 396 (define_peephole2 ; movsi_lreg_const | |
| 397 [(match_scratch:QI 2 "d") | |
| 398 (set (match_operand:SI 0 "l_register_operand" "") | |
| 399 (match_operand:SI 1 "immediate_operand" "")) | |
| 400 (match_dup 2)] | |
| 401 "(operands[1] != const0_rtx | |
| 402 && operands[1] != constm1_rtx)" | |
| 403 [(parallel [(set (match_dup 0) (match_dup 1)) | |
| 404 (clobber (match_dup 2))])] | |
| 405 "") | |
| 406 | |
| 407 ;; '*' because it is not used in rtl generation. | |
| 408 (define_insn "*reload_insi" | |
| 409 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 410 (match_operand:SI 1 "immediate_operand" "i")) | |
| 411 (clobber (match_operand:QI 2 "register_operand" "=&d"))] | |
| 412 "reload_completed" | |
| 413 "* return output_reload_insisf (insn, operands, NULL);" | |
| 414 [(set_attr "length" "8") | |
| 415 (set_attr "cc" "none")]) | |
| 416 | |
| 417 | |
| 418 (define_insn "*movsi" | |
| 419 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,Qm,!d,r") | |
| 420 (match_operand:SI 1 "general_operand" "r,L,Qm,rL,i,i"))] | |
| 421 "(register_operand (operands[0],SImode) | |
| 422 || register_operand (operands[1],SImode) || const0_rtx == operands[1])" | |
| 423 "* return output_movsisf (insn, operands, NULL);" | |
| 424 [(set_attr "length" "4,4,8,9,4,10") | |
| 425 (set_attr "cc" "none,set_zn,clobber,clobber,none,clobber")]) | |
| 426 | |
| 427 ;; fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff | |
| 428 ;; move floating point numbers (32 bit) | |
| 429 | |
| 430 (define_expand "movsf" | |
| 431 [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
| 432 (match_operand:SF 1 "general_operand" ""))] | |
| 433 "" | |
| 434 " | |
| 435 { | |
| 436 /* One of the ops has to be in a register. */ | |
| 437 if (!register_operand (operand1, SFmode) | |
| 438 && !register_operand (operand0, SFmode)) | |
| 439 { | |
| 440 operands[1] = copy_to_mode_reg (SFmode, operand1); | |
| 441 } | |
| 442 }") | |
| 443 | |
| 444 (define_insn "*movsf" | |
| 445 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,Qm,!d,r") | |
| 446 (match_operand:SF 1 "general_operand" "r,G,Qm,r,F,F"))] | |
| 447 "register_operand (operands[0], SFmode) | |
| 448 || register_operand (operands[1], SFmode)" | |
| 449 "* return output_movsisf (insn, operands, NULL);" | |
| 450 [(set_attr "length" "4,4,8,9,4,10") | |
| 451 (set_attr "cc" "none,set_zn,clobber,clobber,none,clobber")]) | |
| 452 | |
| 453 ;;========================================================================= | |
| 454 ;; move string (like memcpy) | |
| 455 ;; implement as RTL loop | |
| 456 | |
| 457 (define_expand "movmemhi" | |
| 458 [(parallel [(set (match_operand:BLK 0 "memory_operand" "") | |
| 459 (match_operand:BLK 1 "memory_operand" "")) | |
| 460 (use (match_operand:HI 2 "const_int_operand" "")) | |
| 461 (use (match_operand:HI 3 "const_int_operand" ""))])] | |
| 462 "" | |
| 463 "{ | |
| 464 int prob; | |
| 465 HOST_WIDE_INT count; | |
| 466 enum machine_mode mode; | |
| 467 rtx label = gen_label_rtx (); | |
| 468 rtx loop_reg; | |
| 469 rtx jump; | |
| 470 | |
| 471 /* Copy pointers into new psuedos - they will be changed. */ | |
| 472 rtx addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); | |
| 473 rtx addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); | |
| 474 | |
| 475 /* Create rtx for tmp register - we use this as scratch. */ | |
| 476 rtx tmp_reg_rtx = gen_rtx_REG (QImode, TMP_REGNO); | |
| 477 | |
| 478 if (GET_CODE (operands[2]) != CONST_INT) | |
| 479 FAIL; | |
| 480 | |
| 481 count = INTVAL (operands[2]); | |
| 482 if (count <= 0) | |
| 483 FAIL; | |
| 484 | |
| 485 /* Work out branch probability for latter use. */ | |
| 486 prob = REG_BR_PROB_BASE - REG_BR_PROB_BASE / count; | |
| 487 | |
| 488 /* See if constant fit 8 bits. */ | |
| 489 mode = (count < 0x100) ? QImode : HImode; | |
| 490 /* Create loop counter register. */ | |
| 491 loop_reg = copy_to_mode_reg (mode, gen_int_mode (count, mode)); | |
| 492 | |
| 493 /* Now create RTL code for move loop. */ | |
| 494 /* Label at top of loop. */ | |
| 495 emit_label (label); | |
| 496 | |
| 497 /* Move one byte into scratch and inc pointer. */ | |
| 498 emit_move_insn (tmp_reg_rtx, gen_rtx_MEM (QImode, addr1)); | |
| 499 emit_move_insn (addr1, gen_rtx_PLUS (Pmode, addr1, const1_rtx)); | |
| 500 | |
| 501 /* Move to mem and inc pointer. */ | |
| 502 emit_move_insn (gen_rtx_MEM (QImode, addr0), tmp_reg_rtx); | |
| 503 emit_move_insn (addr0, gen_rtx_PLUS (Pmode, addr0, const1_rtx)); | |
| 504 | |
| 505 /* Decrement count. */ | |
| 506 emit_move_insn (loop_reg, gen_rtx_PLUS (mode, loop_reg, constm1_rtx)); | |
| 507 | |
| 508 /* Compare with zero and jump if not equal. */ | |
| 509 emit_cmp_and_jump_insns (loop_reg, const0_rtx, NE, NULL_RTX, mode, 1, | |
| 510 label); | |
| 511 /* Set jump probability based on loop count. */ | |
| 512 jump = get_last_insn (); | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
513 add_reg_note (jump, REG_BR_PROB, GEN_INT (prob)); |
| 0 | 514 DONE; |
| 515 }") | |
| 516 | |
| 517 ;; =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 | |
| 518 ;; memset (%0, %2, %1) | |
| 519 | |
| 520 (define_expand "setmemhi" | |
| 521 [(parallel [(set (match_operand:BLK 0 "memory_operand" "") | |
| 522 (match_operand 2 "const_int_operand" "")) | |
| 523 (use (match_operand:HI 1 "const_int_operand" "")) | |
| 524 (use (match_operand:HI 3 "const_int_operand" "n")) | |
| 525 (clobber (match_scratch:HI 4 "")) | |
| 526 (clobber (match_dup 5))])] | |
| 527 "" | |
| 528 "{ | |
| 529 rtx addr0; | |
| 530 int cnt8; | |
| 531 enum machine_mode mode; | |
| 532 | |
| 533 /* If value to set is not zero, use the library routine. */ | |
| 534 if (operands[2] != const0_rtx) | |
| 535 FAIL; | |
| 536 | |
| 537 if (GET_CODE (operands[1]) != CONST_INT) | |
| 538 FAIL; | |
| 539 | |
| 540 cnt8 = byte_immediate_operand (operands[1], GET_MODE (operands[1])); | |
| 541 mode = cnt8 ? QImode : HImode; | |
| 542 operands[5] = gen_rtx_SCRATCH (mode); | |
| 543 operands[1] = copy_to_mode_reg (mode, | |
| 544 gen_int_mode (INTVAL (operands[1]), mode)); | |
| 545 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); | |
| 546 operands[0] = gen_rtx_MEM (BLKmode, addr0); | |
| 547 }") | |
| 548 | |
| 549 (define_insn "*clrmemqi" | |
| 550 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e")) | |
| 551 (const_int 0)) | |
| 552 (use (match_operand:QI 1 "register_operand" "r")) | |
| 553 (use (match_operand:QI 2 "const_int_operand" "n")) | |
| 554 (clobber (match_scratch:HI 3 "=0")) | |
| 555 (clobber (match_scratch:QI 4 "=&1"))] | |
| 556 "" | |
| 557 "st %a0+,__zero_reg__ | |
| 558 dec %1 | |
| 559 brne .-6" | |
| 560 [(set_attr "length" "3") | |
| 561 (set_attr "cc" "clobber")]) | |
| 562 | |
| 563 (define_insn "*clrmemhi" | |
| 564 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e,e")) | |
| 565 (const_int 0)) | |
| 566 (use (match_operand:HI 1 "register_operand" "!w,d")) | |
| 567 (use (match_operand:HI 2 "const_int_operand" "n,n")) | |
| 568 (clobber (match_scratch:HI 3 "=0,0")) | |
| 569 (clobber (match_scratch:HI 4 "=&1,&1"))] | |
| 570 "" | |
| 571 "*{ | |
| 572 if (which_alternative==0) | |
| 573 return (AS2 (st,%a0+,__zero_reg__) CR_TAB | |
| 574 AS2 (sbiw,%A1,1) CR_TAB | |
| 575 AS1 (brne,.-6)); | |
| 576 else | |
| 577 return (AS2 (st,%a0+,__zero_reg__) CR_TAB | |
| 578 AS2 (subi,%A1,1) CR_TAB | |
| 579 AS2 (sbci,%B1,0) CR_TAB | |
| 580 AS1 (brne,.-8)); | |
| 581 }" | |
| 582 [(set_attr "length" "3,4") | |
| 583 (set_attr "cc" "clobber,clobber")]) | |
| 584 | |
| 585 (define_expand "strlenhi" | |
| 586 [(set (match_dup 4) | |
| 587 (unspec:HI [(match_operand:BLK 1 "memory_operand" "") | |
| 588 (match_operand:QI 2 "const_int_operand" "") | |
| 589 (match_operand:HI 3 "immediate_operand" "")] | |
| 590 UNSPEC_STRLEN)) | |
| 591 (set (match_dup 4) (plus:HI (match_dup 4) | |
| 592 (const_int -1))) | |
| 593 (set (match_operand:HI 0 "register_operand" "") | |
| 594 (minus:HI (match_dup 4) | |
| 595 (match_dup 5)))] | |
| 596 "" | |
| 597 "{ | |
| 598 rtx addr; | |
| 599 if (! (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0)) | |
| 600 FAIL; | |
| 601 addr = copy_to_mode_reg (Pmode, XEXP (operands[1],0)); | |
| 602 operands[1] = gen_rtx_MEM (BLKmode, addr); | |
| 603 operands[5] = addr; | |
| 604 operands[4] = gen_reg_rtx (HImode); | |
| 605 }") | |
| 606 | |
| 607 (define_insn "*strlenhi" | |
| 608 [(set (match_operand:HI 0 "register_operand" "=e") | |
| 609 (unspec:HI [(mem:BLK (match_operand:HI 1 "register_operand" "%0")) | |
| 610 (const_int 0) | |
| 611 (match_operand:HI 2 "immediate_operand" "i")] | |
| 612 UNSPEC_STRLEN))] | |
| 613 "" | |
| 614 "ld __tmp_reg__,%a0+ | |
| 615 tst __tmp_reg__ | |
| 616 brne .-6" | |
| 617 [(set_attr "length" "3") | |
| 618 (set_attr "cc" "clobber")]) | |
| 619 | |
| 620 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ | |
| 621 ; add bytes | |
| 622 | |
| 623 (define_insn "addqi3" | |
| 624 [(set (match_operand:QI 0 "register_operand" "=r,d,r,r") | |
| 625 (plus:QI (match_operand:QI 1 "register_operand" "%0,0,0,0") | |
| 626 (match_operand:QI 2 "nonmemory_operand" "r,i,P,N")))] | |
| 627 "" | |
| 628 "@ | |
| 629 add %0,%2 | |
| 630 subi %0,lo8(-(%2)) | |
| 631 inc %0 | |
| 632 dec %0" | |
| 633 [(set_attr "length" "1,1,1,1") | |
| 634 (set_attr "cc" "set_czn,set_czn,set_zn,set_zn")]) | |
| 635 | |
| 636 | |
| 637 (define_expand "addhi3" | |
| 638 [(set (match_operand:HI 0 "register_operand" "") | |
| 639 (plus:HI (match_operand:HI 1 "register_operand" "") | |
| 640 (match_operand:HI 2 "nonmemory_operand" "")))] | |
| 641 "" | |
| 642 " | |
| 643 { | |
| 644 if (GET_CODE (operands[2]) == CONST_INT) | |
| 645 { | |
| 646 short tmp = INTVAL (operands[2]); | |
| 647 operands[2] = GEN_INT(tmp); | |
| 648 } | |
| 649 }") | |
| 650 | |
| 651 | |
| 652 (define_insn "*addhi3_zero_extend" | |
| 653 [(set (match_operand:HI 0 "register_operand" "=r") | |
| 654 (plus:HI (zero_extend:HI | |
| 655 (match_operand:QI 1 "register_operand" "r")) | |
| 656 (match_operand:HI 2 "register_operand" "0")))] | |
| 657 "" | |
| 658 "add %A0,%1 | |
| 659 adc %B0,__zero_reg__" | |
| 660 [(set_attr "length" "2") | |
| 661 (set_attr "cc" "set_n")]) | |
| 662 | |
| 663 (define_insn "*addhi3_zero_extend1" | |
| 664 [(set (match_operand:HI 0 "register_operand" "=r") | |
| 665 (plus:HI (match_operand:HI 1 "register_operand" "%0") | |
| 666 (zero_extend:HI | |
| 667 (match_operand:QI 2 "register_operand" "r"))))] | |
| 668 "" | |
| 669 "add %A0,%2 | |
| 670 adc %B0,__zero_reg__" | |
| 671 [(set_attr "length" "2") | |
| 672 (set_attr "cc" "set_n")]) | |
| 673 | |
| 674 (define_insn "*addhi3_sp_R_pc2" | |
| 675 [(set (match_operand:HI 1 "stack_register_operand" "=q") | |
| 676 (plus:HI (match_operand:HI 2 "stack_register_operand" "q") | |
| 677 (match_operand:HI 0 "avr_sp_immediate_operand" "R")))] | |
| 678 "AVR_2_BYTE_PC" | |
| 679 "*{ | |
| 680 if (CONST_INT_P (operands[0])) | |
| 681 { | |
| 682 switch(INTVAL (operands[0])) | |
| 683 { | |
| 684 case -6: | |
| 685 return \"rcall .\" CR_TAB | |
| 686 \"rcall .\" CR_TAB | |
| 687 \"rcall .\"; | |
| 688 case -5: | |
| 689 return \"rcall .\" CR_TAB | |
| 690 \"rcall .\" CR_TAB | |
| 691 \"push __tmp_reg__\"; | |
| 692 case -4: | |
| 693 return \"rcall .\" CR_TAB | |
| 694 \"rcall .\"; | |
| 695 case -3: | |
| 696 return \"rcall .\" CR_TAB | |
| 697 \"push __tmp_reg__\"; | |
| 698 case -2: | |
| 699 return \"rcall .\"; | |
| 700 case -1: | |
| 701 return \"push __tmp_reg__\"; | |
| 702 case 0: | |
| 703 return \"\"; | |
| 704 case 1: | |
| 705 return \"pop __tmp_reg__\"; | |
| 706 case 2: | |
| 707 return \"pop __tmp_reg__\" CR_TAB | |
| 708 \"pop __tmp_reg__\"; | |
| 709 case 3: | |
| 710 return \"pop __tmp_reg__\" CR_TAB | |
| 711 \"pop __tmp_reg__\" CR_TAB | |
| 712 \"pop __tmp_reg__\"; | |
| 713 case 4: | |
| 714 return \"pop __tmp_reg__\" CR_TAB | |
| 715 \"pop __tmp_reg__\" CR_TAB | |
| 716 \"pop __tmp_reg__\" CR_TAB | |
| 717 \"pop __tmp_reg__\"; | |
| 718 case 5: | |
| 719 return \"pop __tmp_reg__\" CR_TAB | |
| 720 \"pop __tmp_reg__\" CR_TAB | |
| 721 \"pop __tmp_reg__\" CR_TAB | |
| 722 \"pop __tmp_reg__\" CR_TAB | |
| 723 \"pop __tmp_reg__\"; | |
| 724 } | |
| 725 } | |
| 726 return \"bug\"; | |
| 727 }" | |
| 728 [(set (attr "length") | |
| 729 (cond [(eq (const_int -6) (symbol_ref "INTVAL (operands[0])")) (const_int 3) | |
| 730 (eq (const_int -5) (symbol_ref "INTVAL (operands[0])")) (const_int 3) | |
| 731 (eq (const_int -4) (symbol_ref "INTVAL (operands[0])")) (const_int 2) | |
| 732 (eq (const_int -3) (symbol_ref "INTVAL (operands[0])")) (const_int 2) | |
| 733 (eq (const_int -2) (symbol_ref "INTVAL (operands[0])")) (const_int 1) | |
| 734 (eq (const_int -1) (symbol_ref "INTVAL (operands[0])")) (const_int 1) | |
| 735 (eq (const_int 0) (symbol_ref "INTVAL (operands[0])")) (const_int 0) | |
| 736 (eq (const_int 1) (symbol_ref "INTVAL (operands[0])")) (const_int 1) | |
| 737 (eq (const_int 2) (symbol_ref "INTVAL (operands[0])")) (const_int 2) | |
| 738 (eq (const_int 3) (symbol_ref "INTVAL (operands[0])")) (const_int 3) | |
| 739 (eq (const_int 4) (symbol_ref "INTVAL (operands[0])")) (const_int 4) | |
| 740 (eq (const_int 5) (symbol_ref "INTVAL (operands[0])")) (const_int 5)] | |
| 741 (const_int 0)))]) | |
| 742 | |
| 743 (define_insn "*addhi3_sp_R_pc3" | |
| 744 [(set (match_operand:HI 1 "stack_register_operand" "=q") | |
| 745 (plus:HI (match_operand:HI 2 "stack_register_operand" "q") | |
| 746 (match_operand:QI 0 "avr_sp_immediate_operand" "R")))] | |
| 747 "AVR_3_BYTE_PC" | |
| 748 "*{ | |
| 749 if (CONST_INT_P (operands[0])) | |
| 750 { | |
| 751 switch(INTVAL (operands[0])) | |
| 752 { | |
| 753 case -6: | |
| 754 return \"rcall .\" CR_TAB | |
| 755 \"rcall .\"; | |
| 756 case -5: | |
| 757 return \"rcall .\" CR_TAB | |
| 758 \"push __tmp_reg__\" CR_TAB | |
| 759 \"push __tmp_reg__\"; | |
| 760 case -4: | |
| 761 return \"rcall .\" CR_TAB | |
| 762 \"push __tmp_reg__\"; | |
| 763 case -3: | |
| 764 return \"rcall .\"; | |
| 765 case -2: | |
| 766 return \"push __tmp_reg__\" CR_TAB | |
| 767 \"push __tmp_reg__\"; | |
| 768 case -1: | |
| 769 return \"push __tmp_reg__\"; | |
| 770 case 0: | |
| 771 return \"\"; | |
| 772 case 1: | |
| 773 return \"pop __tmp_reg__\"; | |
| 774 case 2: | |
| 775 return \"pop __tmp_reg__\" CR_TAB | |
| 776 \"pop __tmp_reg__\"; | |
| 777 case 3: | |
| 778 return \"pop __tmp_reg__\" CR_TAB | |
| 779 \"pop __tmp_reg__\" CR_TAB | |
| 780 \"pop __tmp_reg__\"; | |
| 781 case 4: | |
| 782 return \"pop __tmp_reg__\" CR_TAB | |
| 783 \"pop __tmp_reg__\" CR_TAB | |
| 784 \"pop __tmp_reg__\" CR_TAB | |
| 785 \"pop __tmp_reg__\"; | |
| 786 case 5: | |
| 787 return \"pop __tmp_reg__\" CR_TAB | |
| 788 \"pop __tmp_reg__\" CR_TAB | |
| 789 \"pop __tmp_reg__\" CR_TAB | |
| 790 \"pop __tmp_reg__\" CR_TAB | |
| 791 \"pop __tmp_reg__\"; | |
| 792 } | |
| 793 } | |
| 794 return \"bug\"; | |
| 795 }" | |
| 796 [(set (attr "length") | |
| 797 (cond [(eq (const_int -6) (symbol_ref "INTVAL (operands[0])")) (const_int 2) | |
| 798 (eq (const_int -5) (symbol_ref "INTVAL (operands[0])")) (const_int 3) | |
| 799 (eq (const_int -4) (symbol_ref "INTVAL (operands[0])")) (const_int 2) | |
| 800 (eq (const_int -3) (symbol_ref "INTVAL (operands[0])")) (const_int 1) | |
| 801 (eq (const_int -2) (symbol_ref "INTVAL (operands[0])")) (const_int 2) | |
| 802 (eq (const_int -1) (symbol_ref "INTVAL (operands[0])")) (const_int 1) | |
| 803 (eq (const_int 0) (symbol_ref "INTVAL (operands[0])")) (const_int 0) | |
| 804 (eq (const_int 1) (symbol_ref "INTVAL (operands[0])")) (const_int 1) | |
| 805 (eq (const_int 2) (symbol_ref "INTVAL (operands[0])")) (const_int 2) | |
| 806 (eq (const_int 3) (symbol_ref "INTVAL (operands[0])")) (const_int 3) | |
| 807 (eq (const_int 4) (symbol_ref "INTVAL (operands[0])")) (const_int 4) | |
| 808 (eq (const_int 5) (symbol_ref "INTVAL (operands[0])")) (const_int 5)] | |
| 809 (const_int 0)))]) | |
| 810 | |
| 811 (define_insn "*addhi3" | |
| 812 [(set (match_operand:HI 0 "register_operand" "=r,!w,!w,d,r,r") | |
| 813 (plus:HI | |
| 814 (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0") | |
| 815 (match_operand:HI 2 "nonmemory_operand" "r,I,J,i,P,N")))] | |
| 816 "" | |
| 817 "@ | |
| 818 add %A0,%A2\;adc %B0,%B2 | |
| 819 adiw %A0,%2 | |
| 820 sbiw %A0,%n2 | |
| 821 subi %A0,lo8(-(%2))\;sbci %B0,hi8(-(%2)) | |
| 822 sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__ | |
| 823 sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__" | |
| 824 [(set_attr "length" "2,1,1,2,3,3") | |
| 825 (set_attr "cc" "set_n,set_czn,set_czn,set_czn,set_n,set_n")]) | |
| 826 | |
| 827 (define_insn "addsi3" | |
| 828 [(set (match_operand:SI 0 "register_operand" "=r,!w,!w,d,r,r") | |
| 829 (plus:SI | |
| 830 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0") | |
| 831 (match_operand:SI 2 "nonmemory_operand" "r,I,J,i,P,N")))] | |
| 832 "" | |
| 833 "@ | |
| 834 add %A0,%A2\;adc %B0,%B2\;adc %C0,%C2\;adc %D0,%D2 | |
| 835 adiw %0,%2\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__ | |
| 836 sbiw %0,%n2\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__ | |
| 837 subi %0,lo8(-(%2))\;sbci %B0,hi8(-(%2))\;sbci %C0,hlo8(-(%2))\;sbci %D0,hhi8(-(%2)) | |
| 838 sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__ | |
| 839 sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__" | |
| 840 [(set_attr "length" "4,3,3,4,5,5") | |
| 841 (set_attr "cc" "set_n,set_n,set_czn,set_czn,set_n,set_n")]) | |
| 842 | |
| 843 (define_insn "*addsi3_zero_extend" | |
| 844 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 845 (plus:SI (zero_extend:SI | |
| 846 (match_operand:QI 1 "register_operand" "r")) | |
| 847 (match_operand:SI 2 "register_operand" "0")))] | |
| 848 "" | |
| 849 "add %A0,%1 | |
| 850 adc %B0,__zero_reg__ | |
| 851 adc %C0,__zero_reg__ | |
| 852 adc %D0,__zero_reg__" | |
| 853 [(set_attr "length" "4") | |
| 854 (set_attr "cc" "set_n")]) | |
| 855 | |
| 856 ;----------------------------------------------------------------------------- | |
| 857 ; sub bytes | |
| 858 (define_insn "subqi3" | |
| 859 [(set (match_operand:QI 0 "register_operand" "=r,d") | |
| 860 (minus:QI (match_operand:QI 1 "register_operand" "0,0") | |
| 861 (match_operand:QI 2 "nonmemory_operand" "r,i")))] | |
| 862 "" | |
| 863 "@ | |
| 864 sub %0,%2 | |
| 865 subi %0,lo8(%2)" | |
| 866 [(set_attr "length" "1,1") | |
| 867 (set_attr "cc" "set_czn,set_czn")]) | |
| 868 | |
| 869 (define_insn "subhi3" | |
| 870 [(set (match_operand:HI 0 "register_operand" "=r,d") | |
| 871 (minus:HI (match_operand:HI 1 "register_operand" "0,0") | |
| 872 (match_operand:HI 2 "nonmemory_operand" "r,i")))] | |
| 873 "" | |
| 874 "@ | |
| 875 sub %A0,%A2\;sbc %B0,%B2 | |
| 876 subi %A0,lo8(%2)\;sbci %B0,hi8(%2)" | |
| 877 [(set_attr "length" "2,2") | |
| 878 (set_attr "cc" "set_czn,set_czn")]) | |
| 879 | |
| 880 (define_insn "*subhi3_zero_extend1" | |
| 881 [(set (match_operand:HI 0 "register_operand" "=r") | |
| 882 (minus:HI (match_operand:HI 1 "register_operand" "0") | |
| 883 (zero_extend:HI | |
| 884 (match_operand:QI 2 "register_operand" "r"))))] | |
| 885 "" | |
| 886 "sub %A0,%2 | |
| 887 sbc %B0,__zero_reg__" | |
| 888 [(set_attr "length" "2") | |
| 889 (set_attr "cc" "set_n")]) | |
| 890 | |
| 891 (define_insn "subsi3" | |
| 892 [(set (match_operand:SI 0 "register_operand" "=r,d") | |
| 893 (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
| 894 (match_operand:SI 2 "nonmemory_operand" "r,i")))] | |
| 895 "" | |
| 896 "@ | |
| 897 sub %0,%2\;sbc %B0,%B2\;sbc %C0,%C2\;sbc %D0,%D2 | |
| 898 subi %A0,lo8(%2)\;sbci %B0,hi8(%2)\;sbci %C0,hlo8(%2)\;sbci %D0,hhi8(%2)" | |
| 899 [(set_attr "length" "4,4") | |
| 900 (set_attr "cc" "set_czn,set_czn")]) | |
| 901 | |
| 902 (define_insn "*subsi3_zero_extend" | |
| 903 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 904 (minus:SI (match_operand:SI 1 "register_operand" "0") | |
| 905 (zero_extend:SI | |
| 906 (match_operand:QI 2 "register_operand" "r"))))] | |
| 907 "" | |
| 908 "sub %A0,%2 | |
| 909 sbc %B0,__zero_reg__ | |
| 910 sbc %C0,__zero_reg__ | |
| 911 sbc %D0,__zero_reg__" | |
| 912 [(set_attr "length" "4") | |
| 913 (set_attr "cc" "set_n")]) | |
| 914 | |
| 915 ;****************************************************************************** | |
| 916 ; mul | |
| 917 | |
| 918 (define_expand "mulqi3" | |
| 919 [(set (match_operand:QI 0 "register_operand" "") | |
| 920 (mult:QI (match_operand:QI 1 "register_operand" "") | |
| 921 (match_operand:QI 2 "register_operand" "")))] | |
| 922 "" | |
| 923 "{ | |
| 924 if (!AVR_HAVE_MUL) | |
| 925 { | |
| 926 emit_insn (gen_mulqi3_call (operands[0], operands[1], operands[2])); | |
| 927 DONE; | |
| 928 } | |
| 929 }") | |
| 930 | |
| 931 (define_insn "*mulqi3_enh" | |
| 932 [(set (match_operand:QI 0 "register_operand" "=r") | |
| 933 (mult:QI (match_operand:QI 1 "register_operand" "r") | |
| 934 (match_operand:QI 2 "register_operand" "r")))] | |
| 935 "AVR_HAVE_MUL" | |
| 936 "mul %1,%2 | |
| 937 mov %0,r0 | |
| 938 clr r1" | |
| 939 [(set_attr "length" "3") | |
| 940 (set_attr "cc" "clobber")]) | |
| 941 | |
| 942 (define_expand "mulqi3_call" | |
| 943 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" "")) | |
| 944 (set (reg:QI 22) (match_operand:QI 2 "register_operand" "")) | |
| 945 (parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22))) | |
| 946 (clobber (reg:QI 22))]) | |
| 947 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))] | |
| 948 "" | |
| 949 "") | |
| 950 | |
| 951 (define_insn "*mulqi3_call" | |
| 952 [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22))) | |
| 953 (clobber (reg:QI 22))] | |
| 954 "!AVR_HAVE_MUL" | |
| 955 "%~call __mulqi3" | |
| 956 [(set_attr "type" "xcall") | |
| 957 (set_attr "cc" "clobber")]) | |
| 958 | |
| 959 (define_insn "mulqihi3" | |
| 960 [(set (match_operand:HI 0 "register_operand" "=r") | |
| 961 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d")) | |
| 962 (sign_extend:HI (match_operand:QI 2 "register_operand" "d"))))] | |
| 963 "AVR_HAVE_MUL" | |
| 964 "muls %1,%2 | |
| 965 movw %0,r0 | |
| 966 clr r1" | |
| 967 [(set_attr "length" "3") | |
| 968 (set_attr "cc" "clobber")]) | |
| 969 | |
| 970 (define_insn "umulqihi3" | |
| 971 [(set (match_operand:HI 0 "register_operand" "=r") | |
| 972 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r")) | |
| 973 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))] | |
| 974 "AVR_HAVE_MUL" | |
| 975 "mul %1,%2 | |
| 976 movw %0,r0 | |
| 977 clr r1" | |
| 978 [(set_attr "length" "3") | |
| 979 (set_attr "cc" "clobber")]) | |
| 980 | |
| 981 (define_expand "mulhi3" | |
| 982 [(set (match_operand:HI 0 "register_operand" "") | |
| 983 (mult:HI (match_operand:HI 1 "register_operand" "") | |
| 984 (match_operand:HI 2 "register_operand" "")))] | |
| 985 "" | |
| 986 " | |
| 987 { | |
| 988 if (!AVR_HAVE_MUL) | |
| 989 { | |
| 990 emit_insn (gen_mulhi3_call (operands[0], operands[1], operands[2])); | |
| 991 DONE; | |
| 992 } | |
| 993 }") | |
| 994 | |
| 995 (define_insn "*mulhi3_enh" | |
| 996 [(set (match_operand:HI 0 "register_operand" "=&r") | |
| 997 (mult:HI (match_operand:HI 1 "register_operand" "r") | |
| 998 (match_operand:HI 2 "register_operand" "r")))] | |
| 999 "AVR_HAVE_MUL" | |
| 1000 "mul %A1,%A2 | |
| 1001 movw %0,r0 | |
| 1002 mul %A1,%B2 | |
| 1003 add %B0,r0 | |
| 1004 mul %B1,%A2 | |
| 1005 add %B0,r0 | |
| 1006 clr r1" | |
| 1007 [(set_attr "length" "7") | |
| 1008 (set_attr "cc" "clobber")]) | |
| 1009 | |
| 1010 (define_expand "mulhi3_call" | |
| 1011 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" "")) | |
| 1012 (set (reg:HI 22) (match_operand:HI 2 "register_operand" "")) | |
| 1013 (parallel [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22))) | |
| 1014 (clobber (reg:HI 22)) | |
| 1015 (clobber (reg:QI 21))]) | |
| 1016 (set (match_operand:HI 0 "register_operand" "") (reg:HI 24))] | |
| 1017 "" | |
| 1018 "") | |
| 1019 | |
| 1020 (define_insn "*mulhi3_call" | |
| 1021 [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22))) | |
| 1022 (clobber (reg:HI 22)) | |
| 1023 (clobber (reg:QI 21))] | |
| 1024 "!AVR_HAVE_MUL" | |
| 1025 "%~call __mulhi3" | |
| 1026 [(set_attr "type" "xcall") | |
| 1027 (set_attr "cc" "clobber")]) | |
| 1028 | |
| 1029 ;; Operand 2 (reg:SI 18) not clobbered on the enhanced core. | |
| 1030 ;; All call-used registers clobbered otherwise - normal library call. | |
| 1031 (define_expand "mulsi3" | |
| 1032 [(set (reg:SI 22) (match_operand:SI 1 "register_operand" "")) | |
| 1033 (set (reg:SI 18) (match_operand:SI 2 "register_operand" "")) | |
| 1034 (parallel [(set (reg:SI 22) (mult:SI (reg:SI 22) (reg:SI 18))) | |
| 1035 (clobber (reg:HI 26)) | |
| 1036 (clobber (reg:HI 30))]) | |
| 1037 (set (match_operand:SI 0 "register_operand" "") (reg:SI 22))] | |
| 1038 "AVR_HAVE_MUL" | |
| 1039 "") | |
| 1040 | |
| 1041 (define_insn "*mulsi3_call" | |
| 1042 [(set (reg:SI 22) (mult:SI (reg:SI 22) (reg:SI 18))) | |
| 1043 (clobber (reg:HI 26)) | |
| 1044 (clobber (reg:HI 30))] | |
| 1045 "AVR_HAVE_MUL" | |
| 1046 "%~call __mulsi3" | |
| 1047 [(set_attr "type" "xcall") | |
| 1048 (set_attr "cc" "clobber")]) | |
| 1049 | |
| 1050 ; / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % | |
| 1051 ; divmod | |
| 1052 | |
| 1053 ;; Generate libgcc.S calls ourselves, because: | |
| 1054 ;; - we know exactly which registers are clobbered (for QI and HI | |
| 1055 ;; modes, some of the call-used registers are preserved) | |
| 1056 ;; - we get both the quotient and the remainder at no extra cost | |
|
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1057 ;; - we split the patterns only after the first CSE passes because |
|
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1058 ;; CSE has problems to operate on hard regs. |
|
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1059 ;; |
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1060 (define_insn_and_split "divmodqi4" |
|
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1061 [(parallel [(set (match_operand:QI 0 "pseudo_register_operand" "") |
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1062 (div:QI (match_operand:QI 1 "pseudo_register_operand" "") |
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1063 (match_operand:QI 2 "pseudo_register_operand" ""))) |
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1064 (set (match_operand:QI 3 "pseudo_register_operand" "") |
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1065 (mod:QI (match_dup 1) (match_dup 2))) |
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1066 (clobber (reg:QI 22)) |
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1067 (clobber (reg:QI 23)) |
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1068 (clobber (reg:QI 24)) |
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1069 (clobber (reg:QI 25))])] |
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1070 "" |
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1071 "this divmodqi4 pattern should have been splitted;" |
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1072 "" |
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1073 [(set (reg:QI 24) (match_dup 1)) |
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1074 (set (reg:QI 22) (match_dup 2)) |
| 0 | 1075 (parallel [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22))) |
| 1076 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22))) | |
| 1077 (clobber (reg:QI 22)) | |
| 1078 (clobber (reg:QI 23))]) | |
|
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1079 (set (match_dup 0) (reg:QI 24)) |
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1080 (set (match_dup 3) (reg:QI 25))] |
| 0 | 1081 "") |
| 1082 | |
| 1083 (define_insn "*divmodqi4_call" | |
| 1084 [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22))) | |
| 1085 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22))) | |
| 1086 (clobber (reg:QI 22)) | |
| 1087 (clobber (reg:QI 23))] | |
| 1088 "" | |
| 1089 "%~call __divmodqi4" | |
| 1090 [(set_attr "type" "xcall") | |
| 1091 (set_attr "cc" "clobber")]) | |
| 1092 | |
|
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1093 (define_insn_and_split "udivmodqi4" |
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1094 [(parallel [(set (match_operand:QI 0 "pseudo_register_operand" "") |
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1095 (udiv:QI (match_operand:QI 1 "pseudo_register_operand" "") |
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1096 (match_operand:QI 2 "pseudo_register_operand" ""))) |
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1097 (set (match_operand:QI 3 "pseudo_register_operand" "") |
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1098 (umod:QI (match_dup 1) (match_dup 2))) |
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1099 (clobber (reg:QI 22)) |
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1100 (clobber (reg:QI 23)) |
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1101 (clobber (reg:QI 24)) |
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1102 (clobber (reg:QI 25))])] |
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1103 "" |
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1104 "this udivmodqi4 pattern should have been splitted;" |
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1105 "" |
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1106 [(set (reg:QI 24) (match_dup 1)) |
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1107 (set (reg:QI 22) (match_dup 2)) |
| 0 | 1108 (parallel [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22))) |
| 1109 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22))) | |
| 1110 (clobber (reg:QI 23))]) | |
|
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1111 (set (match_dup 0) (reg:QI 24)) |
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1112 (set (match_dup 3) (reg:QI 25))] |
| 0 | 1113 "") |
| 1114 | |
| 1115 (define_insn "*udivmodqi4_call" | |
| 1116 [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22))) | |
| 1117 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22))) | |
| 1118 (clobber (reg:QI 23))] | |
| 1119 "" | |
| 1120 "%~call __udivmodqi4" | |
| 1121 [(set_attr "type" "xcall") | |
| 1122 (set_attr "cc" "clobber")]) | |
| 1123 | |
|
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1124 (define_insn_and_split "divmodhi4" |
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1125 [(parallel [(set (match_operand:HI 0 "pseudo_register_operand" "") |
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1126 (div:HI (match_operand:HI 1 "pseudo_register_operand" "") |
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1127 (match_operand:HI 2 "pseudo_register_operand" ""))) |
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1128 (set (match_operand:HI 3 "pseudo_register_operand" "") |
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1129 (mod:HI (match_dup 1) (match_dup 2))) |
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1130 (clobber (reg:QI 21)) |
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1131 (clobber (reg:HI 22)) |
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1132 (clobber (reg:HI 24)) |
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1133 (clobber (reg:HI 26))])] |
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1134 "" |
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1135 "this should have been splitted;" |
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1136 "" |
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1137 [(set (reg:HI 24) (match_dup 1)) |
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update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1138 (set (reg:HI 22) (match_dup 2)) |
| 0 | 1139 (parallel [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22))) |
| 1140 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22))) | |
| 1141 (clobber (reg:HI 26)) | |
| 1142 (clobber (reg:QI 21))]) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1143 (set (match_dup 0) (reg:HI 22)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1144 (set (match_dup 3) (reg:HI 24))] |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1145 "") |
| 0 | 1146 |
| 1147 (define_insn "*divmodhi4_call" | |
| 1148 [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22))) | |
| 1149 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22))) | |
| 1150 (clobber (reg:HI 26)) | |
| 1151 (clobber (reg:QI 21))] | |
| 1152 "" | |
| 1153 "%~call __divmodhi4" | |
| 1154 [(set_attr "type" "xcall") | |
| 1155 (set_attr "cc" "clobber")]) | |
| 1156 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1157 (define_insn_and_split "udivmodhi4" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1158 [(parallel [(set (match_operand:HI 0 "pseudo_register_operand" "") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1159 (udiv:HI (match_operand:HI 1 "pseudo_register_operand" "") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1160 (match_operand:HI 2 "pseudo_register_operand" ""))) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1161 (set (match_operand:HI 3 "pseudo_register_operand" "") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1162 (umod:HI (match_dup 1) (match_dup 2))) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1163 (clobber (reg:QI 21)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1164 (clobber (reg:HI 22)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1165 (clobber (reg:HI 24)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1166 (clobber (reg:HI 26))])] |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1167 "" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1168 "this udivmodhi4 pattern should have been splitted.;" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1169 "" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1170 [(set (reg:HI 24) (match_dup 1)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1171 (set (reg:HI 22) (match_dup 2)) |
| 0 | 1172 (parallel [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22))) |
| 1173 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22))) | |
| 1174 (clobber (reg:HI 26)) | |
| 1175 (clobber (reg:QI 21))]) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1176 (set (match_dup 0) (reg:HI 22)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1177 (set (match_dup 3) (reg:HI 24))] |
| 0 | 1178 "") |
| 1179 | |
| 1180 (define_insn "*udivmodhi4_call" | |
| 1181 [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22))) | |
| 1182 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22))) | |
| 1183 (clobber (reg:HI 26)) | |
| 1184 (clobber (reg:QI 21))] | |
| 1185 "" | |
| 1186 "%~call __udivmodhi4" | |
| 1187 [(set_attr "type" "xcall") | |
| 1188 (set_attr "cc" "clobber")]) | |
| 1189 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1190 (define_insn_and_split "divmodsi4" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1191 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1192 (div:SI (match_operand:SI 1 "pseudo_register_operand" "") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1193 (match_operand:SI 2 "pseudo_register_operand" ""))) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1194 (set (match_operand:SI 3 "pseudo_register_operand" "") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1195 (mod:SI (match_dup 1) (match_dup 2))) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1196 (clobber (reg:SI 18)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1197 (clobber (reg:SI 22)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1198 (clobber (reg:HI 26)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1199 (clobber (reg:HI 30))])] |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1200 "" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1201 "this divmodsi4 pattern should have been splitted;" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1202 "" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1203 [(set (reg:SI 22) (match_dup 1)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1204 (set (reg:SI 18) (match_dup 2)) |
| 0 | 1205 (parallel [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18))) |
| 1206 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18))) | |
| 1207 (clobber (reg:HI 26)) | |
| 1208 (clobber (reg:HI 30))]) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1209 (set (match_dup 0) (reg:SI 18)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1210 (set (match_dup 3) (reg:SI 22))] |
| 0 | 1211 "") |
| 1212 | |
| 1213 (define_insn "*divmodsi4_call" | |
| 1214 [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18))) | |
| 1215 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18))) | |
| 1216 (clobber (reg:HI 26)) | |
| 1217 (clobber (reg:HI 30))] | |
| 1218 "" | |
| 1219 "%~call __divmodsi4" | |
| 1220 [(set_attr "type" "xcall") | |
| 1221 (set_attr "cc" "clobber")]) | |
| 1222 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1223 (define_insn_and_split "udivmodsi4" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1224 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1225 (udiv:SI (match_operand:SI 1 "pseudo_register_operand" "") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1226 (match_operand:SI 2 "pseudo_register_operand" ""))) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1227 (set (match_operand:SI 3 "pseudo_register_operand" "") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1228 (umod:SI (match_dup 1) (match_dup 2))) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1229 (clobber (reg:SI 18)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1230 (clobber (reg:SI 22)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1231 (clobber (reg:HI 26)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1232 (clobber (reg:HI 30))])] |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1233 "" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1234 "this udivmodsi4 pattern should have been splitted;" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1235 "" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1236 [(set (reg:SI 22) (match_dup 1)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1237 (set (reg:SI 18) (match_dup 2)) |
| 0 | 1238 (parallel [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18))) |
| 1239 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18))) | |
| 1240 (clobber (reg:HI 26)) | |
| 1241 (clobber (reg:HI 30))]) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1242 (set (match_dup 0) (reg:SI 18)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1243 (set (match_dup 3) (reg:SI 22))] |
| 0 | 1244 "") |
| 1245 | |
| 1246 (define_insn "*udivmodsi4_call" | |
| 1247 [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18))) | |
| 1248 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18))) | |
| 1249 (clobber (reg:HI 26)) | |
| 1250 (clobber (reg:HI 30))] | |
| 1251 "" | |
| 1252 "%~call __udivmodsi4" | |
| 1253 [(set_attr "type" "xcall") | |
| 1254 (set_attr "cc" "clobber")]) | |
| 1255 | |
| 1256 ;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& | |
| 1257 ; and | |
| 1258 | |
| 1259 (define_insn "andqi3" | |
| 1260 [(set (match_operand:QI 0 "register_operand" "=r,d") | |
| 1261 (and:QI (match_operand:QI 1 "register_operand" "%0,0") | |
| 1262 (match_operand:QI 2 "nonmemory_operand" "r,i")))] | |
| 1263 "" | |
| 1264 "@ | |
| 1265 and %0,%2 | |
| 1266 andi %0,lo8(%2)" | |
| 1267 [(set_attr "length" "1,1") | |
| 1268 (set_attr "cc" "set_zn,set_zn")]) | |
| 1269 | |
| 1270 (define_insn "andhi3" | |
| 1271 [(set (match_operand:HI 0 "register_operand" "=r,d,r") | |
| 1272 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0") | |
| 1273 (match_operand:HI 2 "nonmemory_operand" "r,i,M"))) | |
| 1274 (clobber (match_scratch:QI 3 "=X,X,&d"))] | |
| 1275 "" | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1276 { |
| 0 | 1277 if (which_alternative==0) |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1278 return ("and %A0,%A2" CR_TAB |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1279 "and %B0,%B2"); |
| 0 | 1280 else if (which_alternative==1) |
| 1281 { | |
| 1282 if (GET_CODE (operands[2]) == CONST_INT) | |
| 1283 { | |
| 1284 int mask = INTVAL (operands[2]); | |
| 1285 if ((mask & 0xff) != 0xff) | |
| 1286 output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands); | |
| 1287 if ((mask & 0xff00) != 0xff00) | |
| 1288 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands); | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1289 return ""; |
| 0 | 1290 } |
| 1291 return (AS2 (andi,%A0,lo8(%2)) CR_TAB | |
| 1292 AS2 (andi,%B0,hi8(%2))); | |
| 1293 } | |
| 1294 return (AS2 (ldi,%3,lo8(%2)) CR_TAB | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1295 "and %A0,%3" CR_TAB |
| 0 | 1296 AS1 (clr,%B0)); |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1297 } |
| 0 | 1298 [(set_attr "length" "2,2,3") |
| 1299 (set_attr "cc" "set_n,clobber,set_n")]) | |
| 1300 | |
| 1301 (define_insn "andsi3" | |
| 1302 [(set (match_operand:SI 0 "register_operand" "=r,d") | |
| 1303 (and:SI (match_operand:SI 1 "register_operand" "%0,0") | |
| 1304 (match_operand:SI 2 "nonmemory_operand" "r,i")))] | |
| 1305 "" | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1306 { |
| 0 | 1307 if (which_alternative==0) |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1308 return ("and %0,%2" CR_TAB |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1309 "and %B0,%B2" CR_TAB |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1310 "and %C0,%C2" CR_TAB |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1311 "and %D0,%D2"); |
| 0 | 1312 else if (which_alternative==1) |
| 1313 { | |
| 1314 if (GET_CODE (operands[2]) == CONST_INT) | |
| 1315 { | |
| 1316 HOST_WIDE_INT mask = INTVAL (operands[2]); | |
| 1317 if ((mask & 0xff) != 0xff) | |
| 1318 output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands); | |
| 1319 if ((mask & 0xff00) != 0xff00) | |
| 1320 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands); | |
| 1321 if ((mask & 0xff0000L) != 0xff0000L) | |
| 1322 output_asm_insn (AS2 (andi,%C0,hlo8(%2)), operands); | |
| 1323 if ((mask & 0xff000000L) != 0xff000000L) | |
| 1324 output_asm_insn (AS2 (andi,%D0,hhi8(%2)), operands); | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1325 return ""; |
| 0 | 1326 } |
| 1327 return (AS2 (andi, %A0,lo8(%2)) CR_TAB | |
| 1328 AS2 (andi, %B0,hi8(%2)) CR_TAB | |
| 1329 AS2 (andi, %C0,hlo8(%2)) CR_TAB | |
| 1330 AS2 (andi, %D0,hhi8(%2))); | |
| 1331 } | |
|
55
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1332 return "bug"; |
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1333 } |
| 0 | 1334 [(set_attr "length" "4,4") |
| 1335 (set_attr "cc" "set_n,clobber")]) | |
| 1336 | |
| 1337 (define_peephole2 ; andi | |
| 1338 [(set (match_operand:QI 0 "d_register_operand" "") | |
| 1339 (and:QI (match_dup 0) | |
| 1340 (match_operand:QI 1 "const_int_operand" ""))) | |
| 1341 (set (match_dup 0) | |
| 1342 (and:QI (match_dup 0) | |
| 1343 (match_operand:QI 2 "const_int_operand" "")))] | |
| 1344 "" | |
| 1345 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))] | |
| 1346 { | |
| 1347 operands[1] = GEN_INT (INTVAL (operands[1]) & INTVAL (operands[2])); | |
| 1348 }) | |
| 1349 | |
| 1350 ;;||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| | |
| 1351 ;; ior | |
| 1352 | |
| 1353 (define_insn "iorqi3" | |
| 1354 [(set (match_operand:QI 0 "register_operand" "=r,d") | |
| 1355 (ior:QI (match_operand:QI 1 "register_operand" "%0,0") | |
| 1356 (match_operand:QI 2 "nonmemory_operand" "r,i")))] | |
| 1357 "" | |
| 1358 "@ | |
| 1359 or %0,%2 | |
| 1360 ori %0,lo8(%2)" | |
| 1361 [(set_attr "length" "1,1") | |
| 1362 (set_attr "cc" "set_zn,set_zn")]) | |
| 1363 | |
| 1364 (define_insn "iorhi3" | |
| 1365 [(set (match_operand:HI 0 "register_operand" "=r,d") | |
| 1366 (ior:HI (match_operand:HI 1 "register_operand" "%0,0") | |
| 1367 (match_operand:HI 2 "nonmemory_operand" "r,i")))] | |
| 1368 "" | |
|
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1369 { |
| 0 | 1370 if (which_alternative==0) |
|
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1371 return ("or %A0,%A2" CR_TAB |
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1372 "or %B0,%B2"); |
| 0 | 1373 if (GET_CODE (operands[2]) == CONST_INT) |
| 1374 { | |
| 1375 int mask = INTVAL (operands[2]); | |
| 1376 if (mask & 0xff) | |
| 1377 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands); | |
| 1378 if (mask & 0xff00) | |
| 1379 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands); | |
|
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1380 return ""; |
| 0 | 1381 } |
| 1382 return (AS2 (ori,%0,lo8(%2)) CR_TAB | |
| 1383 AS2 (ori,%B0,hi8(%2))); | |
|
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1384 } |
| 0 | 1385 [(set_attr "length" "2,2") |
| 1386 (set_attr "cc" "set_n,clobber")]) | |
| 1387 | |
| 1388 (define_insn "*iorhi3_clobber" | |
| 1389 [(set (match_operand:HI 0 "register_operand" "=r,r") | |
| 1390 (ior:HI (match_operand:HI 1 "register_operand" "%0,0") | |
| 1391 (match_operand:HI 2 "immediate_operand" "M,i"))) | |
| 1392 (clobber (match_scratch:QI 3 "=&d,&d"))] | |
| 1393 "" | |
| 1394 "@ | |
| 1395 ldi %3,lo8(%2)\;or %A0,%3 | |
| 1396 ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3" | |
| 1397 [(set_attr "length" "2,4") | |
| 1398 (set_attr "cc" "clobber,set_n")]) | |
| 1399 | |
| 1400 (define_insn "iorsi3" | |
| 1401 [(set (match_operand:SI 0 "register_operand" "=r,d") | |
| 1402 (ior:SI (match_operand:SI 1 "register_operand" "%0,0") | |
| 1403 (match_operand:SI 2 "nonmemory_operand" "r,i")))] | |
| 1404 "" | |
|
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1405 { |
| 0 | 1406 if (which_alternative==0) |
|
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1407 return ("or %0,%2" CR_TAB |
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1408 "or %B0,%B2" CR_TAB |
|
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1409 "or %C0,%C2" CR_TAB |
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1410 "or %D0,%D2"); |
| 0 | 1411 if (GET_CODE (operands[2]) == CONST_INT) |
| 1412 { | |
| 1413 HOST_WIDE_INT mask = INTVAL (operands[2]); | |
| 1414 if (mask & 0xff) | |
| 1415 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands); | |
| 1416 if (mask & 0xff00) | |
| 1417 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands); | |
| 1418 if (mask & 0xff0000L) | |
| 1419 output_asm_insn (AS2 (ori,%C0,hlo8(%2)), operands); | |
| 1420 if (mask & 0xff000000L) | |
| 1421 output_asm_insn (AS2 (ori,%D0,hhi8(%2)), operands); | |
|
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1422 return ""; |
| 0 | 1423 } |
| 1424 return (AS2 (ori, %A0,lo8(%2)) CR_TAB | |
| 1425 AS2 (ori, %B0,hi8(%2)) CR_TAB | |
| 1426 AS2 (ori, %C0,hlo8(%2)) CR_TAB | |
| 1427 AS2 (ori, %D0,hhi8(%2))); | |
|
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|
1428 } |
| 0 | 1429 [(set_attr "length" "4,4") |
| 1430 (set_attr "cc" "set_n,clobber")]) | |
| 1431 | |
| 1432 (define_insn "*iorsi3_clobber" | |
| 1433 [(set (match_operand:SI 0 "register_operand" "=r,r") | |
| 1434 (ior:SI (match_operand:SI 1 "register_operand" "%0,0") | |
| 1435 (match_operand:SI 2 "immediate_operand" "M,i"))) | |
| 1436 (clobber (match_scratch:QI 3 "=&d,&d"))] | |
| 1437 "" | |
| 1438 "@ | |
| 1439 ldi %3,lo8(%2)\;or %A0,%3 | |
| 1440 ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3\;ldi %3,hlo8(%2)\;or %C0,%3\;ldi %3,hhi8(%2)\;or %D0,%3" | |
| 1441 [(set_attr "length" "2,8") | |
| 1442 (set_attr "cc" "clobber,set_n")]) | |
| 1443 | |
| 1444 ;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | |
| 1445 ;; xor | |
| 1446 | |
| 1447 (define_insn "xorqi3" | |
| 1448 [(set (match_operand:QI 0 "register_operand" "=r") | |
| 1449 (xor:QI (match_operand:QI 1 "register_operand" "%0") | |
| 1450 (match_operand:QI 2 "register_operand" "r")))] | |
| 1451 "" | |
| 1452 "eor %0,%2" | |
| 1453 [(set_attr "length" "1") | |
| 1454 (set_attr "cc" "set_zn")]) | |
| 1455 | |
| 1456 (define_insn "xorhi3" | |
| 1457 [(set (match_operand:HI 0 "register_operand" "=r") | |
| 1458 (xor:HI (match_operand:HI 1 "register_operand" "%0") | |
| 1459 (match_operand:HI 2 "register_operand" "r")))] | |
| 1460 "" | |
| 1461 "eor %0,%2 | |
| 1462 eor %B0,%B2" | |
| 1463 [(set_attr "length" "2") | |
| 1464 (set_attr "cc" "set_n")]) | |
| 1465 | |
| 1466 (define_insn "xorsi3" | |
| 1467 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1468 (xor:SI (match_operand:SI 1 "register_operand" "%0") | |
| 1469 (match_operand:SI 2 "register_operand" "r")))] | |
| 1470 "" | |
| 1471 "eor %0,%2 | |
| 1472 eor %B0,%B2 | |
| 1473 eor %C0,%C2 | |
| 1474 eor %D0,%D2" | |
| 1475 [(set_attr "length" "4") | |
| 1476 (set_attr "cc" "set_n")]) | |
| 1477 | |
| 1478 ;; swap swap swap swap swap swap swap swap swap swap swap swap swap swap swap | |
| 1479 ;; swap | |
| 1480 | |
| 1481 (define_expand "rotlqi3" | |
| 1482 [(set (match_operand:QI 0 "register_operand" "") | |
| 1483 (rotate:QI (match_operand:QI 1 "register_operand" "") | |
| 1484 (match_operand:QI 2 "const_int_operand" "")))] | |
| 1485 "" | |
| 1486 " | |
| 1487 { | |
| 1488 if (INTVAL (operands[2]) != 4) | |
| 1489 FAIL; | |
| 1490 }") | |
| 1491 | |
| 1492 (define_insn "*rotlqi3_4" | |
| 1493 [(set (match_operand:QI 0 "register_operand" "=r") | |
| 1494 (rotate:QI (match_operand:QI 1 "register_operand" "0") | |
| 1495 (const_int 4)))] | |
| 1496 "" | |
| 1497 "swap %0" | |
| 1498 [(set_attr "length" "1") | |
| 1499 (set_attr "cc" "none")]) | |
| 1500 | |
| 1501 (define_expand "rotlhi3" | |
| 1502 [(set (match_operand:HI 0 "register_operand" "") | |
| 1503 (rotate:HI (match_operand:HI 1 "register_operand" "") | |
| 1504 (match_operand:HI 2 "const_int_operand" "")))] | |
| 1505 "" | |
| 1506 " | |
| 1507 { | |
| 1508 if (INTVAL (operands[2]) != 8) | |
| 1509 FAIL; | |
| 1510 }") | |
| 1511 | |
| 1512 (define_insn_and_split "*rotlhi3_8" | |
| 1513 [(set (match_operand:HI 0 "register_operand" "=r") | |
| 1514 (rotate:HI (match_operand:HI 1 "register_operand" "r") | |
| 1515 (const_int 8)))] | |
| 1516 "" | |
| 1517 "mov __tmp_reg__,%A0 | |
| 1518 mov %A0,%B0 | |
| 1519 mov %B0, __tmp_reg__" | |
| 1520 "reload_completed | |
| 1521 && REGNO (operands[0]) != REGNO (operands[1])" | |
| 1522 [(set (match_dup 2) (match_dup 5)) | |
| 1523 (set (match_dup 3) (match_dup 4))] | |
| 1524 "operands[2] = gen_lowpart (QImode, operands[0]); | |
| 1525 operands[3] = gen_highpart (QImode, operands[0]); | |
| 1526 | |
| 1527 operands[4] = gen_lowpart (QImode, operands[1]); | |
| 1528 operands[5] = gen_highpart (QImode, operands[1]);" | |
| 1529 [(set_attr "length" "3") | |
| 1530 (set_attr "cc" "none")]) | |
| 1531 | |
| 1532 (define_expand "rotlsi3" | |
| 1533 [(set (match_operand:SI 0 "register_operand" "") | |
| 1534 (rotate:SI (match_operand:SI 1 "register_operand" "") | |
| 1535 (match_operand:SI 2 "const_int_operand" "")))] | |
| 1536 "" | |
| 1537 " | |
| 1538 { | |
| 1539 if (INTVAL (operands[2]) != 8 | |
| 1540 || INTVAL (operands[2]) != 16 | |
| 1541 || INTVAL (operands[2]) != 24) | |
| 1542 FAIL; | |
| 1543 }") | |
| 1544 | |
| 1545 (define_insn_and_split "*rotlsi3_16" | |
| 1546 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1547 (rotate:SI (match_operand:SI 1 "register_operand" "r") | |
| 1548 (const_int 16)))] | |
| 1549 "" | |
| 1550 "{mov __tmp_reg__,%A1\;mov %A0,%C1\;mov %C0, __tmp_reg__\;mov __tmp_reg__,%B1\;mov %B0,%D1\;mov %D0, __tmp_reg__|movw __tmp_reg__,%A1\;movw %A0,%C1\;movw %C0, __tmp_reg__\;clr __zero_reg__}" | |
| 1551 "reload_completed | |
| 1552 && REGNO (operands[0]) != REGNO (operands[1])" | |
| 1553 [(set (match_dup 2) (match_dup 5)) | |
| 1554 (set (match_dup 3) (match_dup 4))] | |
| 1555 "unsigned int si_lo_off = subreg_lowpart_offset (HImode, SImode); | |
| 1556 unsigned int si_hi_off = subreg_highpart_offset (HImode, SImode); | |
| 1557 | |
| 1558 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, si_lo_off); | |
| 1559 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, si_hi_off); | |
| 1560 | |
| 1561 operands[4] = simplify_gen_subreg (HImode, operands[1], SImode, si_lo_off); | |
| 1562 operands[5] = simplify_gen_subreg (HImode, operands[1], SImode, si_hi_off); | |
| 1563 | |
| 1564 if (REGNO (operands[0]) == REGNO(operands[1]) + 2) | |
| 1565 { | |
| 1566 emit_move_insn (operands[3], operands[4]); | |
| 1567 DONE; | |
| 1568 } | |
| 1569 else if (REGNO (operands[0]) == REGNO(operands[1]) - 2) | |
| 1570 { | |
| 1571 emit_move_insn (operands[2], operands[5]); | |
| 1572 DONE; | |
| 1573 }" | |
| 1574 [(set (attr "length") (if_then_else (eq_attr "mcu_have_movw" "yes") | |
| 1575 (const_int 4) | |
| 1576 (const_int 6))) | |
| 1577 (set (attr "cc") (if_then_else (eq_attr "mcu_have_movw" "yes") | |
| 1578 (const_string "clobber") | |
| 1579 (const_string "none")))]) | |
| 1580 | |
| 1581 (define_insn_and_split "*rotlsi3_8" | |
| 1582 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1583 (rotate:SI (match_operand:SI 1 "register_operand" "r") | |
| 1584 (const_int 8)))] | |
| 1585 "" | |
| 1586 "mov __tmp_reg__,%D1 | |
| 1587 mov %D0,%C1 | |
| 1588 mov %C0,%B1 | |
| 1589 mov %B0,%A1 | |
| 1590 mov %A0, __tmp_reg__" | |
| 1591 "reload_completed | |
| 1592 && REGNO (operands[0]) != REGNO (operands[1])" | |
| 1593 [(const_int 0)] | |
| 1594 "unsigned int si_lo_off = subreg_lowpart_offset (HImode, SImode); | |
| 1595 unsigned int si_hi_off = subreg_highpart_offset (HImode, SImode); | |
| 1596 unsigned int hi_lo_off = subreg_lowpart_offset (QImode, HImode); | |
| 1597 unsigned int hi_hi_off = subreg_highpart_offset (QImode, HImode); | |
| 1598 | |
| 1599 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, si_lo_off); | |
| 1600 operands[4] = simplify_gen_subreg (HImode, operands[0], SImode, si_hi_off); | |
| 1601 operands[3] = simplify_gen_subreg (QImode, operands[2], HImode, hi_hi_off); | |
| 1602 operands[2] = simplify_gen_subreg (QImode, operands[2], HImode, hi_lo_off); | |
| 1603 operands[5] = simplify_gen_subreg (QImode, operands[4], HImode, hi_hi_off); | |
| 1604 operands[4] = simplify_gen_subreg (QImode, operands[4], HImode, hi_lo_off); | |
| 1605 | |
| 1606 operands[6] = simplify_gen_subreg (HImode, operands[1], SImode, si_lo_off); | |
| 1607 operands[8] = simplify_gen_subreg (HImode, operands[1], SImode, si_hi_off); | |
| 1608 operands[7] = simplify_gen_subreg (QImode, operands[6], HImode, hi_hi_off); | |
| 1609 operands[6] = simplify_gen_subreg (QImode, operands[6], HImode, hi_lo_off); | |
| 1610 operands[9] = simplify_gen_subreg (QImode, operands[8], HImode, hi_hi_off); | |
| 1611 operands[8] = simplify_gen_subreg (QImode, operands[8], HImode, hi_lo_off); | |
| 1612 | |
| 1613 if (REGNO (operands[0]) < REGNO(operands[1])) | |
| 1614 { | |
| 1615 emit_move_insn (operands[2], operands[9]); | |
| 1616 emit_move_insn (operands[3], operands[6]); | |
| 1617 emit_move_insn (operands[4], operands[7]); | |
| 1618 emit_move_insn (operands[5], operands[8]); | |
| 1619 } | |
| 1620 else | |
| 1621 { | |
| 1622 emit_move_insn (operands[5], operands[8]); | |
| 1623 emit_move_insn (operands[2], operands[9]); | |
| 1624 emit_move_insn (operands[4], operands[7]); | |
| 1625 emit_move_insn (operands[3], operands[6]); | |
| 1626 } | |
| 1627 DONE;" | |
| 1628 [(set_attr "length" "5") | |
| 1629 (set_attr "cc" "none")]) | |
| 1630 | |
| 1631 (define_insn_and_split "*rotlsi3_24" | |
| 1632 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1633 (rotate:SI (match_operand:SI 1 "register_operand" "r") | |
| 1634 (const_int 24)))] | |
| 1635 "" | |
| 1636 "mov __tmp_reg__,%A1 | |
| 1637 mov %A0,%B1 | |
| 1638 mov %B0,%C1 | |
| 1639 mov %C0,%D1 | |
| 1640 mov %D0, __tmp_reg__" | |
| 1641 "reload_completed | |
| 1642 && REGNO (operands[0]) != REGNO (operands[1])" | |
| 1643 [(const_int 0)] | |
| 1644 "unsigned int si_lo_off = subreg_lowpart_offset (HImode, SImode); | |
| 1645 unsigned int si_hi_off = subreg_highpart_offset (HImode, SImode); | |
| 1646 unsigned int hi_lo_off = subreg_lowpart_offset (QImode, HImode); | |
| 1647 unsigned int hi_hi_off = subreg_highpart_offset (QImode, HImode); | |
| 1648 | |
| 1649 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, si_lo_off); | |
| 1650 operands[4] = simplify_gen_subreg (HImode, operands[0], SImode, si_hi_off); | |
| 1651 operands[3] = simplify_gen_subreg (QImode, operands[2], HImode, hi_hi_off); | |
| 1652 operands[2] = simplify_gen_subreg (QImode, operands[2], HImode, hi_lo_off); | |
| 1653 operands[5] = simplify_gen_subreg (QImode, operands[4], HImode, hi_hi_off); | |
| 1654 operands[4] = simplify_gen_subreg (QImode, operands[4], HImode, hi_lo_off); | |
| 1655 | |
| 1656 operands[6] = simplify_gen_subreg (HImode, operands[1], SImode, si_lo_off); | |
| 1657 operands[8] = simplify_gen_subreg (HImode, operands[1], SImode, si_hi_off); | |
| 1658 operands[7] = simplify_gen_subreg (QImode, operands[6], HImode, hi_hi_off); | |
| 1659 operands[6] = simplify_gen_subreg (QImode, operands[6], HImode, hi_lo_off); | |
| 1660 operands[9] = simplify_gen_subreg (QImode, operands[8], HImode, hi_hi_off); | |
| 1661 operands[8] = simplify_gen_subreg (QImode, operands[8], HImode, hi_lo_off); | |
| 1662 | |
| 1663 if (REGNO (operands[0]) < REGNO(operands[1])) | |
| 1664 { | |
| 1665 emit_move_insn (operands[2], operands[7]); | |
| 1666 emit_move_insn (operands[5], operands[6]); | |
| 1667 emit_move_insn (operands[3], operands[8]); | |
| 1668 emit_move_insn (operands[4], operands[9]); | |
| 1669 } | |
| 1670 else | |
| 1671 { | |
| 1672 emit_move_insn (operands[5], operands[6]); | |
| 1673 emit_move_insn (operands[4], operands[9]); | |
| 1674 emit_move_insn (operands[3], operands[8]); | |
| 1675 emit_move_insn (operands[2], operands[7]); | |
| 1676 } | |
| 1677 DONE;" | |
| 1678 [(set_attr "length" "5") | |
| 1679 (set_attr "cc" "none")]) | |
| 1680 | |
| 1681 ;;<< << << << << << << << << << << << << << << << << << << << << << << << << << | |
| 1682 ;; arithmetic shift left | |
| 1683 | |
| 1684 (define_expand "ashlqi3" | |
| 1685 [(set (match_operand:QI 0 "register_operand" "") | |
| 1686 (ashift:QI (match_operand:QI 1 "register_operand" "") | |
| 1687 (match_operand:QI 2 "general_operand" "")))] | |
| 1688 "" | |
| 1689 "") | |
| 1690 | |
| 1691 (define_split ; ashlqi3_const4 | |
| 1692 [(set (match_operand:QI 0 "d_register_operand" "") | |
| 1693 (ashift:QI (match_dup 0) | |
| 1694 (const_int 4)))] | |
| 1695 "" | |
| 1696 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4))) | |
| 1697 (set (match_dup 0) (and:QI (match_dup 0) (const_int -16)))] | |
| 1698 "") | |
| 1699 | |
| 1700 (define_split ; ashlqi3_const5 | |
| 1701 [(set (match_operand:QI 0 "d_register_operand" "") | |
| 1702 (ashift:QI (match_dup 0) | |
| 1703 (const_int 5)))] | |
| 1704 "" | |
| 1705 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4))) | |
| 1706 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1))) | |
| 1707 (set (match_dup 0) (and:QI (match_dup 0) (const_int -32)))] | |
| 1708 "") | |
| 1709 | |
| 1710 (define_split ; ashlqi3_const6 | |
| 1711 [(set (match_operand:QI 0 "d_register_operand" "") | |
| 1712 (ashift:QI (match_dup 0) | |
| 1713 (const_int 6)))] | |
| 1714 "" | |
| 1715 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4))) | |
| 1716 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2))) | |
| 1717 (set (match_dup 0) (and:QI (match_dup 0) (const_int -64)))] | |
| 1718 "") | |
| 1719 | |
| 1720 (define_insn "*ashlqi3" | |
| 1721 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r") | |
| 1722 (ashift:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0") | |
| 1723 (match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))] | |
| 1724 "" | |
| 1725 "* return ashlqi3_out (insn, operands, NULL);" | |
| 1726 [(set_attr "length" "5,0,1,2,4,6,9") | |
| 1727 (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")]) | |
| 1728 | |
| 1729 (define_insn "ashlhi3" | |
| 1730 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r") | |
| 1731 (ashift:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0") | |
| 1732 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))] | |
| 1733 "" | |
| 1734 "* return ashlhi3_out (insn, operands, NULL);" | |
| 1735 [(set_attr "length" "6,0,2,2,4,10,10") | |
| 1736 (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")]) | |
| 1737 | |
| 1738 (define_insn "ashlsi3" | |
| 1739 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r") | |
| 1740 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0") | |
| 1741 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))] | |
| 1742 "" | |
| 1743 "* return ashlsi3_out (insn, operands, NULL);" | |
| 1744 [(set_attr "length" "8,0,4,4,8,10,12") | |
| 1745 (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")]) | |
| 1746 | |
| 1747 ;; Optimize if a scratch register from LD_REGS happens to be available. | |
| 1748 | |
| 1749 (define_peephole2 ; ashlqi3_l_const4 | |
| 1750 [(set (match_operand:QI 0 "l_register_operand" "") | |
| 1751 (ashift:QI (match_dup 0) | |
| 1752 (const_int 4))) | |
| 1753 (match_scratch:QI 1 "d")] | |
| 1754 "" | |
| 1755 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4))) | |
| 1756 (set (match_dup 1) (const_int -16)) | |
| 1757 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))] | |
| 1758 "") | |
| 1759 | |
| 1760 (define_peephole2 ; ashlqi3_l_const5 | |
| 1761 [(set (match_operand:QI 0 "l_register_operand" "") | |
| 1762 (ashift:QI (match_dup 0) | |
| 1763 (const_int 5))) | |
| 1764 (match_scratch:QI 1 "d")] | |
| 1765 "" | |
| 1766 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4))) | |
| 1767 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1))) | |
| 1768 (set (match_dup 1) (const_int -32)) | |
| 1769 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))] | |
| 1770 "") | |
| 1771 | |
| 1772 (define_peephole2 ; ashlqi3_l_const6 | |
| 1773 [(set (match_operand:QI 0 "l_register_operand" "") | |
| 1774 (ashift:QI (match_dup 0) | |
| 1775 (const_int 6))) | |
| 1776 (match_scratch:QI 1 "d")] | |
| 1777 "" | |
| 1778 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4))) | |
| 1779 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2))) | |
| 1780 (set (match_dup 1) (const_int -64)) | |
| 1781 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))] | |
| 1782 "") | |
| 1783 | |
| 1784 (define_peephole2 | |
| 1785 [(match_scratch:QI 3 "d") | |
| 1786 (set (match_operand:HI 0 "register_operand" "") | |
| 1787 (ashift:HI (match_operand:HI 1 "register_operand" "") | |
| 1788 (match_operand:QI 2 "const_int_operand" "")))] | |
| 1789 "" | |
| 1790 [(parallel [(set (match_dup 0) (ashift:HI (match_dup 1) (match_dup 2))) | |
| 1791 (clobber (match_dup 3))])] | |
| 1792 "") | |
| 1793 | |
| 1794 (define_insn "*ashlhi3_const" | |
| 1795 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r") | |
| 1796 (ashift:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0") | |
| 1797 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n"))) | |
| 1798 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))] | |
| 1799 "reload_completed" | |
| 1800 "* return ashlhi3_out (insn, operands, NULL);" | |
| 1801 [(set_attr "length" "0,2,2,4,10") | |
| 1802 (set_attr "cc" "none,set_n,clobber,set_n,clobber")]) | |
| 1803 | |
| 1804 (define_peephole2 | |
| 1805 [(match_scratch:QI 3 "d") | |
| 1806 (set (match_operand:SI 0 "register_operand" "") | |
| 1807 (ashift:SI (match_operand:SI 1 "register_operand" "") | |
| 1808 (match_operand:QI 2 "const_int_operand" "")))] | |
| 1809 "" | |
| 1810 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2))) | |
| 1811 (clobber (match_dup 3))])] | |
| 1812 "") | |
| 1813 | |
| 1814 (define_insn "*ashlsi3_const" | |
| 1815 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") | |
| 1816 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r,0") | |
| 1817 (match_operand:QI 2 "const_int_operand" "L,P,O,n"))) | |
| 1818 (clobber (match_scratch:QI 3 "=X,X,X,&d"))] | |
| 1819 "reload_completed" | |
| 1820 "* return ashlsi3_out (insn, operands, NULL);" | |
| 1821 [(set_attr "length" "0,4,4,10") | |
| 1822 (set_attr "cc" "none,set_n,clobber,clobber")]) | |
| 1823 | |
| 1824 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> | |
| 1825 ;; arithmetic shift right | |
| 1826 | |
| 1827 (define_insn "ashrqi3" | |
| 1828 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r") | |
| 1829 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0") | |
| 1830 (match_operand:QI 2 "general_operand" "r,L,P,K,n,Qm")))] | |
| 1831 "" | |
| 1832 "* return ashrqi3_out (insn, operands, NULL);" | |
| 1833 [(set_attr "length" "5,0,1,2,5,9") | |
| 1834 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber")]) | |
| 1835 | |
| 1836 (define_insn "ashrhi3" | |
| 1837 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r") | |
| 1838 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0") | |
| 1839 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))] | |
| 1840 "" | |
| 1841 "* return ashrhi3_out (insn, operands, NULL);" | |
| 1842 [(set_attr "length" "6,0,2,4,4,10,10") | |
| 1843 (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")]) | |
| 1844 | |
| 1845 (define_insn "ashrsi3" | |
| 1846 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r") | |
| 1847 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0") | |
| 1848 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))] | |
| 1849 "" | |
| 1850 "* return ashrsi3_out (insn, operands, NULL);" | |
| 1851 [(set_attr "length" "8,0,4,6,8,10,12") | |
| 1852 (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")]) | |
| 1853 | |
| 1854 ;; Optimize if a scratch register from LD_REGS happens to be available. | |
| 1855 | |
| 1856 (define_peephole2 | |
| 1857 [(match_scratch:QI 3 "d") | |
| 1858 (set (match_operand:HI 0 "register_operand" "") | |
| 1859 (ashiftrt:HI (match_operand:HI 1 "register_operand" "") | |
| 1860 (match_operand:QI 2 "const_int_operand" "")))] | |
| 1861 "" | |
| 1862 [(parallel [(set (match_dup 0) (ashiftrt:HI (match_dup 1) (match_dup 2))) | |
| 1863 (clobber (match_dup 3))])] | |
| 1864 "") | |
| 1865 | |
| 1866 (define_insn "*ashrhi3_const" | |
| 1867 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r") | |
| 1868 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0") | |
| 1869 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n"))) | |
| 1870 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))] | |
| 1871 "reload_completed" | |
| 1872 "* return ashrhi3_out (insn, operands, NULL);" | |
| 1873 [(set_attr "length" "0,2,4,4,10") | |
| 1874 (set_attr "cc" "none,clobber,set_n,clobber,clobber")]) | |
| 1875 | |
| 1876 (define_peephole2 | |
| 1877 [(match_scratch:QI 3 "d") | |
| 1878 (set (match_operand:SI 0 "register_operand" "") | |
| 1879 (ashiftrt:SI (match_operand:SI 1 "register_operand" "") | |
| 1880 (match_operand:QI 2 "const_int_operand" "")))] | |
| 1881 "" | |
| 1882 [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
| 1883 (clobber (match_dup 3))])] | |
| 1884 "") | |
| 1885 | |
| 1886 (define_insn "*ashrsi3_const" | |
| 1887 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") | |
| 1888 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0") | |
| 1889 (match_operand:QI 2 "const_int_operand" "L,P,O,n"))) | |
| 1890 (clobber (match_scratch:QI 3 "=X,X,X,&d"))] | |
| 1891 "reload_completed" | |
| 1892 "* return ashrsi3_out (insn, operands, NULL);" | |
| 1893 [(set_attr "length" "0,4,4,10") | |
| 1894 (set_attr "cc" "none,clobber,set_n,clobber")]) | |
| 1895 | |
| 1896 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> | |
| 1897 ;; logical shift right | |
| 1898 | |
| 1899 (define_expand "lshrqi3" | |
| 1900 [(set (match_operand:QI 0 "register_operand" "") | |
| 1901 (lshiftrt:QI (match_operand:QI 1 "register_operand" "") | |
| 1902 (match_operand:QI 2 "general_operand" "")))] | |
| 1903 "" | |
| 1904 "") | |
| 1905 | |
| 1906 (define_split ; lshrqi3_const4 | |
| 1907 [(set (match_operand:QI 0 "d_register_operand" "") | |
| 1908 (lshiftrt:QI (match_dup 0) | |
| 1909 (const_int 4)))] | |
| 1910 "" | |
| 1911 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4))) | |
| 1912 (set (match_dup 0) (and:QI (match_dup 0) (const_int 15)))] | |
| 1913 "") | |
| 1914 | |
| 1915 (define_split ; lshrqi3_const5 | |
| 1916 [(set (match_operand:QI 0 "d_register_operand" "") | |
| 1917 (lshiftrt:QI (match_dup 0) | |
| 1918 (const_int 5)))] | |
| 1919 "" | |
| 1920 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4))) | |
| 1921 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1))) | |
| 1922 (set (match_dup 0) (and:QI (match_dup 0) (const_int 7)))] | |
| 1923 "") | |
| 1924 | |
| 1925 (define_split ; lshrqi3_const6 | |
| 1926 [(set (match_operand:QI 0 "d_register_operand" "") | |
| 1927 (lshiftrt:QI (match_dup 0) | |
| 1928 (const_int 6)))] | |
| 1929 "" | |
| 1930 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4))) | |
| 1931 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2))) | |
| 1932 (set (match_dup 0) (and:QI (match_dup 0) (const_int 3)))] | |
| 1933 "") | |
| 1934 | |
| 1935 (define_insn "*lshrqi3" | |
| 1936 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r") | |
| 1937 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0") | |
| 1938 (match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))] | |
| 1939 "" | |
| 1940 "* return lshrqi3_out (insn, operands, NULL);" | |
| 1941 [(set_attr "length" "5,0,1,2,4,6,9") | |
| 1942 (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")]) | |
| 1943 | |
| 1944 (define_insn "lshrhi3" | |
| 1945 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r") | |
| 1946 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0") | |
| 1947 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))] | |
| 1948 "" | |
| 1949 "* return lshrhi3_out (insn, operands, NULL);" | |
| 1950 [(set_attr "length" "6,0,2,2,4,10,10") | |
| 1951 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")]) | |
| 1952 | |
| 1953 (define_insn "lshrsi3" | |
| 1954 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r") | |
| 1955 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0") | |
| 1956 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))] | |
| 1957 "" | |
| 1958 "* return lshrsi3_out (insn, operands, NULL);" | |
| 1959 [(set_attr "length" "8,0,4,4,8,10,12") | |
| 1960 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")]) | |
| 1961 | |
| 1962 ;; Optimize if a scratch register from LD_REGS happens to be available. | |
| 1963 | |
| 1964 (define_peephole2 ; lshrqi3_l_const4 | |
| 1965 [(set (match_operand:QI 0 "l_register_operand" "") | |
| 1966 (lshiftrt:QI (match_dup 0) | |
| 1967 (const_int 4))) | |
| 1968 (match_scratch:QI 1 "d")] | |
| 1969 "" | |
| 1970 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4))) | |
| 1971 (set (match_dup 1) (const_int 15)) | |
| 1972 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))] | |
| 1973 "") | |
| 1974 | |
| 1975 (define_peephole2 ; lshrqi3_l_const5 | |
| 1976 [(set (match_operand:QI 0 "l_register_operand" "") | |
| 1977 (lshiftrt:QI (match_dup 0) | |
| 1978 (const_int 5))) | |
| 1979 (match_scratch:QI 1 "d")] | |
| 1980 "" | |
| 1981 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4))) | |
| 1982 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1))) | |
| 1983 (set (match_dup 1) (const_int 7)) | |
| 1984 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))] | |
| 1985 "") | |
| 1986 | |
| 1987 (define_peephole2 ; lshrqi3_l_const6 | |
| 1988 [(set (match_operand:QI 0 "l_register_operand" "") | |
| 1989 (lshiftrt:QI (match_dup 0) | |
| 1990 (const_int 6))) | |
| 1991 (match_scratch:QI 1 "d")] | |
| 1992 "" | |
| 1993 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4))) | |
| 1994 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2))) | |
| 1995 (set (match_dup 1) (const_int 3)) | |
| 1996 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))] | |
| 1997 "") | |
| 1998 | |
| 1999 (define_peephole2 | |
| 2000 [(match_scratch:QI 3 "d") | |
| 2001 (set (match_operand:HI 0 "register_operand" "") | |
| 2002 (lshiftrt:HI (match_operand:HI 1 "register_operand" "") | |
| 2003 (match_operand:QI 2 "const_int_operand" "")))] | |
| 2004 "" | |
| 2005 [(parallel [(set (match_dup 0) (lshiftrt:HI (match_dup 1) (match_dup 2))) | |
| 2006 (clobber (match_dup 3))])] | |
| 2007 "") | |
| 2008 | |
| 2009 (define_insn "*lshrhi3_const" | |
| 2010 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r") | |
| 2011 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0") | |
| 2012 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n"))) | |
| 2013 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))] | |
| 2014 "reload_completed" | |
| 2015 "* return lshrhi3_out (insn, operands, NULL);" | |
| 2016 [(set_attr "length" "0,2,2,4,10") | |
| 2017 (set_attr "cc" "none,clobber,clobber,clobber,clobber")]) | |
| 2018 | |
| 2019 (define_peephole2 | |
| 2020 [(match_scratch:QI 3 "d") | |
| 2021 (set (match_operand:SI 0 "register_operand" "") | |
| 2022 (lshiftrt:SI (match_operand:SI 1 "register_operand" "") | |
| 2023 (match_operand:QI 2 "const_int_operand" "")))] | |
| 2024 "" | |
| 2025 [(parallel [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
| 2026 (clobber (match_dup 3))])] | |
| 2027 "") | |
| 2028 | |
| 2029 (define_insn "*lshrsi3_const" | |
| 2030 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") | |
| 2031 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0") | |
| 2032 (match_operand:QI 2 "const_int_operand" "L,P,O,n"))) | |
| 2033 (clobber (match_scratch:QI 3 "=X,X,X,&d"))] | |
| 2034 "reload_completed" | |
| 2035 "* return lshrsi3_out (insn, operands, NULL);" | |
| 2036 [(set_attr "length" "0,4,4,10") | |
| 2037 (set_attr "cc" "none,clobber,clobber,clobber")]) | |
| 2038 | |
| 2039 ;; abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) | |
| 2040 ;; abs | |
| 2041 | |
| 2042 (define_insn "absqi2" | |
| 2043 [(set (match_operand:QI 0 "register_operand" "=r") | |
| 2044 (abs:QI (match_operand:QI 1 "register_operand" "0")))] | |
| 2045 "" | |
| 2046 "sbrc %0,7 | |
| 2047 neg %0" | |
| 2048 [(set_attr "length" "2") | |
| 2049 (set_attr "cc" "clobber")]) | |
| 2050 | |
| 2051 | |
| 2052 (define_insn "abssf2" | |
| 2053 [(set (match_operand:SF 0 "register_operand" "=d,r") | |
| 2054 (abs:SF (match_operand:SF 1 "register_operand" "0,0")))] | |
| 2055 "" | |
| 2056 "@ | |
| 2057 andi %D0,0x7f | |
| 2058 clt\;bld %D0,7" | |
| 2059 [(set_attr "length" "1,2") | |
| 2060 (set_attr "cc" "set_n,clobber")]) | |
| 2061 | |
| 2062 ;; 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x | |
| 2063 ;; neg | |
| 2064 | |
| 2065 (define_insn "negqi2" | |
| 2066 [(set (match_operand:QI 0 "register_operand" "=r") | |
| 2067 (neg:QI (match_operand:QI 1 "register_operand" "0")))] | |
| 2068 "" | |
| 2069 "neg %0" | |
| 2070 [(set_attr "length" "1") | |
| 2071 (set_attr "cc" "set_zn")]) | |
| 2072 | |
| 2073 (define_insn "neghi2" | |
| 2074 [(set (match_operand:HI 0 "register_operand" "=!d,r,&r") | |
| 2075 (neg:HI (match_operand:HI 1 "register_operand" "0,0,r")))] | |
| 2076 "" | |
| 2077 "@ | |
| 2078 com %B0\;neg %A0\;sbci %B0,lo8(-1) | |
| 2079 com %B0\;neg %A0\;sbc %B0,__zero_reg__\;inc %B0 | |
| 2080 clr %A0\;clr %B0\;sub %A0,%A1\;sbc %B0,%B1" | |
| 2081 [(set_attr "length" "3,4,4") | |
| 2082 (set_attr "cc" "set_czn,set_n,set_czn")]) | |
| 2083 | |
| 2084 (define_insn "negsi2" | |
| 2085 [(set (match_operand:SI 0 "register_operand" "=!d,r,&r") | |
| 2086 (neg:SI (match_operand:SI 1 "register_operand" "0,0,r")))] | |
| 2087 "" | |
| 2088 "@ | |
| 2089 com %D0\;com %C0\;com %B0\;neg %A0\;sbci %B0,lo8(-1)\;sbci %C0,lo8(-1)\;sbci %D0,lo8(-1) | |
| 2090 com %D0\;com %C0\;com %B0\;com %A0\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__ | |
| 2091 clr %A0\;clr %B0\;{clr %C0\;clr %D0|movw %C0,%A0}\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1\;sbc %D0,%D1" | |
| 2092 [(set_attr_alternative "length" | |
| 2093 [(const_int 7) | |
| 2094 (const_int 8) | |
| 2095 (if_then_else (eq_attr "mcu_have_movw" "yes") | |
| 2096 (const_int 7) | |
| 2097 (const_int 8))]) | |
| 2098 (set_attr "cc" "set_czn,set_n,set_czn")]) | |
| 2099 | |
| 2100 (define_insn "negsf2" | |
| 2101 [(set (match_operand:SF 0 "register_operand" "=d,r") | |
| 2102 (neg:SF (match_operand:SF 1 "register_operand" "0,0")))] | |
| 2103 "" | |
| 2104 "@ | |
| 2105 subi %D0,0x80 | |
| 2106 bst %D0,7\;com %D0\;bld %D0,7\;com %D0" | |
| 2107 [(set_attr "length" "1,4") | |
| 2108 (set_attr "cc" "set_n,set_n")]) | |
| 2109 | |
| 2110 ;; !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! | |
| 2111 ;; not | |
| 2112 | |
| 2113 (define_insn "one_cmplqi2" | |
| 2114 [(set (match_operand:QI 0 "register_operand" "=r") | |
| 2115 (not:QI (match_operand:QI 1 "register_operand" "0")))] | |
| 2116 "" | |
| 2117 "com %0" | |
| 2118 [(set_attr "length" "1") | |
| 2119 (set_attr "cc" "set_czn")]) | |
| 2120 | |
| 2121 (define_insn "one_cmplhi2" | |
| 2122 [(set (match_operand:HI 0 "register_operand" "=r") | |
| 2123 (not:HI (match_operand:HI 1 "register_operand" "0")))] | |
| 2124 "" | |
| 2125 "com %0 | |
| 2126 com %B0" | |
| 2127 [(set_attr "length" "2") | |
| 2128 (set_attr "cc" "set_n")]) | |
| 2129 | |
| 2130 (define_insn "one_cmplsi2" | |
| 2131 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 2132 (not:SI (match_operand:SI 1 "register_operand" "0")))] | |
| 2133 "" | |
| 2134 "com %0 | |
| 2135 com %B0 | |
| 2136 com %C0 | |
| 2137 com %D0" | |
| 2138 [(set_attr "length" "4") | |
| 2139 (set_attr "cc" "set_n")]) | |
| 2140 | |
| 2141 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x | |
| 2142 ;; sign extend | |
| 2143 | |
| 2144 (define_insn "extendqihi2" | |
| 2145 [(set (match_operand:HI 0 "register_operand" "=r,r") | |
| 2146 (sign_extend:HI (match_operand:QI 1 "register_operand" "0,*r")))] | |
| 2147 "" | |
| 2148 "@ | |
| 2149 clr %B0\;sbrc %0,7\;com %B0 | |
| 2150 mov %A0,%A1\;clr %B0\;sbrc %A0,7\;com %B0" | |
| 2151 [(set_attr "length" "3,4") | |
| 2152 (set_attr "cc" "set_n,set_n")]) | |
| 2153 | |
| 2154 (define_insn "extendqisi2" | |
| 2155 [(set (match_operand:SI 0 "register_operand" "=r,r") | |
| 2156 (sign_extend:SI (match_operand:QI 1 "register_operand" "0,*r")))] | |
| 2157 "" | |
| 2158 "@ | |
| 2159 clr %B0\;sbrc %A0,7\;com %B0\;mov %C0,%B0\;mov %D0,%B0 | |
| 2160 mov %A0,%A1\;clr %B0\;sbrc %A0,7\;com %B0\;mov %C0,%B0\;mov %D0,%B0" | |
| 2161 [(set_attr "length" "5,6") | |
| 2162 (set_attr "cc" "set_n,set_n")]) | |
| 2163 | |
| 2164 (define_insn "extendhisi2" | |
| 2165 [(set (match_operand:SI 0 "register_operand" "=r,&r") | |
| 2166 (sign_extend:SI (match_operand:HI 1 "register_operand" "0,*r")))] | |
| 2167 "" | |
| 2168 "@ | |
| 2169 clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0 | |
| 2170 {mov %A0,%A1\;mov %B0,%B1|movw %A0,%A1}\;clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0" | |
| 2171 [(set_attr_alternative "length" | |
| 2172 [(const_int 4) | |
| 2173 (if_then_else (eq_attr "mcu_have_movw" "yes") | |
| 2174 (const_int 5) | |
| 2175 (const_int 6))]) | |
| 2176 (set_attr "cc" "set_n,set_n")]) | |
| 2177 | |
| 2178 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x | |
| 2179 ;; zero extend | |
| 2180 | |
| 2181 (define_insn_and_split "zero_extendqihi2" | |
| 2182 [(set (match_operand:HI 0 "register_operand" "=r") | |
| 2183 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))] | |
| 2184 "" | |
| 2185 "#" | |
| 2186 "reload_completed" | |
| 2187 [(set (match_dup 2) (match_dup 1)) | |
| 2188 (set (match_dup 3) (const_int 0))] | |
| 2189 "unsigned int low_off = subreg_lowpart_offset (QImode, HImode); | |
| 2190 unsigned int high_off = subreg_highpart_offset (QImode, HImode); | |
| 2191 | |
| 2192 operands[2] = simplify_gen_subreg (QImode, operands[0], HImode, low_off); | |
| 2193 operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, high_off); | |
| 2194 ") | |
| 2195 | |
| 2196 (define_insn_and_split "zero_extendqisi2" | |
| 2197 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 2198 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))] | |
| 2199 "" | |
| 2200 "#" | |
| 2201 "reload_completed" | |
| 2202 [(set (match_dup 2) (zero_extend:HI (match_dup 1))) | |
| 2203 (set (match_dup 3) (const_int 0))] | |
| 2204 "unsigned int low_off = subreg_lowpart_offset (HImode, SImode); | |
| 2205 unsigned int high_off = subreg_highpart_offset (HImode, SImode); | |
| 2206 | |
| 2207 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off); | |
| 2208 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off); | |
| 2209 ") | |
| 2210 | |
| 2211 (define_insn_and_split "zero_extendhisi2" | |
| 2212 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 2213 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))] | |
| 2214 "" | |
| 2215 "#" | |
| 2216 "reload_completed" | |
| 2217 [(set (match_dup 2) (match_dup 1)) | |
| 2218 (set (match_dup 3) (const_int 0))] | |
| 2219 "unsigned int low_off = subreg_lowpart_offset (HImode, SImode); | |
| 2220 unsigned int high_off = subreg_highpart_offset (HImode, SImode); | |
| 2221 | |
| 2222 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off); | |
| 2223 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off); | |
| 2224 ") | |
| 2225 | |
| 2226 (define_insn_and_split "zero_extendqidi2" | |
| 2227 [(set (match_operand:DI 0 "register_operand" "=r") | |
| 2228 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))] | |
| 2229 "" | |
| 2230 "#" | |
| 2231 "reload_completed" | |
| 2232 [(set (match_dup 2) (zero_extend:SI (match_dup 1))) | |
| 2233 (set (match_dup 3) (const_int 0))] | |
| 2234 "unsigned int low_off = subreg_lowpart_offset (SImode, DImode); | |
| 2235 unsigned int high_off = subreg_highpart_offset (SImode, DImode); | |
| 2236 | |
| 2237 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off); | |
| 2238 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off); | |
| 2239 ") | |
| 2240 | |
| 2241 (define_insn_and_split "zero_extendhidi2" | |
| 2242 [(set (match_operand:DI 0 "register_operand" "=r") | |
| 2243 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))] | |
| 2244 "" | |
| 2245 "#" | |
| 2246 "reload_completed" | |
| 2247 [(set (match_dup 2) (zero_extend:SI (match_dup 1))) | |
| 2248 (set (match_dup 3) (const_int 0))] | |
| 2249 "unsigned int low_off = subreg_lowpart_offset (SImode, DImode); | |
| 2250 unsigned int high_off = subreg_highpart_offset (SImode, DImode); | |
| 2251 | |
| 2252 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off); | |
| 2253 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off); | |
| 2254 ") | |
| 2255 | |
| 2256 (define_insn_and_split "zero_extendsidi2" | |
| 2257 [(set (match_operand:DI 0 "register_operand" "=r") | |
| 2258 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))] | |
| 2259 "" | |
| 2260 "#" | |
| 2261 "reload_completed" | |
| 2262 [(set (match_dup 2) (match_dup 1)) | |
| 2263 (set (match_dup 3) (const_int 0))] | |
| 2264 "unsigned int low_off = subreg_lowpart_offset (SImode, DImode); | |
| 2265 unsigned int high_off = subreg_highpart_offset (SImode, DImode); | |
| 2266 | |
| 2267 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off); | |
| 2268 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off); | |
| 2269 ") | |
| 2270 | |
| 2271 ;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=> | |
| 2272 ;; compare | |
| 2273 | |
|
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|
2274 ; Optimize negated tests into reverse compare if overflow is undefined. |
|
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|
2275 (define_insn "*negated_tstqi" |
| 0 | 2276 [(set (cc0) |
|
55
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|
2277 (compare (neg:QI (match_operand:QI 0 "register_operand" "r")) |
|
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|
2278 (const_int 0)))] |
|
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|
2279 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)" |
|
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|
2280 "cp __zero_reg__,%0" |
| 0 | 2281 [(set_attr "cc" "compare") |
| 2282 (set_attr "length" "1")]) | |
| 2283 | |
| 2284 (define_insn "*reversed_tstqi" | |
| 2285 [(set (cc0) | |
|
55
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|
2286 (compare (const_int 0) |
| 0 | 2287 (match_operand:QI 0 "register_operand" "r")))] |
| 2288 "" | |
| 2289 "cp __zero_reg__,%0" | |
|
55
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|
2290 [(set_attr "cc" "compare") |
|
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|
2291 (set_attr "length" "2")]) |
|
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|
2292 |
|
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|
2293 (define_insn "*negated_tsthi" |
| 0 | 2294 [(set (cc0) |
|
55
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|
2295 (compare (neg:HI (match_operand:HI 0 "register_operand" "r")) |
|
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|
2296 (const_int 0)))] |
|
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|
2297 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)" |
|
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|
2298 "cp __zero_reg__,%A0 |
|
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|
2299 cpc __zero_reg__,%B0" |
|
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|
2300 [(set_attr "cc" "compare") |
|
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|
2301 (set_attr "length" "2")]) |
|
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|
2302 |
|
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|
2303 ;; Leave here the clobber used by the cmphi pattern for simplicity, even |
|
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|
2304 ;; though it is unused, because this pattern is synthesized by avr_reorg. |
| 0 | 2305 (define_insn "*reversed_tsthi" |
| 2306 [(set (cc0) | |
| 2307 (compare (const_int 0) | |
|
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|
2308 (match_operand:HI 0 "register_operand" "r"))) |
|
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|
2309 (clobber (match_scratch:QI 1 "=X"))] |
| 0 | 2310 "" |
| 2311 "cp __zero_reg__,%A0 | |
| 2312 cpc __zero_reg__,%B0" | |
| 2313 [(set_attr "cc" "compare") | |
| 2314 (set_attr "length" "2")]) | |
| 2315 | |
|
55
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|
2316 (define_insn "*negated_tstsi" |
| 0 | 2317 [(set (cc0) |
|
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|
2318 (compare (neg:SI (match_operand:SI 0 "register_operand" "r")) |
|
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|
2319 (const_int 0)))] |
|
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|
2320 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)" |
|
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|
2321 "cp __zero_reg__,%A0 |
|
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|
2322 cpc __zero_reg__,%B0 |
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2323 cpc __zero_reg__,%C0 |
|
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|
2324 cpc __zero_reg__,%D0" |
| 0 | 2325 [(set_attr "cc" "compare") |
| 2326 (set_attr "length" "4")]) | |
| 2327 | |
| 2328 (define_insn "*reversed_tstsi" | |
| 2329 [(set (cc0) | |
|
55
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|
2330 (compare (const_int 0) |
|
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|
2331 (match_operand:SI 0 "register_operand" "r"))) |
|
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|
2332 (clobber (match_scratch:QI 1 "=X"))] |
| 0 | 2333 "" |
| 2334 "cp __zero_reg__,%A0 | |
| 2335 cpc __zero_reg__,%B0 | |
| 2336 cpc __zero_reg__,%C0 | |
| 2337 cpc __zero_reg__,%D0" | |
| 2338 [(set_attr "cc" "compare") | |
| 2339 (set_attr "length" "4")]) | |
| 2340 | |
| 2341 | |
|
55
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|
2342 (define_insn "*cmpqi" |
| 0 | 2343 [(set (cc0) |
|
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|
2344 (compare (match_operand:QI 0 "register_operand" "r,r,d") |
|
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|
2345 (match_operand:QI 1 "nonmemory_operand" "L,r,i")))] |
| 0 | 2346 "" |
| 2347 "@ | |
|
55
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|
2348 tst %0 |
| 0 | 2349 cp %0,%1 |
| 2350 cpi %0,lo8(%1)" | |
|
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|
2351 [(set_attr "cc" "compare,compare,compare") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2352 (set_attr "length" "1,1,1")]) |
| 0 | 2353 |
| 2354 (define_insn "*cmpqi_sign_extend" | |
| 2355 [(set (cc0) | |
| 2356 (compare (sign_extend:HI | |
| 2357 (match_operand:QI 0 "register_operand" "d")) | |
| 2358 (match_operand:HI 1 "const_int_operand" "n")))] | |
| 2359 "INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) <= 127" | |
| 2360 "cpi %0,lo8(%1)" | |
| 2361 [(set_attr "cc" "compare") | |
| 2362 (set_attr "length" "1")]) | |
| 2363 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2364 (define_insn "*cmphi" |
| 0 | 2365 [(set (cc0) |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2366 (compare (match_operand:HI 0 "register_operand" "!w,r,r,d,d,r,r") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2367 (match_operand:HI 1 "nonmemory_operand" "L,L,r,M,i,M,i"))) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2368 (clobber (match_scratch:QI 2 "=X,X,X,X,&d,&d,&d"))] |
| 0 | 2369 "" |
| 2370 "*{ | |
| 2371 switch (which_alternative) | |
| 2372 { | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2373 case 0: case 1: |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2374 return out_tsthi (insn, operands[0], NULL); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2375 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2376 case 2: |
| 0 | 2377 return (AS2 (cp,%A0,%A1) CR_TAB |
| 2378 AS2 (cpc,%B0,%B1)); | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2379 case 3: |
| 0 | 2380 if (reg_unused_after (insn, operands[0]) |
| 2381 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63 | |
| 2382 && test_hard_reg_class (ADDW_REGS, operands[0])) | |
| 2383 return AS2 (sbiw,%0,%1); | |
| 2384 else | |
| 2385 return (AS2 (cpi,%0,%1) CR_TAB | |
| 2386 AS2 (cpc,%B0,__zero_reg__)); | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2387 case 4: |
| 0 | 2388 if (reg_unused_after (insn, operands[0])) |
| 2389 return (AS2 (subi,%0,lo8(%1)) CR_TAB | |
| 2390 AS2 (sbci,%B0,hi8(%1))); | |
| 2391 else | |
| 2392 return (AS2 (ldi, %2,hi8(%1)) CR_TAB | |
| 2393 AS2 (cpi, %A0,lo8(%1)) CR_TAB | |
| 2394 AS2 (cpc, %B0,%2)); | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2395 case 5: |
| 0 | 2396 return (AS2 (ldi, %2,lo8(%1)) CR_TAB |
| 2397 AS2 (cp, %A0,%2) CR_TAB | |
| 2398 AS2 (cpc, %B0,__zero_reg__)); | |
| 2399 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2400 case 6: |
| 0 | 2401 return (AS2 (ldi, %2,lo8(%1)) CR_TAB |
| 2402 AS2 (cp, %A0,%2) CR_TAB | |
| 2403 AS2 (ldi, %2,hi8(%1)) CR_TAB | |
| 2404 AS2 (cpc, %B0,%2)); | |
| 2405 } | |
| 2406 return \"bug\"; | |
| 2407 }" | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2408 [(set_attr "cc" "compare,compare,compare,compare,compare,compare,compare") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2409 (set_attr "length" "1,2,2,2,3,3,4")]) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2410 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2411 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2412 (define_insn "*cmpsi" |
| 0 | 2413 [(set (cc0) |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2414 (compare (match_operand:SI 0 "register_operand" "r,r,d,d,r,r") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2415 (match_operand:SI 1 "nonmemory_operand" "L,r,M,i,M,i"))) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2416 (clobber (match_scratch:QI 2 "=X,X,X,&d,&d,&d"))] |
| 0 | 2417 "" |
| 2418 "*{ | |
| 2419 switch (which_alternative) | |
| 2420 { | |
| 2421 case 0: | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2422 return out_tstsi (insn, operands[0], NULL); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2423 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2424 case 1: |
| 0 | 2425 return (AS2 (cp,%A0,%A1) CR_TAB |
| 2426 AS2 (cpc,%B0,%B1) CR_TAB | |
| 2427 AS2 (cpc,%C0,%C1) CR_TAB | |
| 2428 AS2 (cpc,%D0,%D1)); | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2429 case 2: |
| 0 | 2430 if (reg_unused_after (insn, operands[0]) |
| 2431 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63 | |
| 2432 && test_hard_reg_class (ADDW_REGS, operands[0])) | |
| 2433 return (AS2 (sbiw,%0,%1) CR_TAB | |
| 2434 AS2 (cpc,%C0,__zero_reg__) CR_TAB | |
| 2435 AS2 (cpc,%D0,__zero_reg__)); | |
| 2436 else | |
| 2437 return (AS2 (cpi,%A0,lo8(%1)) CR_TAB | |
| 2438 AS2 (cpc,%B0,__zero_reg__) CR_TAB | |
| 2439 AS2 (cpc,%C0,__zero_reg__) CR_TAB | |
| 2440 AS2 (cpc,%D0,__zero_reg__)); | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2441 case 3: |
| 0 | 2442 if (reg_unused_after (insn, operands[0])) |
| 2443 return (AS2 (subi,%A0,lo8(%1)) CR_TAB | |
| 2444 AS2 (sbci,%B0,hi8(%1)) CR_TAB | |
| 2445 AS2 (sbci,%C0,hlo8(%1)) CR_TAB | |
| 2446 AS2 (sbci,%D0,hhi8(%1))); | |
| 2447 else | |
| 2448 return (AS2 (cpi, %A0,lo8(%1)) CR_TAB | |
| 2449 AS2 (ldi, %2,hi8(%1)) CR_TAB | |
| 2450 AS2 (cpc, %B0,%2) CR_TAB | |
| 2451 AS2 (ldi, %2,hlo8(%1)) CR_TAB | |
| 2452 AS2 (cpc, %C0,%2) CR_TAB | |
| 2453 AS2 (ldi, %2,hhi8(%1)) CR_TAB | |
| 2454 AS2 (cpc, %D0,%2)); | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2455 case 4: |
| 0 | 2456 return (AS2 (ldi,%2,lo8(%1)) CR_TAB |
| 2457 AS2 (cp,%A0,%2) CR_TAB | |
| 2458 AS2 (cpc,%B0,__zero_reg__) CR_TAB | |
| 2459 AS2 (cpc,%C0,__zero_reg__) CR_TAB | |
| 2460 AS2 (cpc,%D0,__zero_reg__)); | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2461 case 5: |
| 0 | 2462 return (AS2 (ldi, %2,lo8(%1)) CR_TAB |
| 2463 AS2 (cp, %A0,%2) CR_TAB | |
| 2464 AS2 (ldi, %2,hi8(%1)) CR_TAB | |
| 2465 AS2 (cpc, %B0,%2) CR_TAB | |
| 2466 AS2 (ldi, %2,hlo8(%1)) CR_TAB | |
| 2467 AS2 (cpc, %C0,%2) CR_TAB | |
| 2468 AS2 (ldi, %2,hhi8(%1)) CR_TAB | |
| 2469 AS2 (cpc, %D0,%2)); | |
| 2470 } | |
| 2471 return \"bug\"; | |
| 2472 }" | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2473 [(set_attr "cc" "compare,compare,compare,compare,compare,compare") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2474 (set_attr "length" "4,4,4,7,5,8")]) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2475 |
| 0 | 2476 |
| 2477 ;; ---------------------------------------------------------------------- | |
| 2478 ;; JUMP INSTRUCTIONS | |
| 2479 ;; ---------------------------------------------------------------------- | |
| 2480 ;; Conditional jump instructions | |
| 2481 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2482 (define_expand "cbranchsi4" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2483 [(parallel [(set (cc0) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2484 (compare (match_operand:SI 1 "register_operand" "") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2485 (match_operand:SI 2 "nonmemory_operand" ""))) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2486 (clobber (match_scratch:QI 4 ""))]) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2487 (set (pc) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2488 (if_then_else |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2489 (match_operator 0 "ordered_comparison_operator" [(cc0) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2490 (const_int 0)]) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2491 (label_ref (match_operand 3 "" "")) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2492 (pc)))] |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2493 "") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2494 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2495 (define_expand "cbranchhi4" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2496 [(parallel [(set (cc0) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2497 (compare (match_operand:HI 1 "register_operand" "") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2498 (match_operand:HI 2 "nonmemory_operand" ""))) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2499 (clobber (match_scratch:QI 4 ""))]) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2500 (set (pc) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2501 (if_then_else |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2502 (match_operator 0 "ordered_comparison_operator" [(cc0) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2503 (const_int 0)]) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2504 (label_ref (match_operand 3 "" "")) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2505 (pc)))] |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2506 "") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2507 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2508 (define_expand "cbranchqi4" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2509 [(set (cc0) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2510 (compare (match_operand:QI 1 "register_operand" "") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2511 (match_operand:QI 2 "nonmemory_operand" ""))) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2512 (set (pc) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2513 (if_then_else |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2514 (match_operator 0 "ordered_comparison_operator" [(cc0) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2515 (const_int 0)]) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2516 (label_ref (match_operand 3 "" "")) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2517 (pc)))] |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2518 "") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2519 |
| 0 | 2520 |
| 2521 ;; Test a single bit in a QI/HI/SImode register. | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2522 ;; Combine will create zero extract patterns for single bit tests. |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2523 ;; permit any mode in source pattern by using VOIDmode. |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2524 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2525 (define_insn "*sbrx_branch<mode>" |
| 0 | 2526 [(set (pc) |
| 2527 (if_then_else | |
| 2528 (match_operator 0 "eqne_operator" | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2529 [(zero_extract:QIDI |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2530 (match_operand:VOID 1 "register_operand" "r") |
| 0 | 2531 (const_int 1) |
| 2532 (match_operand 2 "const_int_operand" "n")) | |
| 2533 (const_int 0)]) | |
| 2534 (label_ref (match_operand 3 "" "")) | |
| 2535 (pc)))] | |
| 2536 "" | |
| 2537 "* return avr_out_sbxx_branch (insn, operands);" | |
| 2538 [(set (attr "length") | |
| 2539 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046)) | |
| 2540 (le (minus (pc) (match_dup 3)) (const_int 2046))) | |
| 2541 (const_int 2) | |
| 2542 (if_then_else (eq_attr "mcu_mega" "no") | |
| 2543 (const_int 2) | |
| 2544 (const_int 4)))) | |
| 2545 (set_attr "cc" "clobber")]) | |
| 2546 | |
|
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2547 ;; Same test based on Bitwise AND RTL. Keep this incase gcc changes patterns. |
|
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|
2548 ;; or for old peepholes. |
|
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|
2549 ;; Fixme - bitwise Mask will not work for DImode |
|
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2550 |
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2551 (define_insn "*sbrx_and_branch<mode>" |
| 0 | 2552 [(set (pc) |
| 2553 (if_then_else | |
| 2554 (match_operator 0 "eqne_operator" | |
|
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|
2555 [(and:QISI |
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2556 (match_operand:QISI 1 "register_operand" "r") |
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2557 (match_operand:QISI 2 "single_one_operand" "n")) |
| 0 | 2558 (const_int 0)]) |
| 2559 (label_ref (match_operand 3 "" "")) | |
| 2560 (pc)))] | |
| 2561 "" | |
|
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|
2562 { |
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2563 HOST_WIDE_INT bitnumber; |
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2564 bitnumber = exact_log2 (GET_MODE_MASK (<MODE>mode) & INTVAL (operands[2])); |
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|
2565 operands[2] = GEN_INT (bitnumber); |
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2566 return avr_out_sbxx_branch (insn, operands); |
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2567 } |
| 0 | 2568 [(set (attr "length") |
| 2569 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046)) | |
| 2570 (le (minus (pc) (match_dup 3)) (const_int 2046))) | |
| 2571 (const_int 2) | |
| 2572 (if_then_else (eq_attr "mcu_mega" "no") | |
| 2573 (const_int 2) | |
| 2574 (const_int 4)))) | |
| 2575 (set_attr "cc" "clobber")]) | |
| 2576 | |
| 2577 ;; Convert sign tests to bit 7/15/31 tests that match the above insns. | |
| 2578 (define_peephole2 | |
|
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2579 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "") |
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2580 (const_int 0))) |
| 0 | 2581 (set (pc) (if_then_else (ge (cc0) (const_int 0)) |
| 2582 (label_ref (match_operand 1 "" "")) | |
| 2583 (pc)))] | |
| 2584 "" | |
| 2585 [(set (pc) (if_then_else (eq (zero_extract:HI (match_dup 0) | |
| 2586 (const_int 1) | |
| 2587 (const_int 7)) | |
| 2588 (const_int 0)) | |
| 2589 (label_ref (match_dup 1)) | |
| 2590 (pc)))] | |
| 2591 "") | |
| 2592 | |
| 2593 (define_peephole2 | |
|
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2594 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "") |
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2595 (const_int 0))) |
| 0 | 2596 (set (pc) (if_then_else (lt (cc0) (const_int 0)) |
| 2597 (label_ref (match_operand 1 "" "")) | |
| 2598 (pc)))] | |
| 2599 "" | |
| 2600 [(set (pc) (if_then_else (ne (zero_extract:HI (match_dup 0) | |
| 2601 (const_int 1) | |
| 2602 (const_int 7)) | |
| 2603 (const_int 0)) | |
| 2604 (label_ref (match_dup 1)) | |
| 2605 (pc)))] | |
| 2606 "") | |
| 2607 | |
| 2608 (define_peephole2 | |
|
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2609 [(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "") |
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2610 (const_int 0))) |
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2611 (clobber (match_operand:HI 2 ""))]) |
| 0 | 2612 (set (pc) (if_then_else (ge (cc0) (const_int 0)) |
| 2613 (label_ref (match_operand 1 "" "")) | |
| 2614 (pc)))] | |
| 2615 "" | |
| 2616 [(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768)) | |
| 2617 (const_int 0)) | |
| 2618 (label_ref (match_dup 1)) | |
| 2619 (pc)))] | |
| 2620 "") | |
| 2621 | |
| 2622 (define_peephole2 | |
|
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2623 [(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "") |
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2624 (const_int 0))) |
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2625 (clobber (match_operand:HI 2 ""))]) |
| 0 | 2626 (set (pc) (if_then_else (lt (cc0) (const_int 0)) |
| 2627 (label_ref (match_operand 1 "" "")) | |
| 2628 (pc)))] | |
| 2629 "" | |
| 2630 [(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768)) | |
| 2631 (const_int 0)) | |
| 2632 (label_ref (match_dup 1)) | |
| 2633 (pc)))] | |
| 2634 "") | |
| 2635 | |
| 2636 (define_peephole2 | |
|
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2637 [(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "") |
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|
2638 (const_int 0))) |
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|
2639 (clobber (match_operand:SI 2 ""))]) |
| 0 | 2640 (set (pc) (if_then_else (ge (cc0) (const_int 0)) |
| 2641 (label_ref (match_operand 1 "" "")) | |
| 2642 (pc)))] | |
| 2643 "" | |
| 2644 [(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2)) | |
| 2645 (const_int 0)) | |
| 2646 (label_ref (match_dup 1)) | |
| 2647 (pc)))] | |
| 2648 "operands[2] = GEN_INT (-2147483647 - 1);") | |
| 2649 | |
| 2650 (define_peephole2 | |
|
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2651 [(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "") |
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|
2652 (const_int 0))) |
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|
2653 (clobber (match_operand:SI 2 ""))]) |
| 0 | 2654 (set (pc) (if_then_else (lt (cc0) (const_int 0)) |
| 2655 (label_ref (match_operand 1 "" "")) | |
| 2656 (pc)))] | |
| 2657 "" | |
| 2658 [(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2)) | |
| 2659 (const_int 0)) | |
| 2660 (label_ref (match_dup 1)) | |
| 2661 (pc)))] | |
| 2662 "operands[2] = GEN_INT (-2147483647 - 1);") | |
| 2663 | |
| 2664 ;; ************************************************************************ | |
| 2665 ;; Implementation of conditional jumps here. | |
| 2666 ;; Compare with 0 (test) jumps | |
| 2667 ;; ************************************************************************ | |
| 2668 | |
| 2669 (define_insn "branch" | |
| 2670 [(set (pc) | |
| 2671 (if_then_else (match_operator 1 "simple_comparison_operator" | |
| 2672 [(cc0) | |
| 2673 (const_int 0)]) | |
| 2674 (label_ref (match_operand 0 "" "")) | |
| 2675 (pc)))] | |
| 2676 "" | |
| 2677 "* | |
| 2678 return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);" | |
| 2679 [(set_attr "type" "branch") | |
| 2680 (set_attr "cc" "clobber")]) | |
| 2681 | |
|
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|
2682 ;; **************************************************************** |
|
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2683 ;; AVR does not have following conditional jumps: LE,LEU,GT,GTU. |
|
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|
2684 ;; Convert them all to proper jumps. |
|
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|
2685 ;; ****************************************************************/ |
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2686 |
| 0 | 2687 (define_insn "difficult_branch" |
| 2688 [(set (pc) | |
| 2689 (if_then_else (match_operator 1 "difficult_comparison_operator" | |
| 2690 [(cc0) | |
| 2691 (const_int 0)]) | |
| 2692 (label_ref (match_operand 0 "" "")) | |
| 2693 (pc)))] | |
| 2694 "" | |
| 2695 "* | |
| 2696 return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);" | |
| 2697 [(set_attr "type" "branch1") | |
| 2698 (set_attr "cc" "clobber")]) | |
| 2699 | |
| 2700 ;; revers branch | |
| 2701 | |
| 2702 (define_insn "rvbranch" | |
| 2703 [(set (pc) | |
| 2704 (if_then_else (match_operator 1 "simple_comparison_operator" | |
| 2705 [(cc0) | |
| 2706 (const_int 0)]) | |
| 2707 (pc) | |
| 2708 (label_ref (match_operand 0 "" ""))))] | |
| 2709 "" | |
| 2710 "* | |
| 2711 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);" | |
| 2712 [(set_attr "type" "branch1") | |
| 2713 (set_attr "cc" "clobber")]) | |
| 2714 | |
| 2715 (define_insn "difficult_rvbranch" | |
| 2716 [(set (pc) | |
| 2717 (if_then_else (match_operator 1 "difficult_comparison_operator" | |
| 2718 [(cc0) | |
| 2719 (const_int 0)]) | |
| 2720 (pc) | |
| 2721 (label_ref (match_operand 0 "" ""))))] | |
| 2722 "" | |
| 2723 "* | |
| 2724 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);" | |
| 2725 [(set_attr "type" "branch") | |
| 2726 (set_attr "cc" "clobber")]) | |
| 2727 | |
| 2728 ;; ************************************************************************** | |
| 2729 ;; Unconditional and other jump instructions. | |
| 2730 | |
| 2731 (define_insn "jump" | |
| 2732 [(set (pc) | |
| 2733 (label_ref (match_operand 0 "" "")))] | |
| 2734 "" | |
| 2735 "*{ | |
| 2736 if (AVR_HAVE_JMP_CALL && get_attr_length (insn) != 1) | |
|
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|
2737 return AS1 (jmp,%x0); |
|
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2738 return AS1 (rjmp,%x0); |
| 0 | 2739 }" |
| 2740 [(set (attr "length") | |
| 2741 (if_then_else (match_operand 0 "symbol_ref_operand" "") | |
| 2742 (if_then_else (eq_attr "mcu_mega" "no") | |
| 2743 (const_int 1) | |
| 2744 (const_int 2)) | |
| 2745 (if_then_else (and (ge (minus (pc) (match_dup 0)) (const_int -2047)) | |
| 2746 (le (minus (pc) (match_dup 0)) (const_int 2047))) | |
| 2747 (const_int 1) | |
| 2748 (const_int 2)))) | |
| 2749 (set_attr "cc" "none")]) | |
| 2750 | |
| 2751 ;; call | |
| 2752 | |
| 2753 (define_expand "call" | |
| 2754 [(call (match_operand:HI 0 "call_insn_operand" "") | |
| 2755 (match_operand:HI 1 "general_operand" ""))] | |
| 2756 ;; Operand 1 not used on the AVR. | |
| 2757 "" | |
| 2758 "") | |
| 2759 | |
| 2760 ;; call value | |
| 2761 | |
| 2762 (define_expand "call_value" | |
| 2763 [(set (match_operand 0 "register_operand" "") | |
| 2764 (call (match_operand:HI 1 "call_insn_operand" "") | |
| 2765 (match_operand:HI 2 "general_operand" "")))] | |
| 2766 ;; Operand 2 not used on the AVR. | |
| 2767 "" | |
| 2768 "") | |
| 2769 | |
| 2770 (define_insn "call_insn" | |
| 2771 [(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "!z,*r,s,n")) | |
| 2772 (match_operand:HI 1 "general_operand" "X,X,X,X"))] | |
| 2773 ;; We don't need in saving Z register because r30,r31 is a call used registers | |
| 2774 ;; Operand 1 not used on the AVR. | |
| 2775 "(register_operand (operands[0], HImode) || CONSTANT_P (operands[0]))" | |
| 2776 "*{ | |
| 2777 if (which_alternative==0) | |
| 2778 return \"%!icall\"; | |
| 2779 else if (which_alternative==1) | |
| 2780 { | |
| 2781 if (AVR_HAVE_MOVW) | |
| 2782 return (AS2 (movw, r30, %0) CR_TAB | |
| 2783 \"%!icall\"); | |
| 2784 else | |
| 2785 return (AS2 (mov, r30, %A0) CR_TAB | |
| 2786 AS2 (mov, r31, %B0) CR_TAB | |
| 2787 \"%!icall\"); | |
| 2788 } | |
| 2789 else if (which_alternative==2) | |
|
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|
2790 return AS1(%~call,%x0); |
| 0 | 2791 return (AS2 (ldi,r30,lo8(%0)) CR_TAB |
| 2792 AS2 (ldi,r31,hi8(%0)) CR_TAB | |
| 2793 \"%!icall\"); | |
| 2794 }" | |
| 2795 [(set_attr "cc" "clobber,clobber,clobber,clobber") | |
| 2796 (set_attr_alternative "length" | |
| 2797 [(const_int 1) | |
| 2798 (if_then_else (eq_attr "mcu_have_movw" "yes") | |
| 2799 (const_int 2) | |
| 2800 (const_int 3)) | |
| 2801 (if_then_else (eq_attr "mcu_mega" "yes") | |
| 2802 (const_int 2) | |
| 2803 (const_int 1)) | |
| 2804 (const_int 3)])]) | |
| 2805 | |
| 2806 (define_insn "call_value_insn" | |
| 2807 [(set (match_operand 0 "register_operand" "=r,r,r,r") | |
| 2808 (call (mem:HI (match_operand:HI 1 "nonmemory_operand" "!z,*r,s,n")) | |
| 2809 ;; We don't need in saving Z register because r30,r31 is a call used registers | |
| 2810 (match_operand:HI 2 "general_operand" "X,X,X,X")))] | |
| 2811 ;; Operand 2 not used on the AVR. | |
| 2812 "(register_operand (operands[0], VOIDmode) || CONSTANT_P (operands[0]))" | |
| 2813 "*{ | |
| 2814 if (which_alternative==0) | |
| 2815 return \"%!icall\"; | |
| 2816 else if (which_alternative==1) | |
| 2817 { | |
| 2818 if (AVR_HAVE_MOVW) | |
| 2819 return (AS2 (movw, r30, %1) CR_TAB | |
| 2820 \"%!icall\"); | |
| 2821 else | |
| 2822 return (AS2 (mov, r30, %A1) CR_TAB | |
| 2823 AS2 (mov, r31, %B1) CR_TAB | |
| 2824 \"%!icall\"); | |
| 2825 } | |
| 2826 else if (which_alternative==2) | |
|
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2827 return AS1(%~call,%x1); |
| 0 | 2828 return (AS2 (ldi, r30, lo8(%1)) CR_TAB |
| 2829 AS2 (ldi, r31, hi8(%1)) CR_TAB | |
| 2830 \"%!icall\"); | |
| 2831 }" | |
| 2832 [(set_attr "cc" "clobber,clobber,clobber,clobber") | |
| 2833 (set_attr_alternative "length" | |
| 2834 [(const_int 1) | |
| 2835 (if_then_else (eq_attr "mcu_have_movw" "yes") | |
| 2836 (const_int 2) | |
| 2837 (const_int 3)) | |
| 2838 (if_then_else (eq_attr "mcu_mega" "yes") | |
| 2839 (const_int 2) | |
| 2840 (const_int 1)) | |
| 2841 (const_int 3)])]) | |
| 2842 | |
| 2843 (define_insn "nop" | |
| 2844 [(const_int 0)] | |
| 2845 "" | |
| 2846 "nop" | |
| 2847 [(set_attr "cc" "none") | |
| 2848 (set_attr "length" "1")]) | |
| 2849 | |
| 2850 ; indirect jump | |
|
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|
2851 |
|
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|
2852 (define_expand "indirect_jump" |
|
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2853 [(set (pc) (match_operand:HI 0 "nonmemory_operand" ""))] |
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2854 "" |
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2855 " if ((!AVR_HAVE_JMP_CALL) && !register_operand(operand0, HImode)) |
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2856 { |
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2857 operands[0] = copy_to_mode_reg(HImode, operand0); |
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2858 }" |
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2859 ) |
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2860 |
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2861 ; indirect jump |
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2862 (define_insn "*jcindirect_jump" |
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2863 [(set (pc) (match_operand:HI 0 "immediate_operand" "i"))] |
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2864 "" |
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2865 "@ |
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2866 %~jmp %x0" |
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2867 [(set_attr "length" "2") |
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2868 (set_attr "cc" "none")]) |
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2869 |
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2870 ;; |
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2871 (define_insn "*njcindirect_jump" |
| 0 | 2872 [(set (pc) (match_operand:HI 0 "register_operand" "!z,*r"))] |
| 2873 "!AVR_HAVE_EIJMP_EICALL" | |
| 2874 "@ | |
| 2875 ijmp | |
| 2876 push %A0\;push %B0\;ret" | |
| 2877 [(set_attr "length" "1,3") | |
| 2878 (set_attr "cc" "none,none")]) | |
| 2879 | |
| 2880 (define_insn "*indirect_jump_avr6" | |
| 2881 [(set (pc) (match_operand:HI 0 "register_operand" "z"))] | |
| 2882 "AVR_HAVE_EIJMP_EICALL" | |
| 2883 "eijmp" | |
| 2884 [(set_attr "length" "1") | |
| 2885 (set_attr "cc" "none")]) | |
| 2886 | |
| 2887 ;; table jump | |
| 2888 | |
| 2889 ;; Table made from "rjmp" instructions for <=8K devices. | |
| 2890 (define_insn "*tablejump_rjmp" | |
| 2891 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "!z,*r")] | |
| 2892 UNSPEC_INDEX_JMP)) | |
| 2893 (use (label_ref (match_operand 1 "" ""))) | |
| 2894 (clobber (match_dup 0))] | |
| 2895 "(!AVR_HAVE_JMP_CALL) && (!AVR_HAVE_EIJMP_EICALL)" | |
| 2896 "@ | |
| 2897 ijmp | |
| 2898 push %A0\;push %B0\;ret" | |
| 2899 [(set_attr "length" "1,3") | |
| 2900 (set_attr "cc" "none,none")]) | |
| 2901 | |
| 2902 ;; Not a prologue, but similar idea - move the common piece of code to libgcc. | |
| 2903 (define_insn "*tablejump_lib" | |
| 2904 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")] | |
| 2905 UNSPEC_INDEX_JMP)) | |
| 2906 (use (label_ref (match_operand 1 "" ""))) | |
| 2907 (clobber (match_dup 0))] | |
| 2908 "AVR_HAVE_JMP_CALL && TARGET_CALL_PROLOGUES" | |
|
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2909 "%~jmp __tablejump2__" |
| 0 | 2910 [(set_attr "length" "2") |
| 2911 (set_attr "cc" "clobber")]) | |
| 2912 | |
| 2913 (define_insn "*tablejump_enh" | |
| 2914 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")] | |
| 2915 UNSPEC_INDEX_JMP)) | |
| 2916 (use (label_ref (match_operand 1 "" ""))) | |
| 2917 (clobber (match_dup 0))] | |
| 2918 "AVR_HAVE_JMP_CALL && AVR_HAVE_LPMX" | |
| 2919 "lsl r30 | |
| 2920 rol r31 | |
| 2921 lpm __tmp_reg__,Z+ | |
| 2922 lpm r31,Z | |
| 2923 mov r30,__tmp_reg__ | |
| 2924 %!ijmp" | |
| 2925 [(set_attr "length" "6") | |
| 2926 (set_attr "cc" "clobber")]) | |
| 2927 | |
| 2928 (define_insn "*tablejump" | |
| 2929 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")] | |
| 2930 UNSPEC_INDEX_JMP)) | |
| 2931 (use (label_ref (match_operand 1 "" ""))) | |
| 2932 (clobber (match_dup 0))] | |
| 2933 "AVR_HAVE_JMP_CALL && !AVR_HAVE_EIJMP_EICALL" | |
| 2934 "lsl r30 | |
| 2935 rol r31 | |
| 2936 lpm | |
| 2937 inc r30 | |
| 2938 push r0 | |
| 2939 lpm | |
| 2940 push r0 | |
| 2941 ret" | |
| 2942 [(set_attr "length" "8") | |
| 2943 (set_attr "cc" "clobber")]) | |
| 2944 | |
| 2945 (define_expand "casesi" | |
| 2946 [(set (match_dup 6) | |
| 2947 (minus:HI (subreg:HI (match_operand:SI 0 "register_operand" "") 0) | |
| 2948 (match_operand:HI 1 "register_operand" ""))) | |
| 2949 (parallel [(set (cc0) | |
| 2950 (compare (match_dup 6) | |
| 2951 (match_operand:HI 2 "register_operand" ""))) | |
| 2952 (clobber (match_scratch:QI 9 ""))]) | |
| 2953 | |
| 2954 (set (pc) | |
| 2955 (if_then_else (gtu (cc0) | |
| 2956 (const_int 0)) | |
| 2957 (label_ref (match_operand 4 "" "")) | |
| 2958 (pc))) | |
| 2959 | |
| 2960 (set (match_dup 6) | |
| 2961 (plus:HI (match_dup 6) (label_ref (match_operand:HI 3 "" "")))) | |
| 2962 | |
| 2963 (parallel [(set (pc) (unspec:HI [(match_dup 6)] UNSPEC_INDEX_JMP)) | |
| 2964 (use (label_ref (match_dup 3))) | |
| 2965 (clobber (match_dup 6))])] | |
| 2966 "" | |
| 2967 " | |
| 2968 { | |
| 2969 operands[6] = gen_reg_rtx (HImode); | |
| 2970 }") | |
| 2971 | |
| 2972 | |
| 2973 ;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | |
| 2974 ;; This instruction sets Z flag | |
| 2975 | |
| 2976 (define_insn "sez" | |
| 2977 [(set (cc0) (const_int 0))] | |
| 2978 "" | |
| 2979 "sez" | |
| 2980 [(set_attr "length" "1") | |
| 2981 (set_attr "cc" "compare")]) | |
| 2982 | |
| 2983 ;; Clear/set/test a single bit in I/O address space. | |
| 2984 | |
| 2985 (define_insn "*cbi" | |
| 2986 [(set (mem:QI (match_operand 0 "low_io_address_operand" "n")) | |
| 2987 (and:QI (mem:QI (match_dup 0)) | |
| 2988 (match_operand:QI 1 "single_zero_operand" "n")))] | |
| 2989 "(optimize > 0)" | |
| 2990 { | |
| 2991 operands[2] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff)); | |
|
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2992 return AS2 (cbi,%m0-0x20,%2); |
| 0 | 2993 } |
| 2994 [(set_attr "length" "1") | |
| 2995 (set_attr "cc" "none")]) | |
| 2996 | |
| 2997 (define_insn "*sbi" | |
| 2998 [(set (mem:QI (match_operand 0 "low_io_address_operand" "n")) | |
| 2999 (ior:QI (mem:QI (match_dup 0)) | |
| 3000 (match_operand:QI 1 "single_one_operand" "n")))] | |
| 3001 "(optimize > 0)" | |
| 3002 { | |
| 3003 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff)); | |
|
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3004 return AS2 (sbi,%m0-0x20,%2); |
| 0 | 3005 } |
| 3006 [(set_attr "length" "1") | |
| 3007 (set_attr "cc" "none")]) | |
| 3008 | |
| 3009 ;; Lower half of the I/O space - use sbic/sbis directly. | |
| 3010 (define_insn "*sbix_branch" | |
| 3011 [(set (pc) | |
| 3012 (if_then_else | |
| 3013 (match_operator 0 "eqne_operator" | |
| 3014 [(zero_extract:HI | |
| 3015 (mem:QI (match_operand 1 "low_io_address_operand" "n")) | |
| 3016 (const_int 1) | |
| 3017 (match_operand 2 "const_int_operand" "n")) | |
| 3018 (const_int 0)]) | |
| 3019 (label_ref (match_operand 3 "" "")) | |
| 3020 (pc)))] | |
| 3021 "(optimize > 0)" | |
| 3022 "* return avr_out_sbxx_branch (insn, operands);" | |
| 3023 [(set (attr "length") | |
| 3024 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046)) | |
| 3025 (le (minus (pc) (match_dup 3)) (const_int 2046))) | |
| 3026 (const_int 2) | |
| 3027 (if_then_else (eq_attr "mcu_mega" "no") | |
| 3028 (const_int 2) | |
| 3029 (const_int 4)))) | |
| 3030 (set_attr "cc" "clobber")]) | |
| 3031 | |
| 3032 ;; Tests of bit 7 are pessimized to sign tests, so we need this too... | |
| 3033 (define_insn "*sbix_branch_bit7" | |
| 3034 [(set (pc) | |
| 3035 (if_then_else | |
| 3036 (match_operator 0 "gelt_operator" | |
| 3037 [(mem:QI (match_operand 1 "low_io_address_operand" "n")) | |
| 3038 (const_int 0)]) | |
| 3039 (label_ref (match_operand 2 "" "")) | |
| 3040 (pc)))] | |
| 3041 "(optimize > 0)" | |
| 3042 { | |
| 3043 operands[3] = operands[2]; | |
| 3044 operands[2] = GEN_INT (7); | |
| 3045 return avr_out_sbxx_branch (insn, operands); | |
| 3046 } | |
| 3047 [(set (attr "length") | |
| 3048 (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046)) | |
| 3049 (le (minus (pc) (match_dup 2)) (const_int 2046))) | |
| 3050 (const_int 2) | |
| 3051 (if_then_else (eq_attr "mcu_mega" "no") | |
| 3052 (const_int 2) | |
| 3053 (const_int 4)))) | |
| 3054 (set_attr "cc" "clobber")]) | |
| 3055 | |
| 3056 ;; Upper half of the I/O space - read port to __tmp_reg__ and use sbrc/sbrs. | |
| 3057 (define_insn "*sbix_branch_tmp" | |
| 3058 [(set (pc) | |
| 3059 (if_then_else | |
| 3060 (match_operator 0 "eqne_operator" | |
| 3061 [(zero_extract:HI | |
| 3062 (mem:QI (match_operand 1 "high_io_address_operand" "n")) | |
| 3063 (const_int 1) | |
| 3064 (match_operand 2 "const_int_operand" "n")) | |
| 3065 (const_int 0)]) | |
| 3066 (label_ref (match_operand 3 "" "")) | |
| 3067 (pc)))] | |
| 3068 "(optimize > 0)" | |
| 3069 "* return avr_out_sbxx_branch (insn, operands);" | |
| 3070 [(set (attr "length") | |
| 3071 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046)) | |
| 3072 (le (minus (pc) (match_dup 3)) (const_int 2045))) | |
| 3073 (const_int 3) | |
| 3074 (if_then_else (eq_attr "mcu_mega" "no") | |
| 3075 (const_int 3) | |
| 3076 (const_int 5)))) | |
| 3077 (set_attr "cc" "clobber")]) | |
| 3078 | |
| 3079 (define_insn "*sbix_branch_tmp_bit7" | |
| 3080 [(set (pc) | |
| 3081 (if_then_else | |
| 3082 (match_operator 0 "gelt_operator" | |
| 3083 [(mem:QI (match_operand 1 "high_io_address_operand" "n")) | |
| 3084 (const_int 0)]) | |
| 3085 (label_ref (match_operand 2 "" "")) | |
| 3086 (pc)))] | |
| 3087 "(optimize > 0)" | |
| 3088 { | |
| 3089 operands[3] = operands[2]; | |
| 3090 operands[2] = GEN_INT (7); | |
| 3091 return avr_out_sbxx_branch (insn, operands); | |
| 3092 } | |
| 3093 [(set (attr "length") | |
| 3094 (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046)) | |
| 3095 (le (minus (pc) (match_dup 2)) (const_int 2045))) | |
| 3096 (const_int 3) | |
| 3097 (if_then_else (eq_attr "mcu_mega" "no") | |
| 3098 (const_int 3) | |
| 3099 (const_int 5)))) | |
| 3100 (set_attr "cc" "clobber")]) | |
| 3101 | |
| 3102 ;; ************************* Peepholes ******************************** | |
| 3103 | |
| 3104 (define_peephole | |
| 3105 [(set (match_operand:SI 0 "d_register_operand" "") | |
| 3106 (plus:SI (match_dup 0) | |
| 3107 (const_int -1))) | |
| 3108 (parallel | |
| 3109 [(set (cc0) | |
| 3110 (compare (match_dup 0) | |
| 3111 (const_int -1))) | |
| 3112 (clobber (match_operand:QI 1 "d_register_operand" ""))]) | |
| 3113 (set (pc) | |
| 3114 (if_then_else (ne (cc0) (const_int 0)) | |
| 3115 (label_ref (match_operand 2 "" "")) | |
| 3116 (pc)))] | |
| 3117 "" | |
| 3118 "* | |
| 3119 { | |
| 3120 CC_STATUS_INIT; | |
| 3121 if (test_hard_reg_class (ADDW_REGS, operands[0])) | |
| 3122 output_asm_insn (AS2 (sbiw,%0,1) CR_TAB | |
| 3123 AS2 (sbc,%C0,__zero_reg__) CR_TAB | |
| 3124 AS2 (sbc,%D0,__zero_reg__) \"\\n\", operands); | |
| 3125 else | |
| 3126 output_asm_insn (AS2 (subi,%A0,1) CR_TAB | |
| 3127 AS2 (sbc,%B0,__zero_reg__) CR_TAB | |
| 3128 AS2 (sbc,%C0,__zero_reg__) CR_TAB | |
| 3129 AS2 (sbc,%D0,__zero_reg__) \"\\n\", operands); | |
| 3130 switch (avr_jump_mode (operands[2],insn)) | |
| 3131 { | |
| 3132 case 1: | |
| 3133 return AS1 (brcc,%2); | |
| 3134 case 2: | |
| 3135 return (AS1 (brcs,.+2) CR_TAB | |
| 3136 AS1 (rjmp,%2)); | |
| 3137 } | |
| 3138 return (AS1 (brcs,.+4) CR_TAB | |
| 3139 AS1 (jmp,%2)); | |
| 3140 }") | |
| 3141 | |
| 3142 (define_peephole | |
| 3143 [(set (match_operand:HI 0 "d_register_operand" "") | |
| 3144 (plus:HI (match_dup 0) | |
| 3145 (const_int -1))) | |
| 3146 (parallel | |
| 3147 [(set (cc0) | |
| 3148 (compare (match_dup 0) | |
| 3149 (const_int 65535))) | |
| 3150 (clobber (match_operand:QI 1 "d_register_operand" ""))]) | |
| 3151 (set (pc) | |
| 3152 (if_then_else (ne (cc0) (const_int 0)) | |
| 3153 (label_ref (match_operand 2 "" "")) | |
| 3154 (pc)))] | |
| 3155 "" | |
| 3156 "* | |
| 3157 { | |
| 3158 CC_STATUS_INIT; | |
| 3159 if (test_hard_reg_class (ADDW_REGS, operands[0])) | |
| 3160 output_asm_insn (AS2 (sbiw,%0,1), operands); | |
| 3161 else | |
| 3162 output_asm_insn (AS2 (subi,%A0,1) CR_TAB | |
| 3163 AS2 (sbc,%B0,__zero_reg__) \"\\n\", operands); | |
| 3164 switch (avr_jump_mode (operands[2],insn)) | |
| 3165 { | |
| 3166 case 1: | |
| 3167 return AS1 (brcc,%2); | |
| 3168 case 2: | |
| 3169 return (AS1 (brcs,.+2) CR_TAB | |
| 3170 AS1 (rjmp,%2)); | |
| 3171 } | |
| 3172 return (AS1 (brcs,.+4) CR_TAB | |
| 3173 AS1 (jmp,%2)); | |
| 3174 }") | |
| 3175 | |
| 3176 (define_peephole | |
| 3177 [(set (match_operand:QI 0 "d_register_operand" "") | |
| 3178 (plus:QI (match_dup 0) | |
| 3179 (const_int -1))) | |
| 3180 (set (cc0) | |
| 3181 (compare (match_dup 0) | |
| 3182 (const_int -1))) | |
| 3183 (set (pc) | |
| 3184 (if_then_else (ne (cc0) (const_int 0)) | |
| 3185 (label_ref (match_operand 1 "" "")) | |
| 3186 (pc)))] | |
| 3187 "" | |
| 3188 "* | |
| 3189 { | |
| 3190 CC_STATUS_INIT; | |
| 3191 cc_status.value1 = operands[0]; | |
| 3192 cc_status.flags |= CC_OVERFLOW_UNUSABLE; | |
| 3193 output_asm_insn (AS2 (subi,%A0,1), operands); | |
| 3194 switch (avr_jump_mode (operands[1],insn)) | |
| 3195 { | |
| 3196 case 1: | |
| 3197 return AS1 (brcc,%1); | |
| 3198 case 2: | |
| 3199 return (AS1 (brcs,.+2) CR_TAB | |
| 3200 AS1 (rjmp,%1)); | |
| 3201 } | |
| 3202 return (AS1 (brcs,.+4) CR_TAB | |
| 3203 AS1 (jmp,%1)); | |
| 3204 }") | |
| 3205 | |
| 3206 (define_peephole | |
|
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|
3207 [(set (cc0) |
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3208 (compare (match_operand:QI 0 "register_operand" "") |
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|
3209 (const_int 0))) |
| 0 | 3210 (set (pc) |
| 3211 (if_then_else (eq (cc0) (const_int 0)) | |
| 3212 (label_ref (match_operand 1 "" "")) | |
| 3213 (pc)))] | |
| 3214 "jump_over_one_insn_p (insn, operands[1])" | |
| 3215 "cpse %0,__zero_reg__") | |
| 3216 | |
| 3217 (define_peephole | |
| 3218 [(set (cc0) | |
| 3219 (compare (match_operand:QI 0 "register_operand" "") | |
| 3220 (match_operand:QI 1 "register_operand" ""))) | |
| 3221 (set (pc) | |
| 3222 (if_then_else (eq (cc0) (const_int 0)) | |
| 3223 (label_ref (match_operand 2 "" "")) | |
| 3224 (pc)))] | |
| 3225 "jump_over_one_insn_p (insn, operands[2])" | |
| 3226 "cpse %0,%1") | |
| 3227 | |
| 3228 ;;pppppppppppppppppppppppppppppppppppppppppppppppppppp | |
| 3229 ;;prologue/epilogue support instructions | |
| 3230 | |
| 3231 (define_insn "popqi" | |
| 3232 [(set (match_operand:QI 0 "register_operand" "=r") | |
| 3233 (mem:QI (post_inc (reg:HI REG_SP))))] | |
| 3234 "" | |
| 3235 "pop %0" | |
| 3236 [(set_attr "cc" "none") | |
| 3237 (set_attr "length" "1")]) | |
| 3238 | |
| 3239 (define_insn "pophi" | |
| 3240 [(set (match_operand:HI 0 "register_operand" "=r") | |
| 3241 (mem:HI (post_inc (reg:HI REG_SP))))] | |
| 3242 "" | |
| 3243 "pop %A0\;pop %B0" | |
| 3244 [(set_attr "cc" "none") | |
| 3245 (set_attr "length" "2")]) | |
| 3246 | |
| 3247 ;; Enable Interrupts | |
| 3248 (define_insn "enable_interrupt" | |
| 3249 [(unspec [(const_int 0)] UNSPEC_SEI)] | |
| 3250 "" | |
| 3251 "sei" | |
| 3252 [(set_attr "length" "1") | |
| 3253 (set_attr "cc" "none") | |
| 3254 ]) | |
| 3255 | |
| 3256 ;; Disable Interrupts | |
| 3257 (define_insn "disable_interrupt" | |
| 3258 [(unspec [(const_int 0)] UNSPEC_CLI)] | |
| 3259 "" | |
| 3260 "cli" | |
| 3261 [(set_attr "length" "1") | |
| 3262 (set_attr "cc" "none") | |
| 3263 ]) | |
| 3264 | |
| 3265 ;; Library prologue saves | |
| 3266 (define_insn "call_prologue_saves" | |
| 3267 [(unspec_volatile:HI [(const_int 0)] UNSPECV_PROLOGUE_SAVES) | |
| 3268 (match_operand:HI 0 "immediate_operand" "") | |
| 3269 (set (reg:HI REG_SP) (minus:HI | |
| 3270 (reg:HI REG_SP) | |
| 3271 (match_operand:HI 1 "immediate_operand" ""))) | |
| 3272 (use (reg:HI REG_X)) | |
| 3273 (clobber (reg:HI REG_Z))] | |
| 3274 "" | |
| 3275 "ldi r30,lo8(gs(1f)) | |
| 3276 ldi r31,hi8(gs(1f)) | |
| 3277 %~jmp __prologue_saves__+((18 - %0) * 2) | |
| 3278 1:" | |
| 3279 [(set_attr_alternative "length" | |
| 3280 [(if_then_else (eq_attr "mcu_mega" "yes") | |
| 3281 (const_int 6) | |
| 3282 (const_int 5))]) | |
| 3283 (set_attr "cc" "clobber") | |
| 3284 ]) | |
| 3285 | |
| 3286 ; epilogue restores using library | |
| 3287 (define_insn "epilogue_restores" | |
| 3288 [(unspec_volatile:QI [(const_int 0)] UNSPECV_EPILOGUE_RESTORES) | |
| 3289 (set (reg:HI REG_Y ) (plus:HI | |
| 3290 (reg:HI REG_Y) | |
| 3291 (match_operand:HI 0 "immediate_operand" ""))) | |
| 3292 (set (reg:HI REG_SP) (reg:HI REG_Y)) | |
| 3293 (clobber (reg:QI REG_Z))] | |
| 3294 "" | |
| 3295 "ldi r30, lo8(%0) | |
| 3296 %~jmp __epilogue_restores__ + ((18 - %0) * 2)" | |
| 3297 [(set_attr_alternative "length" | |
| 3298 [(if_then_else (eq_attr "mcu_mega" "yes") | |
| 3299 (const_int 3) | |
| 3300 (const_int 2))]) | |
| 3301 (set_attr "cc" "clobber") | |
| 3302 ]) | |
| 3303 | |
| 3304 ; return | |
| 3305 (define_insn "return" | |
| 3306 [(return)] | |
| 3307 "reload_completed && avr_simple_epilogue ()" | |
| 3308 "ret" | |
| 3309 [(set_attr "cc" "none") | |
| 3310 (set_attr "length" "1")]) | |
| 3311 | |
| 3312 (define_insn "return_from_epilogue" | |
| 3313 [(return)] | |
| 3314 "(reload_completed | |
| 3315 && cfun->machine | |
| 3316 && !(cfun->machine->is_interrupt || cfun->machine->is_signal) | |
| 3317 && !cfun->machine->is_naked)" | |
| 3318 "ret" | |
| 3319 [(set_attr "cc" "none") | |
| 3320 (set_attr "length" "1")]) | |
| 3321 | |
| 3322 (define_insn "return_from_interrupt_epilogue" | |
| 3323 [(return)] | |
| 3324 "(reload_completed | |
| 3325 && cfun->machine | |
| 3326 && (cfun->machine->is_interrupt || cfun->machine->is_signal) | |
| 3327 && !cfun->machine->is_naked)" | |
| 3328 "reti" | |
| 3329 [(set_attr "cc" "none") | |
| 3330 (set_attr "length" "1")]) | |
| 3331 | |
| 3332 (define_insn "return_from_naked_epilogue" | |
| 3333 [(return)] | |
| 3334 "(reload_completed | |
| 3335 && cfun->machine | |
| 3336 && cfun->machine->is_naked)" | |
| 3337 "" | |
| 3338 [(set_attr "cc" "none") | |
| 3339 (set_attr "length" "0")]) | |
| 3340 | |
| 3341 (define_expand "prologue" | |
| 3342 [(const_int 0)] | |
| 3343 "" | |
| 3344 " | |
| 3345 { | |
| 3346 expand_prologue (); | |
| 3347 DONE; | |
| 3348 }") | |
| 3349 | |
| 3350 (define_expand "epilogue" | |
| 3351 [(const_int 0)] | |
| 3352 "" | |
| 3353 " | |
| 3354 { | |
| 3355 expand_epilogue (); | |
| 3356 DONE; | |
| 3357 }") |