Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/arm/vfp.md @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
| author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 22 Mar 2011 17:18:12 +0900 |
| parents | b7f97abdc517 |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
| 0 | 1 ;; ARM VFP instruction patterns |
|
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2 ;; Copyright (C) 2003, 2005, 2006, 2007, 2008, 2010 |
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3 ;; Free Software Foundation, Inc. |
| 0 | 4 ;; Written by CodeSourcery. |
| 5 ;; | |
| 6 ;; This file is part of GCC. | |
| 7 ;; | |
| 8 ;; GCC is free software; you can redistribute it and/or modify it | |
| 9 ;; under the terms of the GNU General Public License as published by | |
| 10 ;; the Free Software Foundation; either version 3, or (at your option) | |
| 11 ;; any later version. | |
| 12 ;; | |
| 13 ;; GCC is distributed in the hope that it will be useful, but | |
| 14 ;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 16 ;; General Public License for more details. | |
| 17 ;; | |
| 18 ;; You should have received a copy of the GNU General Public License | |
| 19 ;; along with GCC; see the file COPYING3. If not see | |
| 20 ;; <http://www.gnu.org/licenses/>. */ | |
| 21 | |
| 22 ;; Additional register numbers | |
| 23 (define_constants | |
| 24 [(VFPCC_REGNUM 127)] | |
| 25 ) | |
| 26 | |
| 27 ;; The VFP "type" attributes differ from those used in the FPA model. | |
| 28 ;; fcpys Single precision cpy. | |
| 29 ;; ffariths Single precision abs, neg. | |
| 30 ;; ffarithd Double precision abs, neg, cpy. | |
| 31 ;; fadds Single precision add/sub. | |
| 32 ;; faddd Double precision add/sub. | |
| 33 ;; fconsts Single precision load immediate. | |
| 34 ;; fconstd Double precision load immediate. | |
| 35 ;; fcmps Single precision comparison. | |
| 36 ;; fcmpd Double precision comparison. | |
| 37 ;; fmuls Single precision multiply. | |
| 38 ;; fmuld Double precision multiply. | |
| 39 ;; fmacs Single precision multiply-accumulate. | |
| 40 ;; fmacd Double precision multiply-accumulate. | |
| 41 ;; fdivs Single precision sqrt or division. | |
| 42 ;; fdivd Double precision sqrt or division. | |
| 43 ;; f_flag fmstat operation | |
| 44 ;; f_load[sd] Floating point load from memory. | |
| 45 ;; f_store[sd] Floating point store to memory. | |
| 46 ;; f_2_r Transfer vfp to arm reg. | |
| 47 ;; r_2_f Transfer arm to vfp reg. | |
| 48 ;; f_cvt Convert floating<->integral | |
| 49 | |
| 50 ;; SImode moves | |
| 51 ;; ??? For now do not allow loading constants into vfp regs. This causes | |
| 52 ;; problems because small constants get converted into adds. | |
| 53 (define_insn "*arm_movsi_vfp" | |
| 54 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv") | |
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55 (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))] |
| 0 | 56 "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT |
| 57 && ( s_register_operand (operands[0], SImode) | |
| 58 || s_register_operand (operands[1], SImode))" | |
| 59 "* | |
| 60 switch (which_alternative) | |
| 61 { | |
| 62 case 0: case 1: | |
| 63 return \"mov%?\\t%0, %1\"; | |
| 64 case 2: | |
| 65 return \"mvn%?\\t%0, #%B1\"; | |
| 66 case 3: | |
| 67 return \"movw%?\\t%0, %1\"; | |
| 68 case 4: | |
| 69 return \"ldr%?\\t%0, %1\"; | |
| 70 case 5: | |
| 71 return \"str%?\\t%1, %0\"; | |
| 72 case 6: | |
| 73 return \"fmsr%?\\t%0, %1\\t%@ int\"; | |
| 74 case 7: | |
| 75 return \"fmrs%?\\t%0, %1\\t%@ int\"; | |
| 76 case 8: | |
| 77 return \"fcpys%?\\t%0, %1\\t%@ int\"; | |
| 78 case 9: case 10: | |
| 79 return output_move_vfp (operands); | |
| 80 default: | |
| 81 gcc_unreachable (); | |
| 82 } | |
| 83 " | |
| 84 [(set_attr "predicable" "yes") | |
| 85 (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") | |
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86 (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*") |
| 0 | 87 (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*") |
| 88 (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")] | |
| 89 ) | |
| 90 | |
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91 ;; See thumb2.md:thumb2_movsi_insn for an explanation of the split |
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92 ;; high/low register alternatives for loads and stores here. |
| 0 | 93 (define_insn "*thumb2_movsi_vfp" |
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94 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r, l,*hk,m, *m,*t, r,*t,*t, *Uv") |
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95 (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,*mi,l,*hk, r,*t,*t,*Uvi,*t"))] |
| 0 | 96 "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT |
| 97 && ( s_register_operand (operands[0], SImode) | |
| 98 || s_register_operand (operands[1], SImode))" | |
| 99 "* | |
| 100 switch (which_alternative) | |
| 101 { | |
| 102 case 0: case 1: | |
| 103 return \"mov%?\\t%0, %1\"; | |
| 104 case 2: | |
| 105 return \"mvn%?\\t%0, #%B1\"; | |
| 106 case 3: | |
| 107 return \"movw%?\\t%0, %1\"; | |
| 108 case 4: | |
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109 case 5: |
| 0 | 110 return \"ldr%?\\t%0, %1\"; |
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111 case 6: |
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112 case 7: |
| 0 | 113 return \"str%?\\t%1, %0\"; |
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114 case 8: |
| 0 | 115 return \"fmsr%?\\t%0, %1\\t%@ int\"; |
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116 case 9: |
| 0 | 117 return \"fmrs%?\\t%0, %1\\t%@ int\"; |
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118 case 10: |
| 0 | 119 return \"fcpys%?\\t%0, %1\\t%@ int\"; |
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120 case 11: case 12: |
| 0 | 121 return output_move_vfp (operands); |
| 122 default: | |
| 123 gcc_unreachable (); | |
| 124 } | |
| 125 " | |
| 126 [(set_attr "predicable" "yes") | |
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127 (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") |
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128 (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*,*,*") |
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129 (set_attr "pool_range" "*,*,*,*,1020,4096,*,*,*,*,*,1020,*") |
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130 (set_attr "neg_pool_range" "*,*,*,*, 0, 0,*,*,*,*,*,1008,*")] |
| 0 | 131 ) |
| 132 | |
| 133 | |
| 134 ;; DImode moves | |
| 135 | |
| 136 (define_insn "*arm_movdi_vfp" | |
| 137 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv") | |
| 138 (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))] | |
| 139 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP | |
| 140 && ( register_operand (operands[0], DImode) | |
| 141 || register_operand (operands[1], DImode))" | |
| 142 "* | |
| 143 switch (which_alternative) | |
| 144 { | |
| 145 case 0: | |
| 146 return \"#\"; | |
| 147 case 1: | |
| 148 case 2: | |
| 149 return output_move_double (operands); | |
| 150 case 3: | |
| 151 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\"; | |
| 152 case 4: | |
| 153 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\"; | |
| 154 case 5: | |
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155 if (TARGET_VFP_SINGLE) |
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156 return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\"; |
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157 else |
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158 return \"fcpyd%?\\t%P0, %P1\\t%@ int\"; |
| 0 | 159 case 6: case 7: |
| 160 return output_move_vfp (operands); | |
| 161 default: | |
| 162 gcc_unreachable (); | |
| 163 } | |
| 164 " | |
| 165 [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") | |
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166 (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8) |
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167 (eq_attr "alternative" "5") |
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168 (if_then_else |
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169 (eq (symbol_ref "TARGET_VFP_SINGLE") |
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170 (const_int 1)) |
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171 (const_int 8) |
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172 (const_int 4))] |
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173 (const_int 4))) |
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174 (set_attr "predicable" "yes") |
| 0 | 175 (set_attr "pool_range" "*,1020,*,*,*,*,1020,*") |
| 176 (set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")] | |
| 177 ) | |
| 178 | |
| 179 (define_insn "*thumb2_movdi_vfp" | |
| 180 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv") | |
| 181 (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))] | |
| 182 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 183 "* | |
| 184 switch (which_alternative) | |
| 185 { | |
| 186 case 0: case 1: case 2: | |
| 187 return (output_move_double (operands)); | |
| 188 case 3: | |
| 189 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\"; | |
| 190 case 4: | |
| 191 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\"; | |
| 192 case 5: | |
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193 if (TARGET_VFP_SINGLE) |
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194 return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\"; |
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195 else |
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196 return \"fcpyd%?\\t%P0, %P1\\t%@ int\"; |
| 0 | 197 case 6: case 7: |
| 198 return output_move_vfp (operands); | |
| 199 default: | |
| 200 abort (); | |
| 201 } | |
| 202 " | |
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203 [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") |
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204 (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8) |
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205 (eq_attr "alternative" "5") |
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206 (if_then_else |
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207 (eq (symbol_ref "TARGET_VFP_SINGLE") |
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208 (const_int 1)) |
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209 (const_int 8) |
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210 (const_int 4))] |
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211 (const_int 4))) |
| 0 | 212 (set_attr "pool_range" "*,4096,*,*,*,*,1020,*") |
| 213 (set_attr "neg_pool_range" "*, 0,*,*,*,*,1008,*")] | |
| 214 ) | |
| 215 | |
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216 ;; HFmode moves |
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217 (define_insn "*movhf_vfp_neon" |
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218 [(set (match_operand:HF 0 "nonimmediate_operand" "= t,Um,r,m,t,r,t,r,r") |
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219 (match_operand:HF 1 "general_operand" " Um, t,m,r,t,r,r,t,F"))] |
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220 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16 |
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221 && ( s_register_operand (operands[0], HFmode) |
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222 || s_register_operand (operands[1], HFmode))" |
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223 "* |
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224 switch (which_alternative) |
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225 { |
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226 case 0: /* S register from memory */ |
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227 return \"vld1.16\\t{%z0}, %A1\"; |
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228 case 1: /* memory from S register */ |
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229 return \"vst1.16\\t{%z1}, %A0\"; |
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230 case 2: /* ARM register from memory */ |
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231 return \"ldrh\\t%0, %1\\t%@ __fp16\"; |
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232 case 3: /* memory from ARM register */ |
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233 return \"strh\\t%1, %0\\t%@ __fp16\"; |
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234 case 4: /* S register from S register */ |
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235 return \"fcpys\\t%0, %1\"; |
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236 case 5: /* ARM register from ARM register */ |
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237 return \"mov\\t%0, %1\\t%@ __fp16\"; |
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238 case 6: /* S register from ARM register */ |
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239 return \"fmsr\\t%0, %1\"; |
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240 case 7: /* ARM register from S register */ |
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241 return \"fmrs\\t%0, %1\"; |
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242 case 8: /* ARM register from constant */ |
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243 { |
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244 REAL_VALUE_TYPE r; |
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245 long bits; |
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246 rtx ops[4]; |
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247 |
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248 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); |
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249 bits = real_to_target (NULL, &r, HFmode); |
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250 ops[0] = operands[0]; |
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251 ops[1] = GEN_INT (bits); |
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252 ops[2] = GEN_INT (bits & 0xff00); |
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253 ops[3] = GEN_INT (bits & 0x00ff); |
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254 |
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255 if (arm_arch_thumb2) |
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256 output_asm_insn (\"movw\\t%0, %1\", ops); |
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257 else |
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258 output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops); |
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259 return \"\"; |
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260 } |
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261 default: |
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262 gcc_unreachable (); |
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263 } |
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264 " |
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265 [(set_attr "conds" "unconditional") |
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266 (set_attr "type" "*,*,load1,store1,fcpys,*,r_2_f,f_2_r,*") |
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267 (set_attr "neon_type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,*,*,*,*,*,*,*") |
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268 (set_attr "length" "4,4,4,4,4,4,4,4,8")] |
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269 ) |
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270 |
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271 ;; FP16 without element load/store instructions. |
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272 (define_insn "*movhf_vfp" |
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273 [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,t,r,t,r,r") |
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274 (match_operand:HF 1 "general_operand" " m,r,t,r,r,t,F"))] |
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275 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16 && !TARGET_NEON_FP16 |
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276 && ( s_register_operand (operands[0], HFmode) |
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277 || s_register_operand (operands[1], HFmode))" |
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278 "* |
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279 switch (which_alternative) |
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280 { |
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281 case 0: /* ARM register from memory */ |
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282 return \"ldrh\\t%0, %1\\t%@ __fp16\"; |
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283 case 1: /* memory from ARM register */ |
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284 return \"strh\\t%1, %0\\t%@ __fp16\"; |
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285 case 2: /* S register from S register */ |
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286 return \"fcpys\\t%0, %1\"; |
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287 case 3: /* ARM register from ARM register */ |
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288 return \"mov\\t%0, %1\\t%@ __fp16\"; |
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289 case 4: /* S register from ARM register */ |
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290 return \"fmsr\\t%0, %1\"; |
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291 case 5: /* ARM register from S register */ |
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292 return \"fmrs\\t%0, %1\"; |
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293 case 6: /* ARM register from constant */ |
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294 { |
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295 REAL_VALUE_TYPE r; |
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296 long bits; |
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297 rtx ops[4]; |
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298 |
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299 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); |
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300 bits = real_to_target (NULL, &r, HFmode); |
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301 ops[0] = operands[0]; |
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302 ops[1] = GEN_INT (bits); |
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303 ops[2] = GEN_INT (bits & 0xff00); |
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304 ops[3] = GEN_INT (bits & 0x00ff); |
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305 |
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306 if (arm_arch_thumb2) |
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307 output_asm_insn (\"movw\\t%0, %1\", ops); |
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308 else |
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309 output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops); |
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310 return \"\"; |
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311 } |
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312 default: |
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313 gcc_unreachable (); |
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314 } |
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315 " |
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316 [(set_attr "conds" "unconditional") |
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317 (set_attr "type" "load1,store1,fcpys,*,r_2_f,f_2_r,*") |
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318 (set_attr "length" "4,4,4,4,4,4,8")] |
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319 ) |
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320 |
| 0 | 321 |
| 322 ;; SFmode moves | |
| 323 ;; Disparage the w<->r cases because reloading an invalid address is | |
| 324 ;; preferable to loading the value via integer registers. | |
| 325 | |
| 326 (define_insn "*movsf_vfp" | |
| 327 [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t ,Uv,r ,m,t,r") | |
| 328 (match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))] | |
| 329 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP | |
| 330 && ( s_register_operand (operands[0], SFmode) | |
| 331 || s_register_operand (operands[1], SFmode))" | |
| 332 "* | |
| 333 switch (which_alternative) | |
| 334 { | |
| 335 case 0: | |
| 336 return \"fmsr%?\\t%0, %1\"; | |
| 337 case 1: | |
| 338 return \"fmrs%?\\t%0, %1\"; | |
| 339 case 2: | |
| 340 return \"fconsts%?\\t%0, #%G1\"; | |
| 341 case 3: case 4: | |
| 342 return output_move_vfp (operands); | |
| 343 case 5: | |
| 344 return \"ldr%?\\t%0, %1\\t%@ float\"; | |
| 345 case 6: | |
| 346 return \"str%?\\t%1, %0\\t%@ float\"; | |
| 347 case 7: | |
| 348 return \"fcpys%?\\t%0, %1\"; | |
| 349 case 8: | |
| 350 return \"mov%?\\t%0, %1\\t%@ float\"; | |
| 351 default: | |
| 352 gcc_unreachable (); | |
| 353 } | |
| 354 " | |
| 355 [(set_attr "predicable" "yes") | |
| 356 (set_attr "type" | |
| 357 "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*") | |
|
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358 (set_attr "insn" "*,*,*,*,*,*,*,*,mov") |
| 0 | 359 (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*") |
| 360 (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")] | |
| 361 ) | |
| 362 | |
| 363 (define_insn "*thumb2_movsf_vfp" | |
| 364 [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t ,Uv,r ,m,t,r") | |
| 365 (match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))] | |
| 366 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP | |
| 367 && ( s_register_operand (operands[0], SFmode) | |
| 368 || s_register_operand (operands[1], SFmode))" | |
| 369 "* | |
| 370 switch (which_alternative) | |
| 371 { | |
| 372 case 0: | |
| 373 return \"fmsr%?\\t%0, %1\"; | |
| 374 case 1: | |
| 375 return \"fmrs%?\\t%0, %1\"; | |
| 376 case 2: | |
| 377 return \"fconsts%?\\t%0, #%G1\"; | |
| 378 case 3: case 4: | |
| 379 return output_move_vfp (operands); | |
| 380 case 5: | |
| 381 return \"ldr%?\\t%0, %1\\t%@ float\"; | |
| 382 case 6: | |
| 383 return \"str%?\\t%1, %0\\t%@ float\"; | |
| 384 case 7: | |
| 385 return \"fcpys%?\\t%0, %1\"; | |
| 386 case 8: | |
| 387 return \"mov%?\\t%0, %1\\t%@ float\"; | |
| 388 default: | |
| 389 gcc_unreachable (); | |
| 390 } | |
| 391 " | |
| 392 [(set_attr "predicable" "yes") | |
| 393 (set_attr "type" | |
|
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394 "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*") |
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395 (set_attr "insn" "*,*,*,*,*,*,*,*,mov") |
| 0 | 396 (set_attr "pool_range" "*,*,*,1020,*,4092,*,*,*") |
| 397 (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")] | |
| 398 ) | |
| 399 | |
| 400 | |
| 401 ;; DFmode moves | |
| 402 | |
| 403 (define_insn "*movdf_vfp" | |
| 404 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r") | |
|
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405 (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))] |
| 0 | 406 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP |
| 407 && ( register_operand (operands[0], DFmode) | |
| 408 || register_operand (operands[1], DFmode))" | |
| 409 "* | |
| 410 { | |
| 411 switch (which_alternative) | |
| 412 { | |
| 413 case 0: | |
| 414 return \"fmdrr%?\\t%P0, %Q1, %R1\"; | |
| 415 case 1: | |
| 416 return \"fmrrd%?\\t%Q0, %R0, %P1\"; | |
| 417 case 2: | |
|
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418 gcc_assert (TARGET_VFP_DOUBLE); |
| 0 | 419 return \"fconstd%?\\t%P0, #%G1\"; |
| 420 case 3: case 4: | |
| 421 return output_move_double (operands); | |
| 422 case 5: case 6: | |
| 423 return output_move_vfp (operands); | |
| 424 case 7: | |
|
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425 if (TARGET_VFP_SINGLE) |
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426 return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\"; |
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427 else |
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428 return \"fcpyd%?\\t%P0, %P1\"; |
| 0 | 429 case 8: |
| 430 return \"#\"; | |
| 431 default: | |
| 432 gcc_unreachable (); | |
| 433 } | |
| 434 } | |
| 435 " | |
| 436 [(set_attr "type" | |
| 437 "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*") | |
|
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438 (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8) |
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439 (eq_attr "alternative" "7") |
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440 (if_then_else |
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441 (eq (symbol_ref "TARGET_VFP_SINGLE") |
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442 (const_int 1)) |
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443 (const_int 8) |
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444 (const_int 4))] |
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445 (const_int 4))) |
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446 (set_attr "predicable" "yes") |
| 0 | 447 (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*") |
| 448 (set_attr "neg_pool_range" "*,*,*,1008,*,1008,*,*,*")] | |
| 449 ) | |
| 450 | |
| 451 (define_insn "*thumb2_movdf_vfp" | |
| 452 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r") | |
|
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453 (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))] |
| 0 | 454 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP" |
| 455 "* | |
| 456 { | |
| 457 switch (which_alternative) | |
| 458 { | |
| 459 case 0: | |
| 460 return \"fmdrr%?\\t%P0, %Q1, %R1\"; | |
| 461 case 1: | |
| 462 return \"fmrrd%?\\t%Q0, %R0, %P1\"; | |
| 463 case 2: | |
|
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464 gcc_assert (TARGET_VFP_DOUBLE); |
| 0 | 465 return \"fconstd%?\\t%P0, #%G1\"; |
| 466 case 3: case 4: case 8: | |
| 467 return output_move_double (operands); | |
| 468 case 5: case 6: | |
| 469 return output_move_vfp (operands); | |
| 470 case 7: | |
|
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471 if (TARGET_VFP_SINGLE) |
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472 return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\"; |
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473 else |
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474 return \"fcpyd%?\\t%P0, %P1\"; |
| 0 | 475 default: |
| 476 abort (); | |
| 477 } | |
| 478 } | |
| 479 " | |
| 480 [(set_attr "type" | |
|
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481 "r_2_f,f_2_r,fconstd,load2,store2,f_loadd,f_stored,ffarithd,*") |
|
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482 (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8) |
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483 (eq_attr "alternative" "7") |
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484 (if_then_else |
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485 (eq (symbol_ref "TARGET_VFP_SINGLE") |
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486 (const_int 1)) |
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487 (const_int 8) |
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488 (const_int 4))] |
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489 (const_int 4))) |
| 0 | 490 (set_attr "pool_range" "*,*,*,4096,*,1020,*,*,*") |
| 491 (set_attr "neg_pool_range" "*,*,*,0,*,1008,*,*,*")] | |
| 492 ) | |
| 493 | |
| 494 | |
| 495 ;; Conditional move patterns | |
| 496 | |
| 497 (define_insn "*movsfcc_vfp" | |
| 498 [(set (match_operand:SF 0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r") | |
| 499 (if_then_else:SF | |
| 500 (match_operator 3 "arm_comparison_operator" | |
| 501 [(match_operand 4 "cc_register" "") (const_int 0)]) | |
| 502 (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t") | |
| 503 (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))] | |
| 504 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 505 "@ | |
| 506 fcpys%D3\\t%0, %2 | |
| 507 fcpys%d3\\t%0, %1 | |
| 508 fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1 | |
| 509 fmsr%D3\\t%0, %2 | |
| 510 fmsr%d3\\t%0, %1 | |
| 511 fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1 | |
| 512 fmrs%D3\\t%0, %2 | |
| 513 fmrs%d3\\t%0, %1 | |
| 514 fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1" | |
| 515 [(set_attr "conds" "use") | |
| 516 (set_attr "length" "4,4,8,4,4,8,4,4,8") | |
| 517 (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] | |
| 518 ) | |
| 519 | |
| 520 (define_insn "*thumb2_movsfcc_vfp" | |
| 521 [(set (match_operand:SF 0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r") | |
| 522 (if_then_else:SF | |
| 523 (match_operator 3 "arm_comparison_operator" | |
| 524 [(match_operand 4 "cc_register" "") (const_int 0)]) | |
| 525 (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t") | |
| 526 (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))] | |
| 527 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 528 "@ | |
| 529 it\\t%D3\;fcpys%D3\\t%0, %2 | |
| 530 it\\t%d3\;fcpys%d3\\t%0, %1 | |
| 531 ite\\t%D3\;fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1 | |
| 532 it\\t%D3\;fmsr%D3\\t%0, %2 | |
| 533 it\\t%d3\;fmsr%d3\\t%0, %1 | |
| 534 ite\\t%D3\;fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1 | |
| 535 it\\t%D3\;fmrs%D3\\t%0, %2 | |
| 536 it\\t%d3\;fmrs%d3\\t%0, %1 | |
| 537 ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1" | |
| 538 [(set_attr "conds" "use") | |
| 539 (set_attr "length" "6,6,10,6,6,10,6,6,10") | |
| 540 (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] | |
| 541 ) | |
| 542 | |
| 543 (define_insn "*movdfcc_vfp" | |
| 544 [(set (match_operand:DF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r") | |
| 545 (if_then_else:DF | |
| 546 (match_operator 3 "arm_comparison_operator" | |
| 547 [(match_operand 4 "cc_register" "") (const_int 0)]) | |
| 548 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w") | |
| 549 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))] | |
|
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550 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 551 "@ |
| 552 fcpyd%D3\\t%P0, %P2 | |
| 553 fcpyd%d3\\t%P0, %P1 | |
| 554 fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1 | |
| 555 fmdrr%D3\\t%P0, %Q2, %R2 | |
| 556 fmdrr%d3\\t%P0, %Q1, %R1 | |
| 557 fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1 | |
| 558 fmrrd%D3\\t%Q0, %R0, %P2 | |
| 559 fmrrd%d3\\t%Q0, %R0, %P1 | |
| 560 fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1" | |
| 561 [(set_attr "conds" "use") | |
| 562 (set_attr "length" "4,4,8,4,4,8,4,4,8") | |
| 563 (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] | |
| 564 ) | |
| 565 | |
| 566 (define_insn "*thumb2_movdfcc_vfp" | |
| 567 [(set (match_operand:DF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r") | |
| 568 (if_then_else:DF | |
| 569 (match_operator 3 "arm_comparison_operator" | |
| 570 [(match_operand 4 "cc_register" "") (const_int 0)]) | |
| 571 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w") | |
| 572 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))] | |
|
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573 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 574 "@ |
| 575 it\\t%D3\;fcpyd%D3\\t%P0, %P2 | |
| 576 it\\t%d3\;fcpyd%d3\\t%P0, %P1 | |
| 577 ite\\t%D3\;fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1 | |
| 578 it\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2 | |
| 579 it\t%d3\;fmdrr%d3\\t%P0, %Q1, %R1 | |
| 580 ite\\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1 | |
| 581 it\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2 | |
| 582 it\t%d3\;fmrrd%d3\\t%Q0, %R0, %P1 | |
| 583 ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1" | |
| 584 [(set_attr "conds" "use") | |
| 585 (set_attr "length" "6,6,10,6,6,10,6,6,10") | |
| 586 (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] | |
| 587 ) | |
| 588 | |
| 589 | |
| 590 ;; Sign manipulation functions | |
| 591 | |
| 592 (define_insn "*abssf2_vfp" | |
| 593 [(set (match_operand:SF 0 "s_register_operand" "=t") | |
| 594 (abs:SF (match_operand:SF 1 "s_register_operand" "t")))] | |
| 595 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 596 "fabss%?\\t%0, %1" | |
| 597 [(set_attr "predicable" "yes") | |
| 598 (set_attr "type" "ffariths")] | |
| 599 ) | |
| 600 | |
| 601 (define_insn "*absdf2_vfp" | |
| 602 [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 603 (abs:DF (match_operand:DF 1 "s_register_operand" "w")))] | |
|
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604 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 605 "fabsd%?\\t%P0, %P1" |
| 606 [(set_attr "predicable" "yes") | |
| 607 (set_attr "type" "ffarithd")] | |
| 608 ) | |
| 609 | |
| 610 (define_insn "*negsf2_vfp" | |
| 611 [(set (match_operand:SF 0 "s_register_operand" "=t,?r") | |
| 612 (neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))] | |
| 613 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 614 "@ | |
| 615 fnegs%?\\t%0, %1 | |
| 616 eor%?\\t%0, %1, #-2147483648" | |
| 617 [(set_attr "predicable" "yes") | |
| 618 (set_attr "type" "ffariths")] | |
| 619 ) | |
| 620 | |
| 621 (define_insn_and_split "*negdf2_vfp" | |
| 622 [(set (match_operand:DF 0 "s_register_operand" "=w,?r,?r") | |
| 623 (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))] | |
|
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624 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 625 "@ |
| 626 fnegd%?\\t%P0, %P1 | |
| 627 # | |
| 628 #" | |
|
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629 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && reload_completed |
| 0 | 630 && arm_general_register_operand (operands[0], DFmode)" |
| 631 [(set (match_dup 0) (match_dup 1))] | |
| 632 " | |
| 633 if (REGNO (operands[0]) == REGNO (operands[1])) | |
| 634 { | |
| 635 operands[0] = gen_highpart (SImode, operands[0]); | |
| 636 operands[1] = gen_rtx_XOR (SImode, operands[0], GEN_INT (0x80000000)); | |
| 637 } | |
| 638 else | |
| 639 { | |
| 640 rtx in_hi, in_lo, out_hi, out_lo; | |
| 641 | |
| 642 in_hi = gen_rtx_XOR (SImode, gen_highpart (SImode, operands[1]), | |
| 643 GEN_INT (0x80000000)); | |
| 644 in_lo = gen_lowpart (SImode, operands[1]); | |
| 645 out_hi = gen_highpart (SImode, operands[0]); | |
| 646 out_lo = gen_lowpart (SImode, operands[0]); | |
| 647 | |
| 648 if (REGNO (in_lo) == REGNO (out_hi)) | |
| 649 { | |
| 650 emit_insn (gen_rtx_SET (SImode, out_lo, in_lo)); | |
| 651 operands[0] = out_hi; | |
| 652 operands[1] = in_hi; | |
| 653 } | |
| 654 else | |
| 655 { | |
| 656 emit_insn (gen_rtx_SET (SImode, out_hi, in_hi)); | |
| 657 operands[0] = out_lo; | |
| 658 operands[1] = in_lo; | |
| 659 } | |
| 660 } | |
| 661 " | |
| 662 [(set_attr "predicable" "yes") | |
| 663 (set_attr "length" "4,4,8") | |
| 664 (set_attr "type" "ffarithd")] | |
| 665 ) | |
| 666 | |
| 667 | |
| 668 ;; Arithmetic insns | |
| 669 | |
| 670 (define_insn "*addsf3_vfp" | |
| 671 [(set (match_operand:SF 0 "s_register_operand" "=t") | |
| 672 (plus:SF (match_operand:SF 1 "s_register_operand" "t") | |
| 673 (match_operand:SF 2 "s_register_operand" "t")))] | |
| 674 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 675 "fadds%?\\t%0, %1, %2" | |
| 676 [(set_attr "predicable" "yes") | |
| 677 (set_attr "type" "fadds")] | |
| 678 ) | |
| 679 | |
| 680 (define_insn "*adddf3_vfp" | |
| 681 [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 682 (plus:DF (match_operand:DF 1 "s_register_operand" "w") | |
| 683 (match_operand:DF 2 "s_register_operand" "w")))] | |
|
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684 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 685 "faddd%?\\t%P0, %P1, %P2" |
| 686 [(set_attr "predicable" "yes") | |
| 687 (set_attr "type" "faddd")] | |
| 688 ) | |
| 689 | |
| 690 | |
| 691 (define_insn "*subsf3_vfp" | |
| 692 [(set (match_operand:SF 0 "s_register_operand" "=t") | |
| 693 (minus:SF (match_operand:SF 1 "s_register_operand" "t") | |
| 694 (match_operand:SF 2 "s_register_operand" "t")))] | |
| 695 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 696 "fsubs%?\\t%0, %1, %2" | |
| 697 [(set_attr "predicable" "yes") | |
| 698 (set_attr "type" "fadds")] | |
| 699 ) | |
| 700 | |
| 701 (define_insn "*subdf3_vfp" | |
| 702 [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 703 (minus:DF (match_operand:DF 1 "s_register_operand" "w") | |
| 704 (match_operand:DF 2 "s_register_operand" "w")))] | |
|
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705 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 706 "fsubd%?\\t%P0, %P1, %P2" |
| 707 [(set_attr "predicable" "yes") | |
| 708 (set_attr "type" "faddd")] | |
| 709 ) | |
| 710 | |
| 711 | |
| 712 ;; Division insns | |
| 713 | |
| 714 (define_insn "*divsf3_vfp" | |
| 715 [(set (match_operand:SF 0 "s_register_operand" "+t") | |
| 716 (div:SF (match_operand:SF 1 "s_register_operand" "t") | |
| 717 (match_operand:SF 2 "s_register_operand" "t")))] | |
| 718 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 719 "fdivs%?\\t%0, %1, %2" | |
| 720 [(set_attr "predicable" "yes") | |
| 721 (set_attr "type" "fdivs")] | |
| 722 ) | |
| 723 | |
| 724 (define_insn "*divdf3_vfp" | |
| 725 [(set (match_operand:DF 0 "s_register_operand" "+w") | |
| 726 (div:DF (match_operand:DF 1 "s_register_operand" "w") | |
| 727 (match_operand:DF 2 "s_register_operand" "w")))] | |
|
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728 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 729 "fdivd%?\\t%P0, %P1, %P2" |
| 730 [(set_attr "predicable" "yes") | |
| 731 (set_attr "type" "fdivd")] | |
| 732 ) | |
| 733 | |
| 734 | |
| 735 ;; Multiplication insns | |
| 736 | |
| 737 (define_insn "*mulsf3_vfp" | |
| 738 [(set (match_operand:SF 0 "s_register_operand" "+t") | |
| 739 (mult:SF (match_operand:SF 1 "s_register_operand" "t") | |
| 740 (match_operand:SF 2 "s_register_operand" "t")))] | |
| 741 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 742 "fmuls%?\\t%0, %1, %2" | |
| 743 [(set_attr "predicable" "yes") | |
| 744 (set_attr "type" "fmuls")] | |
| 745 ) | |
| 746 | |
| 747 (define_insn "*muldf3_vfp" | |
| 748 [(set (match_operand:DF 0 "s_register_operand" "+w") | |
| 749 (mult:DF (match_operand:DF 1 "s_register_operand" "w") | |
| 750 (match_operand:DF 2 "s_register_operand" "w")))] | |
|
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751 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 752 "fmuld%?\\t%P0, %P1, %P2" |
| 753 [(set_attr "predicable" "yes") | |
| 754 (set_attr "type" "fmuld")] | |
| 755 ) | |
| 756 | |
| 757 | |
| 758 (define_insn "*mulsf3negsf_vfp" | |
| 759 [(set (match_operand:SF 0 "s_register_operand" "+t") | |
| 760 (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t")) | |
| 761 (match_operand:SF 2 "s_register_operand" "t")))] | |
| 762 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 763 "fnmuls%?\\t%0, %1, %2" | |
| 764 [(set_attr "predicable" "yes") | |
| 765 (set_attr "type" "fmuls")] | |
| 766 ) | |
| 767 | |
| 768 (define_insn "*muldf3negdf_vfp" | |
| 769 [(set (match_operand:DF 0 "s_register_operand" "+w") | |
| 770 (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w")) | |
| 771 (match_operand:DF 2 "s_register_operand" "w")))] | |
|
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772 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 773 "fnmuld%?\\t%P0, %P1, %P2" |
| 774 [(set_attr "predicable" "yes") | |
| 775 (set_attr "type" "fmuld")] | |
| 776 ) | |
| 777 | |
| 778 | |
| 779 ;; Multiply-accumulate insns | |
| 780 | |
| 781 ;; 0 = 1 * 2 + 0 | |
| 782 (define_insn "*mulsf3addsf_vfp" | |
| 783 [(set (match_operand:SF 0 "s_register_operand" "=t") | |
| 784 (plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t") | |
| 785 (match_operand:SF 3 "s_register_operand" "t")) | |
| 786 (match_operand:SF 1 "s_register_operand" "0")))] | |
| 787 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 788 "fmacs%?\\t%0, %2, %3" | |
| 789 [(set_attr "predicable" "yes") | |
| 790 (set_attr "type" "fmacs")] | |
| 791 ) | |
| 792 | |
| 793 (define_insn "*muldf3adddf_vfp" | |
| 794 [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 795 (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w") | |
| 796 (match_operand:DF 3 "s_register_operand" "w")) | |
| 797 (match_operand:DF 1 "s_register_operand" "0")))] | |
|
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798 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 799 "fmacd%?\\t%P0, %P2, %P3" |
| 800 [(set_attr "predicable" "yes") | |
| 801 (set_attr "type" "fmacd")] | |
| 802 ) | |
| 803 | |
| 804 ;; 0 = 1 * 2 - 0 | |
| 805 (define_insn "*mulsf3subsf_vfp" | |
| 806 [(set (match_operand:SF 0 "s_register_operand" "=t") | |
| 807 (minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t") | |
| 808 (match_operand:SF 3 "s_register_operand" "t")) | |
| 809 (match_operand:SF 1 "s_register_operand" "0")))] | |
| 810 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 811 "fmscs%?\\t%0, %2, %3" | |
| 812 [(set_attr "predicable" "yes") | |
| 813 (set_attr "type" "fmacs")] | |
| 814 ) | |
| 815 | |
| 816 (define_insn "*muldf3subdf_vfp" | |
| 817 [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 818 (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w") | |
| 819 (match_operand:DF 3 "s_register_operand" "w")) | |
| 820 (match_operand:DF 1 "s_register_operand" "0")))] | |
|
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821 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 822 "fmscd%?\\t%P0, %P2, %P3" |
| 823 [(set_attr "predicable" "yes") | |
| 824 (set_attr "type" "fmacd")] | |
| 825 ) | |
| 826 | |
| 827 ;; 0 = -(1 * 2) + 0 | |
| 828 (define_insn "*mulsf3negsfaddsf_vfp" | |
| 829 [(set (match_operand:SF 0 "s_register_operand" "=t") | |
| 830 (minus:SF (match_operand:SF 1 "s_register_operand" "0") | |
| 831 (mult:SF (match_operand:SF 2 "s_register_operand" "t") | |
| 832 (match_operand:SF 3 "s_register_operand" "t"))))] | |
| 833 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 834 "fnmacs%?\\t%0, %2, %3" | |
| 835 [(set_attr "predicable" "yes") | |
| 836 (set_attr "type" "fmacs")] | |
| 837 ) | |
| 838 | |
| 839 (define_insn "*fmuldf3negdfadddf_vfp" | |
| 840 [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 841 (minus:DF (match_operand:DF 1 "s_register_operand" "0") | |
| 842 (mult:DF (match_operand:DF 2 "s_register_operand" "w") | |
| 843 (match_operand:DF 3 "s_register_operand" "w"))))] | |
|
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844 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 845 "fnmacd%?\\t%P0, %P2, %P3" |
| 846 [(set_attr "predicable" "yes") | |
| 847 (set_attr "type" "fmacd")] | |
| 848 ) | |
| 849 | |
| 850 | |
| 851 ;; 0 = -(1 * 2) - 0 | |
| 852 (define_insn "*mulsf3negsfsubsf_vfp" | |
| 853 [(set (match_operand:SF 0 "s_register_operand" "=t") | |
| 854 (minus:SF (mult:SF | |
| 855 (neg:SF (match_operand:SF 2 "s_register_operand" "t")) | |
| 856 (match_operand:SF 3 "s_register_operand" "t")) | |
| 857 (match_operand:SF 1 "s_register_operand" "0")))] | |
| 858 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 859 "fnmscs%?\\t%0, %2, %3" | |
| 860 [(set_attr "predicable" "yes") | |
| 861 (set_attr "type" "fmacs")] | |
| 862 ) | |
| 863 | |
| 864 (define_insn "*muldf3negdfsubdf_vfp" | |
| 865 [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 866 (minus:DF (mult:DF | |
| 867 (neg:DF (match_operand:DF 2 "s_register_operand" "w")) | |
| 868 (match_operand:DF 3 "s_register_operand" "w")) | |
| 869 (match_operand:DF 1 "s_register_operand" "0")))] | |
|
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870 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 871 "fnmscd%?\\t%P0, %P2, %P3" |
| 872 [(set_attr "predicable" "yes") | |
| 873 (set_attr "type" "fmacd")] | |
| 874 ) | |
| 875 | |
| 876 | |
| 877 ;; Conversion routines | |
| 878 | |
| 879 (define_insn "*extendsfdf2_vfp" | |
| 880 [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 881 (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))] | |
|
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882 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 883 "fcvtds%?\\t%P0, %1" |
| 884 [(set_attr "predicable" "yes") | |
| 885 (set_attr "type" "f_cvt")] | |
| 886 ) | |
| 887 | |
| 888 (define_insn "*truncdfsf2_vfp" | |
| 889 [(set (match_operand:SF 0 "s_register_operand" "=t") | |
| 890 (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))] | |
|
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891 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 892 "fcvtsd%?\\t%0, %P1" |
| 893 [(set_attr "predicable" "yes") | |
| 894 (set_attr "type" "f_cvt")] | |
| 895 ) | |
| 896 | |
|
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897 (define_insn "extendhfsf2" |
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898 [(set (match_operand:SF 0 "s_register_operand" "=t") |
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899 (float_extend:SF (match_operand:HF 1 "s_register_operand" "t")))] |
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900 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16" |
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901 "vcvtb%?.f32.f16\\t%0, %1" |
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902 [(set_attr "predicable" "yes") |
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903 (set_attr "type" "f_cvt")] |
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904 ) |
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905 |
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906 (define_insn "truncsfhf2" |
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907 [(set (match_operand:HF 0 "s_register_operand" "=t") |
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908 (float_truncate:HF (match_operand:SF 1 "s_register_operand" "t")))] |
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909 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16" |
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910 "vcvtb%?.f16.f32\\t%0, %1" |
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911 [(set_attr "predicable" "yes") |
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912 (set_attr "type" "f_cvt")] |
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913 ) |
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914 |
| 0 | 915 (define_insn "*truncsisf2_vfp" |
| 916 [(set (match_operand:SI 0 "s_register_operand" "=t") | |
| 917 (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))] | |
| 918 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 919 "ftosizs%?\\t%0, %1" | |
| 920 [(set_attr "predicable" "yes") | |
| 921 (set_attr "type" "f_cvt")] | |
| 922 ) | |
| 923 | |
| 924 (define_insn "*truncsidf2_vfp" | |
| 925 [(set (match_operand:SI 0 "s_register_operand" "=t") | |
| 926 (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))] | |
|
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927 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 928 "ftosizd%?\\t%0, %P1" |
| 929 [(set_attr "predicable" "yes") | |
| 930 (set_attr "type" "f_cvt")] | |
| 931 ) | |
| 932 | |
| 933 | |
| 934 (define_insn "fixuns_truncsfsi2" | |
| 935 [(set (match_operand:SI 0 "s_register_operand" "=t") | |
| 936 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))] | |
| 937 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 938 "ftouizs%?\\t%0, %1" | |
| 939 [(set_attr "predicable" "yes") | |
| 940 (set_attr "type" "f_cvt")] | |
| 941 ) | |
| 942 | |
| 943 (define_insn "fixuns_truncdfsi2" | |
| 944 [(set (match_operand:SI 0 "s_register_operand" "=t") | |
| 945 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))] | |
|
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946 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 947 "ftouizd%?\\t%0, %P1" |
| 948 [(set_attr "predicable" "yes") | |
| 949 (set_attr "type" "f_cvt")] | |
| 950 ) | |
| 951 | |
| 952 | |
| 953 (define_insn "*floatsisf2_vfp" | |
| 954 [(set (match_operand:SF 0 "s_register_operand" "=t") | |
| 955 (float:SF (match_operand:SI 1 "s_register_operand" "t")))] | |
| 956 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 957 "fsitos%?\\t%0, %1" | |
| 958 [(set_attr "predicable" "yes") | |
| 959 (set_attr "type" "f_cvt")] | |
| 960 ) | |
| 961 | |
| 962 (define_insn "*floatsidf2_vfp" | |
| 963 [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 964 (float:DF (match_operand:SI 1 "s_register_operand" "t")))] | |
|
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965 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 966 "fsitod%?\\t%P0, %1" |
| 967 [(set_attr "predicable" "yes") | |
| 968 (set_attr "type" "f_cvt")] | |
| 969 ) | |
| 970 | |
| 971 | |
| 972 (define_insn "floatunssisf2" | |
| 973 [(set (match_operand:SF 0 "s_register_operand" "=t") | |
| 974 (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))] | |
| 975 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 976 "fuitos%?\\t%0, %1" | |
| 977 [(set_attr "predicable" "yes") | |
| 978 (set_attr "type" "f_cvt")] | |
| 979 ) | |
| 980 | |
| 981 (define_insn "floatunssidf2" | |
| 982 [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 983 (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))] | |
|
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984 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 985 "fuitod%?\\t%P0, %1" |
| 986 [(set_attr "predicable" "yes") | |
| 987 (set_attr "type" "f_cvt")] | |
| 988 ) | |
| 989 | |
| 990 | |
| 991 ;; Sqrt insns. | |
| 992 | |
| 993 (define_insn "*sqrtsf2_vfp" | |
| 994 [(set (match_operand:SF 0 "s_register_operand" "=t") | |
| 995 (sqrt:SF (match_operand:SF 1 "s_register_operand" "t")))] | |
| 996 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 997 "fsqrts%?\\t%0, %1" | |
| 998 [(set_attr "predicable" "yes") | |
| 999 (set_attr "type" "fdivs")] | |
| 1000 ) | |
| 1001 | |
| 1002 (define_insn "*sqrtdf2_vfp" | |
| 1003 [(set (match_operand:DF 0 "s_register_operand" "=w") | |
| 1004 (sqrt:DF (match_operand:DF 1 "s_register_operand" "w")))] | |
|
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1005 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 1006 "fsqrtd%?\\t%P0, %P1" |
| 1007 [(set_attr "predicable" "yes") | |
| 1008 (set_attr "type" "fdivd")] | |
| 1009 ) | |
| 1010 | |
| 1011 | |
| 1012 ;; Patterns to split/copy vfp condition flags. | |
| 1013 | |
| 1014 (define_insn "*movcc_vfp" | |
| 1015 [(set (reg CC_REGNUM) | |
| 1016 (reg VFPCC_REGNUM))] | |
| 1017 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 1018 "fmstat%?" | |
| 1019 [(set_attr "conds" "set") | |
| 1020 (set_attr "type" "f_flag")] | |
| 1021 ) | |
| 1022 | |
| 1023 (define_insn_and_split "*cmpsf_split_vfp" | |
| 1024 [(set (reg:CCFP CC_REGNUM) | |
| 1025 (compare:CCFP (match_operand:SF 0 "s_register_operand" "t") | |
| 1026 (match_operand:SF 1 "vfp_compare_operand" "tG")))] | |
| 1027 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 1028 "#" | |
| 1029 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 1030 [(set (reg:CCFP VFPCC_REGNUM) | |
| 1031 (compare:CCFP (match_dup 0) | |
| 1032 (match_dup 1))) | |
| 1033 (set (reg:CCFP CC_REGNUM) | |
| 1034 (reg:CCFP VFPCC_REGNUM))] | |
| 1035 "" | |
| 1036 ) | |
| 1037 | |
| 1038 (define_insn_and_split "*cmpsf_trap_split_vfp" | |
| 1039 [(set (reg:CCFPE CC_REGNUM) | |
| 1040 (compare:CCFPE (match_operand:SF 0 "s_register_operand" "t") | |
| 1041 (match_operand:SF 1 "vfp_compare_operand" "tG")))] | |
| 1042 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 1043 "#" | |
| 1044 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 1045 [(set (reg:CCFPE VFPCC_REGNUM) | |
| 1046 (compare:CCFPE (match_dup 0) | |
| 1047 (match_dup 1))) | |
| 1048 (set (reg:CCFPE CC_REGNUM) | |
| 1049 (reg:CCFPE VFPCC_REGNUM))] | |
| 1050 "" | |
| 1051 ) | |
| 1052 | |
| 1053 (define_insn_and_split "*cmpdf_split_vfp" | |
| 1054 [(set (reg:CCFP CC_REGNUM) | |
| 1055 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w") | |
| 1056 (match_operand:DF 1 "vfp_compare_operand" "wG")))] | |
|
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1057 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 1058 "#" |
|
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1059 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 1060 [(set (reg:CCFP VFPCC_REGNUM) |
| 1061 (compare:CCFP (match_dup 0) | |
| 1062 (match_dup 1))) | |
| 1063 (set (reg:CCFP CC_REGNUM) | |
|
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1064 (reg:CCFP VFPCC_REGNUM))] |
| 0 | 1065 "" |
| 1066 ) | |
| 1067 | |
| 1068 (define_insn_and_split "*cmpdf_trap_split_vfp" | |
| 1069 [(set (reg:CCFPE CC_REGNUM) | |
| 1070 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w") | |
| 1071 (match_operand:DF 1 "vfp_compare_operand" "wG")))] | |
|
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1072 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 1073 "#" |
|
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1074 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 1075 [(set (reg:CCFPE VFPCC_REGNUM) |
| 1076 (compare:CCFPE (match_dup 0) | |
| 1077 (match_dup 1))) | |
| 1078 (set (reg:CCFPE CC_REGNUM) | |
| 1079 (reg:CCFPE VFPCC_REGNUM))] | |
| 1080 "" | |
| 1081 ) | |
| 1082 | |
| 1083 | |
| 1084 ;; Comparison patterns | |
| 1085 | |
| 1086 (define_insn "*cmpsf_vfp" | |
| 1087 [(set (reg:CCFP VFPCC_REGNUM) | |
| 1088 (compare:CCFP (match_operand:SF 0 "s_register_operand" "t,t") | |
| 1089 (match_operand:SF 1 "vfp_compare_operand" "t,G")))] | |
| 1090 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 1091 "@ | |
| 1092 fcmps%?\\t%0, %1 | |
| 1093 fcmpzs%?\\t%0" | |
| 1094 [(set_attr "predicable" "yes") | |
| 1095 (set_attr "type" "fcmps")] | |
| 1096 ) | |
| 1097 | |
| 1098 (define_insn "*cmpsf_trap_vfp" | |
| 1099 [(set (reg:CCFPE VFPCC_REGNUM) | |
| 1100 (compare:CCFPE (match_operand:SF 0 "s_register_operand" "t,t") | |
| 1101 (match_operand:SF 1 "vfp_compare_operand" "t,G")))] | |
| 1102 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 1103 "@ | |
| 1104 fcmpes%?\\t%0, %1 | |
| 1105 fcmpezs%?\\t%0" | |
| 1106 [(set_attr "predicable" "yes") | |
|
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1107 (set_attr "type" "fcmps")] |
| 0 | 1108 ) |
| 1109 | |
| 1110 (define_insn "*cmpdf_vfp" | |
| 1111 [(set (reg:CCFP VFPCC_REGNUM) | |
| 1112 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w,w") | |
| 1113 (match_operand:DF 1 "vfp_compare_operand" "w,G")))] | |
|
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1114 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 1115 "@ |
| 1116 fcmpd%?\\t%P0, %P1 | |
| 1117 fcmpzd%?\\t%P0" | |
| 1118 [(set_attr "predicable" "yes") | |
| 1119 (set_attr "type" "fcmpd")] | |
| 1120 ) | |
| 1121 | |
| 1122 (define_insn "*cmpdf_trap_vfp" | |
| 1123 [(set (reg:CCFPE VFPCC_REGNUM) | |
| 1124 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w,w") | |
| 1125 (match_operand:DF 1 "vfp_compare_operand" "w,G")))] | |
|
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1126 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" |
| 0 | 1127 "@ |
| 1128 fcmped%?\\t%P0, %P1 | |
| 1129 fcmpezd%?\\t%P0" | |
| 1130 [(set_attr "predicable" "yes") | |
| 1131 (set_attr "type" "fcmpd")] | |
| 1132 ) | |
| 1133 | |
| 1134 | |
| 1135 ;; Store multiple insn used in function prologue. | |
| 1136 | |
| 1137 (define_insn "*push_multi_vfp" | |
| 1138 [(match_parallel 2 "multi_register_push" | |
| 1139 [(set (match_operand:BLK 0 "memory_operand" "=m") | |
|
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1140 (unspec:BLK [(match_operand:DF 1 "vfp_register_operand" "")] |
| 0 | 1141 UNSPEC_PUSH_MULT))])] |
| 1142 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" | |
| 1143 "* return vfp_output_fstmd (operands);" | |
| 1144 [(set_attr "type" "f_stored")] | |
| 1145 ) | |
| 1146 | |
| 1147 | |
| 1148 ;; Unimplemented insns: | |
| 1149 ;; fldm* | |
| 1150 ;; fstm* | |
| 1151 ;; fmdhr et al (VFPv1) | |
| 1152 ;; Support for xD (single precision only) variants. | |
| 1153 ;; fmrrs, fmsrr |