Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/iq2000/iq2000.md @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
| author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 22 Mar 2011 17:18:12 +0900 |
| parents | 77e2b8dfacca |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
| 0 | 1 ;; iq2000.md Machine Description for Vitesse IQ2000 processors |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2 ;; Copyright (C) 2003, 2004, 2005, 2007, 2010 Free Software Foundation, Inc. |
| 0 | 3 |
| 4 ;; This file is part of GCC. | |
| 5 | |
| 6 ;; GCC is free software; you can redistribute it and/or modify | |
| 7 ;; it under the terms of the GNU General Public License as published by | |
| 8 ;; the Free Software Foundation; either version 3, or (at your option) | |
| 9 ;; any later version. | |
| 10 | |
| 11 ;; GCC is distributed in the hope that it will be useful, | |
| 12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 ;; GNU General Public License for more details. | |
| 15 | |
| 16 ;; You should have received a copy of the GNU General Public License | |
| 17 ;; along with GCC; see the file COPYING3. If not see | |
| 18 ;; <http://www.gnu.org/licenses/>. | |
| 19 | |
| 20 (define_constants | |
| 21 [(UNSPEC_ADO16 0) | |
| 22 (UNSPEC_RAM 1) | |
| 23 (UNSPEC_CHKHDR 2) | |
| 24 (UNSPEC_PKRL 3) | |
| 25 (UNSPEC_CFC0 4) | |
| 26 (UNSPEC_CFC1 5) | |
| 27 (UNSPEC_CFC2 6) | |
| 28 (UNSPEC_CFC3 7) | |
| 29 (UNSPEC_CTC0 8) | |
| 30 (UNSPEC_CTC1 9) | |
| 31 (UNSPEC_CTC2 10) | |
| 32 (UNSPEC_CTC3 11) | |
| 33 (UNSPEC_MFC0 12) | |
| 34 (UNSPEC_MFC1 13) | |
| 35 (UNSPEC_MFC2 14) | |
| 36 (UNSPEC_MFC3 15) | |
| 37 (UNSPEC_MTC0 16) | |
| 38 (UNSPEC_MTC1 17) | |
| 39 (UNSPEC_MTC2 18) | |
| 40 (UNSPEC_MTC3 19) | |
| 41 (UNSPEC_LUR 20) | |
| 42 (UNSPEC_RB 21) | |
| 43 (UNSPEC_RX 22) | |
| 44 (UNSPEC_SRRD 23) | |
| 45 (UNSPEC_SRWR 24) | |
| 46 (UNSPEC_WB 25) | |
| 47 (UNSPEC_WX 26) | |
| 48 (UNSPEC_LUC32 49) | |
| 49 (UNSPEC_LUC32L 27) | |
| 50 (UNSPEC_LUC64 28) | |
| 51 (UNSPEC_LUC64L 29) | |
| 52 (UNSPEC_LUK 30) | |
| 53 (UNSPEC_LULCK 31) | |
| 54 (UNSPEC_LUM32 32) | |
| 55 (UNSPEC_LUM32L 33) | |
| 56 (UNSPEC_LUM64 34) | |
| 57 (UNSPEC_LUM64L 35) | |
| 58 (UNSPEC_LURL 36) | |
| 59 (UNSPEC_MRGB 37) | |
| 60 (UNSPEC_SRRDL 38) | |
| 61 (UNSPEC_SRULCK 39) | |
| 62 (UNSPEC_SRWRU 40) | |
| 63 (UNSPEC_TRAPQFL 41) | |
| 64 (UNSPEC_TRAPQNE 42) | |
| 65 (UNSPEC_TRAPREL 43) | |
| 66 (UNSPEC_WBU 44) | |
| 67 (UNSPEC_SYSCALL 45)] | |
| 68 ) | |
| 69 ;; UNSPEC values used in iq2000.md | |
| 70 ;; Number USE | |
| 71 ;; 0 movsi_ul | |
| 72 ;; 1 movsi_us, get_fnaddr | |
| 73 ;; 3 eh_set_return | |
| 74 ;; 20 builtin_setjmp_setup | |
| 75 ;; | |
| 76 ;; UNSPEC_VOLATILE values | |
| 77 ;; 0 blockage | |
| 78 ;; 2 loadgp | |
| 79 ;; 3 builtin_longjmp | |
| 80 ;; 4 exception_receiver | |
| 81 ;; 10 consttable_qi | |
| 82 ;; 11 consttable_hi | |
| 83 ;; 12 consttable_si | |
| 84 ;; 13 consttable_di | |
| 85 ;; 14 consttable_sf | |
| 86 ;; 15 consttable_df | |
| 87 ;; 16 align_2 | |
| 88 ;; 17 align_4 | |
| 89 ;; 18 align_8 | |
| 90 | |
| 91 | |
| 92 ;; .................... | |
| 93 ;; | |
| 94 ;; Attributes | |
| 95 ;; | |
| 96 ;; .................... | |
| 97 | |
| 98 ;; Classification of each insn. | |
| 99 ;; branch conditional branch | |
| 100 ;; jump unconditional jump | |
| 101 ;; call unconditional call | |
| 102 ;; load load instruction(s) | |
| 103 ;; store store instruction(s) | |
| 104 ;; move data movement within same register set | |
| 105 ;; xfer transfer to/from coprocessor | |
| 106 ;; arith integer arithmetic instruction | |
| 107 ;; darith double precision integer arithmetic instructions | |
| 108 ;; imul integer multiply | |
| 109 ;; idiv integer divide | |
| 110 ;; icmp integer compare | |
| 111 ;; fadd floating point add/subtract | |
| 112 ;; fmul floating point multiply | |
| 113 ;; fmadd floating point multiply-add | |
| 114 ;; fdiv floating point divide | |
| 115 ;; fabs floating point absolute value | |
| 116 ;; fneg floating point negation | |
| 117 ;; fcmp floating point compare | |
| 118 ;; fcvt floating point convert | |
| 119 ;; fsqrt floating point square root | |
| 120 ;; multi multiword sequence (or user asm statements) | |
| 121 ;; nop no operation | |
| 122 | |
| 123 (define_attr "type" | |
| 124 "unknown,branch,jump,call,load,store,move,xfer,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop" | |
| 125 (const_string "unknown")) | |
| 126 | |
| 127 ;; Main data type used by the insn | |
| 128 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown")) | |
| 129 | |
| 130 ;; Length (in # of bytes). A conditional branch is allowed only to a | |
| 131 ;; location within a signed 18-bit offset of the delay slot. If that | |
| 132 ;; provides too small a range, we use the `j' instruction. This | |
| 133 ;; instruction takes a 28-bit value, but that value is not an offset. | |
| 134 ;; Instead, it's bitwise-ored with the high-order four bits of the | |
| 135 ;; instruction in the delay slot, which means it cannot be used to | |
| 136 ;; cross a 256MB boundary. We could fall back back on the jr, | |
| 137 ;; instruction which allows full access to the entire address space, | |
| 138 ;; but we do not do so at present. | |
| 139 | |
| 140 (define_attr "length" "" | |
| 141 (cond [(eq_attr "type" "branch") | |
| 142 (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4)))) | |
| 143 (const_int 131072)) | |
| 144 (const_int 4)] | |
| 145 (const_int 12))] | |
| 146 (const_int 4))) | |
| 147 | |
| 148 (define_attr "cpu" | |
| 149 "default,iq2000" | |
| 150 (const (symbol_ref "iq2000_cpu_attr"))) | |
| 151 | |
| 152 ;; Does the instruction have a mandatory delay slot? has_dslot | |
| 153 ;; Can the instruction be in a delay slot? ok_in_dslot | |
| 154 ;; Can the instruction not be in a delay slot? not_in_dslot | |
| 155 (define_attr "dslot" "has_dslot,ok_in_dslot,not_in_dslot" | |
| 156 (if_then_else (eq_attr "type" "branch,jump,call,xfer,fcmp") | |
| 157 (const_string "has_dslot") | |
| 158 (const_string "ok_in_dslot"))) | |
| 159 | |
| 160 ;; Attribute defining whether or not we can use the branch-likely instructions | |
| 161 | |
| 162 (define_attr "branch_likely" "no,yes" | |
| 163 (const | |
| 164 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0)) | |
| 165 (const_string "yes") | |
| 166 (const_string "no")))) | |
| 167 | |
| 168 | |
| 169 ;; Describe a user's asm statement. | |
| 170 (define_asm_attributes | |
| 171 [(set_attr "type" "multi")]) | |
| 172 | |
| 173 | |
| 174 | |
| 175 ;; ......................... | |
| 176 ;; | |
| 177 ;; Delay slots, can't describe load/fcmp/xfer delay slots here | |
| 178 ;; | |
| 179 ;; ......................... | |
| 180 | |
| 181 (define_delay (eq_attr "type" "jump") | |
| 182 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")) | |
| 183 (nil) | |
| 184 (nil)]) | |
| 185 | |
| 186 (define_delay (eq_attr "type" "branch") | |
| 187 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")) | |
| 188 (nil) | |
| 189 (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")))]) | |
| 190 | |
| 191 (define_delay (eq_attr "type" "call") | |
| 192 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")) | |
| 193 (nil) | |
| 194 (nil)]) | |
| 195 | |
| 196 (include "predicates.md") | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
197 (include "constraints.md") |
| 0 | 198 |
| 199 | |
| 200 ;; ......................... | |
| 201 ;; | |
| 202 ;; Pipeline model | |
| 203 ;; | |
| 204 ;; ......................... | |
| 205 | |
| 206 (define_automaton "iq2000") | |
| 207 (define_cpu_unit "core,memory" "iq2000") | |
| 208 | |
| 209 (define_insn_reservation "nonmemory" 1 | |
| 210 (eq_attr "type" "!load,move,store,xfer") | |
| 211 "core") | |
| 212 | |
| 213 (define_insn_reservation "iq2000_load_move" 3 | |
| 214 (and (eq_attr "type" "load,move") | |
| 215 (eq_attr "cpu" "iq2000")) | |
| 216 "memory") | |
| 217 | |
| 218 (define_insn_reservation "other_load_move" 1 | |
| 219 (and (eq_attr "type" "load,move") | |
| 220 (eq_attr "cpu" "!iq2000")) | |
| 221 "memory") | |
| 222 | |
| 223 (define_insn_reservation "store" 1 | |
| 224 (eq_attr "type" "store") | |
| 225 "memory") | |
| 226 | |
| 227 (define_insn_reservation "xfer" 2 | |
| 228 (eq_attr "type" "xfer") | |
| 229 "memory") | |
| 230 | |
| 231 ;; | |
| 232 ;; .................... | |
| 233 ;; | |
| 234 ;; CONDITIONAL TRAPS | |
| 235 ;; | |
| 236 ;; .................... | |
| 237 ;; | |
| 238 | |
| 239 (define_insn "trap" | |
| 240 [(trap_if (const_int 1) (const_int 0))] | |
| 241 "" | |
| 242 "* | |
| 243 { | |
| 244 return \"break\"; | |
| 245 }") | |
| 246 | |
| 247 ;; | |
| 248 ;; .................... | |
| 249 ;; | |
| 250 ;; ADDITION | |
| 251 ;; | |
| 252 ;; .................... | |
| 253 ;; | |
| 254 | |
| 255 (define_expand "addsi3" | |
| 256 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 257 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") | |
| 258 (match_operand:SI 2 "arith_operand" "dI")))] | |
| 259 "" | |
| 260 "") | |
| 261 | |
| 262 (define_insn "addsi3_internal" | |
| 263 [(set (match_operand:SI 0 "register_operand" "=d,=d") | |
| 264 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ") | |
| 265 (match_operand:SI 2 "arith_operand" "d,I")))] | |
| 266 "" | |
| 267 "@ | |
| 268 addu\\t%0,%z1,%2 | |
| 269 addiu\\t%0,%z1,%2" | |
| 270 [(set_attr "type" "arith") | |
| 271 (set_attr "mode" "SI")]) | |
| 272 | |
| 273 ;; | |
| 274 ;; .................... | |
| 275 ;; | |
| 276 ;; SUBTRACTION | |
| 277 ;; | |
| 278 ;; .................... | |
| 279 ;; | |
| 280 | |
| 281 (define_expand "subsi3" | |
| 282 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 283 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") | |
| 284 (match_operand:SI 2 "arith_operand" "dI")))] | |
| 285 "" | |
| 286 "") | |
| 287 | |
| 288 (define_insn "subsi3_internal" | |
| 289 [(set (match_operand:SI 0 "register_operand" "=d,=d") | |
| 290 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ") | |
| 291 (match_operand:SI 2 "arith_operand" "d,I")))] | |
| 292 "" | |
| 293 "@ | |
| 294 subu\\t%0,%z1,%2 | |
| 295 addiu\\t%0,%z1,%n2" | |
| 296 [(set_attr "type" "arith") | |
| 297 (set_attr "mode" "SI")]) | |
| 298 | |
| 299 ;; | |
| 300 ;; .................... | |
| 301 ;; | |
| 302 ;; NEGATION and ONE'S COMPLEMENT | |
| 303 ;; | |
| 304 ;; .................... | |
| 305 | |
| 306 (define_insn "negsi2" | |
| 307 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 308 (neg:SI (match_operand:SI 1 "register_operand" "d")))] | |
| 309 "" | |
| 310 "* | |
| 311 { | |
| 312 operands[2] = const0_rtx; | |
| 313 return \"subu\\t%0,%z2,%1\"; | |
| 314 }" | |
| 315 [(set_attr "type" "arith") | |
| 316 (set_attr "mode" "SI")]) | |
| 317 | |
| 318 (define_insn "one_cmplsi2" | |
| 319 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 320 (not:SI (match_operand:SI 1 "register_operand" "d")))] | |
| 321 "" | |
| 322 "* | |
| 323 { | |
| 324 operands[2] = const0_rtx; | |
| 325 return \"nor\\t%0,%z2,%1\"; | |
| 326 }" | |
| 327 [(set_attr "type" "arith") | |
| 328 (set_attr "mode" "SI")]) | |
| 329 | |
| 330 ;; | |
| 331 ;; .................... | |
| 332 ;; | |
| 333 ;; LOGICAL | |
| 334 ;; | |
| 335 ;; .................... | |
| 336 ;; | |
| 337 | |
| 338 (define_expand "andsi3" | |
| 339 [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
| 340 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d") | |
| 341 (match_operand:SI 2 "nonmemory_operand" "d,K,N")))] | |
| 342 "" | |
| 343 "") | |
| 344 | |
| 345 (define_insn "" | |
| 346 [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
| 347 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d") | |
| 348 (match_operand:SI 2 "nonmemory_operand" "d,K,N")))] | |
| 349 "" | |
| 350 "* | |
| 351 { | |
| 352 if (which_alternative == 0) | |
| 353 return \"and\\t%0,%1,%2\"; | |
| 354 else if (which_alternative == 1) | |
| 355 return \"andi\\t%0,%1,%x2\"; | |
| 356 else if (which_alternative == 2) | |
| 357 { | |
| 358 if ((INTVAL (operands[2]) & 0xffff) == 0xffff) | |
| 359 { | |
| 360 operands[2] = GEN_INT (INTVAL (operands[2]) >> 16); | |
| 361 return \"andoui\\t%0,%1,%x2\"; | |
| 362 } | |
| 363 else | |
| 364 { | |
| 365 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); | |
| 366 return \"andoi\\t%0,%1,%x2\"; | |
| 367 } | |
| 368 } | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
369 else |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
370 gcc_unreachable (); |
| 0 | 371 }" |
| 372 [(set_attr "type" "arith") | |
| 373 (set_attr "mode" "SI")]) | |
| 374 | |
| 375 (define_expand "iorsi3" | |
| 376 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 377 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") | |
| 378 (match_operand:SI 2 "uns_arith_operand" "d,K")))] | |
| 379 "" | |
| 380 "") | |
| 381 | |
| 382 (define_insn "" | |
| 383 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 384 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") | |
| 385 (match_operand:SI 2 "uns_arith_operand" "d,K")))] | |
| 386 "" | |
| 387 "@ | |
| 388 or\\t%0,%1,%2 | |
| 389 ori\\t%0,%1,%x2" | |
| 390 [(set_attr "type" "arith") | |
| 391 (set_attr "mode" "SI")]) | |
| 392 | |
| 393 (define_expand "xorsi3" | |
| 394 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 395 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") | |
| 396 (match_operand:SI 2 "uns_arith_operand" "d,K")))] | |
| 397 "" | |
| 398 "") | |
| 399 | |
| 400 (define_insn "" | |
| 401 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 402 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") | |
| 403 (match_operand:SI 2 "uns_arith_operand" "d,K")))] | |
| 404 "" | |
| 405 "@ | |
| 406 xor\\t%0,%1,%2 | |
| 407 xori\\t%0,%1,%x2" | |
| 408 [(set_attr "type" "arith") | |
| 409 (set_attr "mode" "SI")]) | |
| 410 | |
| 411 (define_insn "*norsi3" | |
| 412 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 413 (and:SI (not:SI (match_operand:SI 1 "register_operand" "d")) | |
| 414 (not:SI (match_operand:SI 2 "register_operand" "d"))))] | |
| 415 "" | |
| 416 "nor\\t%0,%z1,%z2" | |
| 417 [(set_attr "type" "arith") | |
| 418 (set_attr "mode" "SI")]) | |
| 419 | |
| 420 ;; | |
| 421 ;; .................... | |
| 422 ;; | |
| 423 ;; ZERO EXTENSION | |
| 424 ;; | |
| 425 ;; .................... | |
| 426 | |
| 427 ;; Extension insns. | |
| 428 ;; Those for integer source operand are ordered widest source type first. | |
| 429 | |
| 430 (define_expand "zero_extendhisi2" | |
| 431 [(set (match_operand:SI 0 "register_operand" "") | |
| 432 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] | |
| 433 "" | |
| 434 "") | |
| 435 | |
| 436 (define_insn "" | |
| 437 [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
| 438 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))] | |
| 439 "" | |
| 440 "* | |
| 441 { | |
| 442 if (which_alternative == 0) | |
| 443 return \"andi\\t%0,%1,0xffff\"; | |
| 444 else | |
| 445 return iq2000_move_1word (operands, insn, TRUE); | |
| 446 }" | |
| 447 [(set_attr "type" "arith,load,load") | |
| 448 (set_attr "mode" "SI") | |
| 449 (set_attr "length" "4,4,8")]) | |
| 450 | |
| 451 (define_expand "zero_extendqihi2" | |
| 452 [(set (match_operand:HI 0 "register_operand" "") | |
| 453 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
| 454 "" | |
| 455 "") | |
| 456 | |
| 457 (define_insn "" | |
| 458 [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
| 459 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))] | |
| 460 "" | |
| 461 "* | |
| 462 { | |
| 463 if (which_alternative == 0) | |
| 464 return \"andi\\t%0,%1,0x00ff\"; | |
| 465 else | |
| 466 return iq2000_move_1word (operands, insn, TRUE); | |
| 467 }" | |
| 468 [(set_attr "type" "arith,load,load") | |
| 469 (set_attr "mode" "HI") | |
| 470 (set_attr "length" "4,4,8")]) | |
| 471 | |
| 472 (define_expand "zero_extendqisi2" | |
| 473 [(set (match_operand:SI 0 "register_operand" "") | |
| 474 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
| 475 "" | |
| 476 "") | |
| 477 | |
| 478 (define_insn "" | |
| 479 [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
| 480 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))] | |
| 481 "" | |
| 482 "* | |
| 483 { | |
| 484 if (which_alternative == 0) | |
| 485 return \"andi\\t%0,%1,0x00ff\"; | |
| 486 else | |
| 487 return iq2000_move_1word (operands, insn, TRUE); | |
| 488 }" | |
| 489 [(set_attr "type" "arith,load,load") | |
| 490 (set_attr "mode" "SI") | |
| 491 (set_attr "length" "4,4,8")]) | |
| 492 | |
| 493 ;; | |
| 494 ;; .................... | |
| 495 ;; | |
| 496 ;; SIGN EXTENSION | |
| 497 ;; | |
| 498 ;; .................... | |
| 499 | |
| 500 ;; Extension insns. | |
| 501 ;; Those for integer source operand are ordered widest source type first. | |
| 502 | |
| 503 ;; These patterns originally accepted general_operands, however, slightly | |
| 504 ;; better code is generated by only accepting register_operands, and then | |
| 505 ;; letting combine generate the lh and lb insns. | |
| 506 | |
| 507 (define_expand "extendhisi2" | |
| 508 [(set (match_operand:SI 0 "register_operand" "") | |
| 509 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] | |
| 510 "" | |
| 511 " | |
| 512 { | |
| 513 if (optimize && GET_CODE (operands[1]) == MEM) | |
| 514 operands[1] = force_not_mem (operands[1]); | |
| 515 | |
| 516 if (GET_CODE (operands[1]) != MEM) | |
| 517 { | |
| 518 rtx op1 = gen_lowpart (SImode, operands[1]); | |
| 519 rtx temp = gen_reg_rtx (SImode); | |
| 520 rtx shift = GEN_INT (16); | |
| 521 | |
| 522 emit_insn (gen_ashlsi3 (temp, op1, shift)); | |
| 523 emit_insn (gen_ashrsi3 (operands[0], temp, shift)); | |
| 524 DONE; | |
| 525 } | |
| 526 }") | |
| 527 | |
| 528 (define_insn "extendhisi2_internal" | |
| 529 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 530 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))] | |
| 531 "" | |
| 532 "* return iq2000_move_1word (operands, insn, FALSE);" | |
| 533 [(set_attr "type" "load") | |
| 534 (set_attr "mode" "SI") | |
| 535 (set_attr "length" "4,8")]) | |
| 536 | |
| 537 (define_expand "extendqihi2" | |
| 538 [(set (match_operand:HI 0 "register_operand" "") | |
| 539 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
| 540 "" | |
| 541 " | |
| 542 { | |
| 543 if (optimize && GET_CODE (operands[1]) == MEM) | |
| 544 operands[1] = force_not_mem (operands[1]); | |
| 545 | |
| 546 if (GET_CODE (operands[1]) != MEM) | |
| 547 { | |
| 548 rtx op0 = gen_lowpart (SImode, operands[0]); | |
| 549 rtx op1 = gen_lowpart (SImode, operands[1]); | |
| 550 rtx temp = gen_reg_rtx (SImode); | |
| 551 rtx shift = GEN_INT (24); | |
| 552 | |
| 553 emit_insn (gen_ashlsi3 (temp, op1, shift)); | |
| 554 emit_insn (gen_ashrsi3 (op0, temp, shift)); | |
| 555 DONE; | |
| 556 } | |
| 557 }") | |
| 558 | |
| 559 (define_insn "extendqihi2_internal" | |
| 560 [(set (match_operand:HI 0 "register_operand" "=d,d") | |
| 561 (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))] | |
| 562 "" | |
| 563 "* return iq2000_move_1word (operands, insn, FALSE);" | |
| 564 [(set_attr "type" "load") | |
| 565 (set_attr "mode" "SI") | |
| 566 (set_attr "length" "4,8")]) | |
| 567 | |
| 568 | |
| 569 (define_expand "extendqisi2" | |
| 570 [(set (match_operand:SI 0 "register_operand" "") | |
| 571 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
| 572 "" | |
| 573 " | |
| 574 { | |
| 575 if (optimize && GET_CODE (operands[1]) == MEM) | |
| 576 operands[1] = force_not_mem (operands[1]); | |
| 577 | |
| 578 if (GET_CODE (operands[1]) != MEM) | |
| 579 { | |
| 580 rtx op1 = gen_lowpart (SImode, operands[1]); | |
| 581 rtx temp = gen_reg_rtx (SImode); | |
| 582 rtx shift = GEN_INT (24); | |
| 583 | |
| 584 emit_insn (gen_ashlsi3 (temp, op1, shift)); | |
| 585 emit_insn (gen_ashrsi3 (operands[0], temp, shift)); | |
| 586 DONE; | |
| 587 } | |
| 588 }") | |
| 589 | |
| 590 (define_insn "extendqisi2_insn" | |
| 591 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 592 (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))] | |
| 593 "" | |
| 594 "* return iq2000_move_1word (operands, insn, FALSE);" | |
| 595 [(set_attr "type" "load") | |
| 596 (set_attr "mode" "SI") | |
| 597 (set_attr "length" "4,8")]) | |
| 598 | |
| 599 ;; | |
| 600 ;; ........................ | |
| 601 ;; | |
| 602 ;; BIT FIELD EXTRACTION | |
| 603 ;; | |
| 604 ;; ........................ | |
| 605 | |
| 606 (define_insn "extzv" | |
| 607 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 608 (zero_extract:SI (match_operand:SI 1 "register_operand" "r") | |
| 609 (match_operand:SI 2 "const_int_operand" "O") | |
| 610 (match_operand:SI 3 "const_int_operand" "O")))] | |
| 611 "" | |
| 612 "* | |
| 613 { | |
| 614 int value[4]; | |
| 615 value[2] = INTVAL (operands[2]); | |
| 616 value[3] = INTVAL (operands[3]); | |
| 617 operands[2] = GEN_INT ((value[3])); | |
| 618 operands[3] = GEN_INT ((32 - value[2])); | |
| 619 return \"ram\\t%0,%1,%2,%3,0x0\"; | |
| 620 }" | |
| 621 [(set_attr "type" "arith")]) | |
| 622 | |
| 623 ;; | |
| 624 ;; .................... | |
| 625 ;; | |
| 626 ;; DATA MOVEMENT | |
| 627 ;; | |
| 628 ;; .................... | |
| 629 | |
| 630 /* Take care of constants that don't fit in single instruction */ | |
| 631 (define_split | |
| 632 [(set (match_operand:SI 0 "register_operand" "") | |
| 633 (match_operand:SI 1 "general_operand" ""))] | |
| 634 "(reload_in_progress || reload_completed) | |
| 635 && large_int (operands[1], SImode)" | |
| 636 | |
| 637 [(set (match_dup 0 ) | |
| 638 (high:SI (match_dup 1))) | |
| 639 (set (match_dup 0 ) | |
| 640 (lo_sum:SI (match_dup 0) | |
| 641 (match_dup 1)))] | |
| 642 ) | |
| 643 | |
| 644 ;; ??? iq2000_move_1word has support for HIGH, so this pattern may be | |
| 645 ;; unnecessary. | |
| 646 | |
| 647 (define_insn "high" | |
| 648 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 649 (high:SI (match_operand:SI 1 "immediate_operand" "")))] | |
| 650 "" | |
| 651 "lui\\t%0,%%hi(%1) # high" | |
| 652 [(set_attr "type" "move")]) | |
| 653 | |
| 654 (define_insn "low" | |
| 655 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 656 (lo_sum:SI (match_operand:SI 1 "register_operand" "r") | |
| 657 (match_operand:SI 2 "immediate_operand" "")))] | |
| 658 "" | |
| 659 "addiu\\t%0,%1,%%lo(%2) # low" | |
| 660 [(set_attr "type" "arith") | |
| 661 (set_attr "mode" "SI")]) | |
| 662 | |
| 663 ;; 32-bit Integer moves | |
| 664 | |
| 665 (define_split | |
| 666 [(set (match_operand:SI 0 "register_operand" "") | |
| 667 (match_operand:SI 1 "large_int" ""))] | |
| 668 "reload_in_progress | reload_completed" | |
| 669 [(set (match_dup 0) | |
| 670 (match_dup 2)) | |
| 671 (set (match_dup 0) | |
| 672 (ior:SI (match_dup 0) | |
| 673 (match_dup 3)))] | |
| 674 " | |
| 675 { | |
| 676 operands[2] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]) | |
| 677 & BITMASK_UPPER16, | |
| 678 SImode)); | |
| 679 operands[3] = GEN_INT (INTVAL (operands[1]) & BITMASK_LOWER16); | |
| 680 }") | |
| 681 | |
| 682 ;; Unlike most other insns, the move insns can't be split with | |
| 683 ;; different predicates, because register spilling and other parts of | |
| 684 ;; the compiler, have memoized the insn number already. | |
| 685 | |
| 686 (define_expand "movsi" | |
| 687 [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
| 688 (match_operand:SI 1 "general_operand" ""))] | |
| 689 "" | |
| 690 " | |
| 691 { | |
| 692 if (iq2000_check_split (operands[1], SImode)) | |
| 693 { | |
| 694 enum machine_mode mode = GET_MODE (operands[0]); | |
| 695 rtx tem = ((reload_in_progress | reload_completed) | |
| 696 ? operands[0] : gen_reg_rtx (mode)); | |
| 697 | |
| 698 emit_insn (gen_rtx_SET (VOIDmode, tem, | |
| 699 gen_rtx_HIGH (mode, operands[1]))); | |
| 700 | |
| 701 operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]); | |
| 702 } | |
| 703 | |
| 704 if ((reload_in_progress | reload_completed) == 0 | |
| 705 && !register_operand (operands[0], SImode) | |
| 706 && !register_operand (operands[1], SImode) | |
| 707 && (GET_CODE (operands[1]) != CONST_INT | |
| 708 || INTVAL (operands[1]) != 0)) | |
| 709 { | |
| 710 rtx temp = force_reg (SImode, operands[1]); | |
| 711 emit_move_insn (operands[0], temp); | |
| 712 DONE; | |
| 713 } | |
| 714 | |
| 715 /* Take care of constants that don't fit in single instruction */ | |
| 716 if ((reload_in_progress || reload_completed) | |
| 717 && CONSTANT_P (operands[1]) | |
| 718 && GET_CODE (operands[1]) != HIGH | |
| 719 && GET_CODE (operands[1]) != LO_SUM | |
| 720 && ! SMALL_INT_UNSIGNED (operands[1])) | |
| 721 { | |
| 722 rtx tem = ((reload_in_progress | reload_completed) | |
| 723 ? operands[0] : gen_reg_rtx (SImode)); | |
| 724 | |
| 725 emit_insn (gen_rtx_SET (VOIDmode, tem, | |
| 726 gen_rtx_HIGH (SImode, operands[1]))); | |
| 727 operands[1] = gen_rtx_LO_SUM (SImode, tem, operands[1]); | |
| 728 } | |
| 729 }") | |
| 730 | |
| 731 ;; The difference between these two is whether or not ints are allowed | |
| 732 ;; in FP registers (off by default, use -mdebugh to enable). | |
| 733 | |
| 734 (define_insn "movsi_internal2" | |
|
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735 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,R,m") |
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736 (match_operand:SI 1 "move_operand" "d,IKL,Mnis,R,m,dJ,dJ"))] |
| 0 | 737 "(register_operand (operands[0], SImode) |
| 738 || register_operand (operands[1], SImode) | |
| 739 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" | |
| 740 "* return iq2000_move_1word (operands, insn, FALSE);" | |
|
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741 [(set_attr "type" "move,arith,arith,load,load,store,store") |
| 0 | 742 (set_attr "mode" "SI") |
|
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743 (set_attr "length" "4,4,8,8,8,4,8")]) |
| 0 | 744 |
| 745 ;; 16-bit Integer moves | |
| 746 | |
| 747 ;; Unlike most other insns, the move insns can't be split with | |
| 748 ;; different predicates, because register spilling and other parts of | |
| 749 ;; the compiler, have memoized the insn number already. | |
| 750 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined | |
| 751 | |
| 752 (define_expand "movhi" | |
| 753 [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
| 754 (match_operand:HI 1 "general_operand" ""))] | |
| 755 "" | |
| 756 " | |
| 757 { | |
| 758 if ((reload_in_progress | reload_completed) == 0 | |
| 759 && !register_operand (operands[0], HImode) | |
| 760 && !register_operand (operands[1], HImode) | |
| 761 && ((GET_CODE (operands[1]) != CONST_INT | |
| 762 || INTVAL (operands[1]) != 0))) | |
| 763 { | |
| 764 rtx temp = force_reg (HImode, operands[1]); | |
| 765 emit_move_insn (operands[0], temp); | |
| 766 DONE; | |
| 767 } | |
| 768 }") | |
| 769 | |
| 770 ;; The difference between these two is whether or not ints are allowed | |
| 771 ;; in FP registers (off by default, use -mdebugh to enable). | |
| 772 | |
| 773 (define_insn "movhi_internal2" | |
|
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774 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m") |
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775 (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ"))] |
| 0 | 776 "(register_operand (operands[0], HImode) |
| 777 || register_operand (operands[1], HImode) | |
| 778 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" | |
| 779 "* return iq2000_move_1word (operands, insn, TRUE);" | |
|
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780 [(set_attr "type" "move,arith,load,load,store,store") |
| 0 | 781 (set_attr "mode" "HI") |
|
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782 (set_attr "length" "4,4,4,8,4,8")]) |
| 0 | 783 |
| 784 ;; 8-bit Integer moves | |
| 785 | |
| 786 ;; Unlike most other insns, the move insns can't be split with | |
| 787 ;; different predicates, because register spilling and other parts of | |
| 788 ;; the compiler, have memoized the insn number already. | |
| 789 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined | |
| 790 | |
| 791 (define_expand "movqi" | |
| 792 [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
| 793 (match_operand:QI 1 "general_operand" ""))] | |
| 794 "" | |
| 795 " | |
| 796 { | |
| 797 if ((reload_in_progress | reload_completed) == 0 | |
| 798 && !register_operand (operands[0], QImode) | |
| 799 && !register_operand (operands[1], QImode) | |
| 800 && (GET_CODE (operands[1]) != CONST_INT | |
| 801 || INTVAL (operands[1]) != 0)) | |
| 802 { | |
| 803 rtx temp = force_reg (QImode, operands[1]); | |
| 804 emit_move_insn (operands[0], temp); | |
| 805 DONE; | |
| 806 } | |
| 807 }") | |
| 808 | |
| 809 ;; The difference between these two is whether or not ints are allowed | |
| 810 ;; in FP registers (off by default, use -mdebugh to enable). | |
| 811 | |
| 812 (define_insn "movqi_internal2" | |
|
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813 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m") |
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814 (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ"))] |
| 0 | 815 "(register_operand (operands[0], QImode) |
| 816 || register_operand (operands[1], QImode) | |
| 817 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" | |
| 818 "* return iq2000_move_1word (operands, insn, TRUE);" | |
|
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819 [(set_attr "type" "move,arith,load,load,store,store") |
| 0 | 820 (set_attr "mode" "QI") |
|
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821 (set_attr "length" "4,4,4,8,4,8")]) |
| 0 | 822 |
| 823 ;; 32-bit floating point moves | |
| 824 | |
| 825 (define_expand "movsf" | |
| 826 [(set (match_operand:SF 0 "general_operand" "") | |
| 827 (match_operand:SF 1 "general_operand" ""))] | |
| 828 "" | |
| 829 " | |
| 830 { | |
| 831 if (!reload_in_progress | |
| 832 && !reload_completed | |
| 833 && GET_CODE (operands[0]) == MEM | |
| 834 && (GET_CODE (operands[1]) == MEM | |
| 835 || GET_CODE (operands[1]) == CONST_DOUBLE)) | |
| 836 operands[1] = copy_to_mode_reg (SFmode, operands[1]); | |
| 837 | |
| 838 /* Take care of reg <- SF constant */ | |
| 839 if ( const_double_operand (operands[1], GET_MODE (operands[1]) ) ) | |
| 840 { | |
| 841 emit_insn (gen_movsf_high (operands[0], operands[1])); | |
| 842 emit_insn (gen_movsf_lo_sum (operands[0], operands[0], operands[1])); | |
| 843 DONE; | |
| 844 } | |
| 845 }") | |
| 846 | |
| 847 (define_insn "movsf_lo_sum" | |
| 848 [(set (match_operand:SF 0 "register_operand" "=r") | |
| 849 (lo_sum:SF (match_operand:SF 1 "register_operand" "r") | |
| 850 (match_operand:SF 2 "const_double_operand" "")))] | |
| 851 "" | |
| 852 "* | |
| 853 { | |
| 854 REAL_VALUE_TYPE r; | |
| 855 long i; | |
| 856 | |
| 857 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]); | |
| 858 REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
| 859 operands[2] = GEN_INT (i); | |
| 860 return \"addiu\\t%0,%1,%%lo(%2) # low\"; | |
| 861 }" | |
| 862 [(set_attr "length" "4") | |
| 863 (set_attr "type" "arith")]) | |
| 864 | |
| 865 (define_insn "movsf_high" | |
| 866 [(set (match_operand:SF 0 "register_operand" "=r") | |
| 867 (high:SF (match_operand:SF 1 "const_double_operand" "")))] | |
| 868 "" | |
| 869 "* | |
| 870 { | |
| 871 REAL_VALUE_TYPE r; | |
| 872 long i; | |
| 873 | |
| 874 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); | |
| 875 REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
| 876 operands[1] = GEN_INT (i); | |
| 877 return \"lui\\t%0,%%hi(%1) # high\"; | |
| 878 }" | |
| 879 [(set_attr "length" "4") | |
| 880 (set_attr "type" "arith")]) | |
| 881 | |
| 882 (define_insn "*movsf_internal" | |
| 883 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m") | |
| 884 (match_operand:SF 1 "nonimmediate_operand" "r,m,r"))] | |
| 885 "!memory_operand (operands[0], SFmode) || !memory_operand (operands[1], SFmode)" | |
| 886 "* | |
| 887 { | |
| 888 iq2000_fill_delay_slot (\"\", DELAY_LOAD, operands, insn); | |
| 889 if (which_alternative == 0) | |
| 890 return \"or\\t%0,%1,%1\"; | |
| 891 else if (which_alternative == 1) | |
| 892 return \"lw\\t%0,%1\"; | |
| 893 else if (which_alternative == 2) | |
| 894 return \"sw\\t%1,%0\"; | |
|
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895 else |
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896 gcc_unreachable (); |
| 0 | 897 }" |
| 898 [(set_attr "length" "4,4,4") | |
| 899 (set_attr "type" "arith,load,store")] | |
| 900 ) | |
| 901 | |
| 902 ;; | |
| 903 ;; .................... | |
| 904 ;; | |
| 905 ;; SHIFTS | |
| 906 ;; | |
| 907 ;; .................... | |
| 908 | |
| 909 (define_expand "ashlsi3" | |
| 910 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 911 (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
| 912 (match_operand:SI 2 "arith_operand" "dI")))] | |
| 913 "" | |
| 914 "") | |
| 915 | |
| 916 (define_insn "ashlsi3_internal1" | |
| 917 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 918 (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
| 919 (match_operand:SI 2 "arith_operand" "dI")))] | |
| 920 "" | |
| 921 "* | |
| 922 { | |
| 923 if (GET_CODE (operands[2]) == CONST_INT) | |
| 924 { | |
| 925 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); | |
| 926 return \"sll\\t%0,%1,%2\"; | |
| 927 } | |
| 928 else | |
| 929 return \"sllv\\t%0,%1,%2\"; | |
| 930 }" | |
| 931 [(set_attr "type" "arith") | |
| 932 (set_attr "mode" "SI")]) | |
| 933 | |
| 934 (define_expand "ashrsi3" | |
| 935 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 936 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") | |
| 937 (match_operand:SI 2 "arith_operand" "dI")))] | |
| 938 "" | |
| 939 "") | |
| 940 | |
| 941 (define_insn "ashrsi3_internal1" | |
| 942 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 943 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") | |
| 944 (match_operand:SI 2 "arith_operand" "dI")))] | |
| 945 "" | |
| 946 "* | |
| 947 { | |
| 948 if (GET_CODE (operands[2]) == CONST_INT) | |
| 949 { | |
| 950 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); | |
| 951 return \"sra\\t%0,%1,%2\"; | |
| 952 } | |
| 953 else | |
| 954 return \"srav\\t%0,%1,%2\"; | |
| 955 }" | |
| 956 [(set_attr "type" "arith") | |
| 957 (set_attr "mode" "SI")]) | |
| 958 | |
| 959 (define_expand "lshrsi3" | |
| 960 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 961 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") | |
| 962 (match_operand:SI 2 "arith_operand" "dI")))] | |
| 963 "" | |
| 964 "") | |
| 965 | |
| 966 (define_insn "lshrsi3_internal1" | |
| 967 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 968 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") | |
| 969 (match_operand:SI 2 "arith_operand" "dI")))] | |
| 970 "" | |
| 971 "* | |
| 972 { | |
| 973 if (GET_CODE (operands[2]) == CONST_INT) | |
| 974 { | |
| 975 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); | |
| 976 return \"srl\\t%0,%1,%2\"; | |
| 977 } | |
| 978 else | |
| 979 return \"srlv\\t%0,%1,%2\"; | |
| 980 }" | |
| 981 [(set_attr "type" "arith") | |
| 982 (set_attr "mode" "SI")]) | |
| 983 | |
| 984 ;; Rotate Right | |
| 985 (define_insn "rotrsi3" | |
| 986 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 987 (rotatert:SI (match_operand:SI 1 "register_operand" "r") | |
| 988 (match_operand:SI 2 "uns_arith_operand" "O")))] | |
| 989 "" | |
| 990 "ram %0,%1,%2,0x0,0x0" | |
| 991 [(set_attr "type" "arith")]) | |
| 992 | |
| 993 | |
| 994 ;; | |
| 995 ;; .................... | |
| 996 ;; | |
|
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997 ;; CONDITIONAL BRANCHES |
| 0 | 998 ;; |
| 999 ;; .................... | |
| 1000 | |
|
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1001 (define_expand "cbranchsi4" |
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1002 [(set (pc) |
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1003 (if_then_else |
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1004 (match_operator:SI 0 "ordered_comparison_operator" |
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1005 [(match_operand:SI 1 "register_operand") |
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1006 (match_operand:SI 2 "reg_or_const_operand")]) |
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1007 (label_ref (match_operand:SI 3 "")) |
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1008 (pc)))] |
| 0 | 1009 "" |
| 1010 " | |
| 1011 { | |
|
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1012 gen_conditional_branch (operands, SImode); |
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1013 DONE; |
| 0 | 1014 }") |
| 1015 | |
| 1016 | |
| 1017 ;; Conditional branches on comparisons with zero. | |
| 1018 | |
| 1019 (define_insn "branch_zero" | |
| 1020 [(set (pc) | |
| 1021 (if_then_else | |
| 1022 (match_operator:SI 0 "cmp_op" | |
| 1023 [(match_operand:SI 2 "register_operand" "d") | |
| 1024 (const_int 0)]) | |
| 1025 (label_ref (match_operand 1 "" "")) | |
| 1026 (pc)))] | |
| 1027 "" | |
| 1028 "* | |
| 1029 { | |
| 1030 return iq2000_output_conditional_branch (insn, | |
| 1031 operands, | |
| 1032 /*two_operands_p=*/0, | |
| 1033 /*float_p=*/0, | |
| 1034 /*inverted_p=*/0, | |
| 1035 get_attr_length (insn)); | |
| 1036 }" | |
| 1037 [(set_attr "type" "branch") | |
| 1038 (set_attr "mode" "none")]) | |
| 1039 | |
| 1040 (define_insn "branch_zero_inverted" | |
| 1041 [(set (pc) | |
| 1042 (if_then_else | |
| 1043 (match_operator:SI 0 "cmp_op" | |
| 1044 [(match_operand:SI 2 "register_operand" "d") | |
| 1045 (const_int 0)]) | |
| 1046 (pc) | |
| 1047 (label_ref (match_operand 1 "" ""))))] | |
| 1048 "" | |
| 1049 "* | |
| 1050 { | |
| 1051 return iq2000_output_conditional_branch (insn, | |
| 1052 operands, | |
| 1053 /*two_operands_p=*/0, | |
| 1054 /*float_p=*/0, | |
| 1055 /*inverted_p=*/1, | |
| 1056 get_attr_length (insn)); | |
| 1057 }" | |
| 1058 [(set_attr "type" "branch") | |
| 1059 (set_attr "mode" "none")]) | |
| 1060 | |
| 1061 ;; Conditional branch on equality comparison. | |
| 1062 | |
| 1063 (define_insn "branch_equality" | |
| 1064 [(set (pc) | |
| 1065 (if_then_else | |
| 1066 (match_operator:SI 0 "equality_op" | |
| 1067 [(match_operand:SI 2 "register_operand" "d") | |
| 1068 (match_operand:SI 3 "register_operand" "d")]) | |
| 1069 (label_ref (match_operand 1 "" "")) | |
| 1070 (pc)))] | |
| 1071 "" | |
| 1072 "* | |
| 1073 { | |
| 1074 return iq2000_output_conditional_branch (insn, | |
| 1075 operands, | |
| 1076 /*two_operands_p=*/1, | |
| 1077 /*float_p=*/0, | |
| 1078 /*inverted_p=*/0, | |
| 1079 get_attr_length (insn)); | |
| 1080 }" | |
| 1081 [(set_attr "type" "branch") | |
| 1082 (set_attr "mode" "none")]) | |
| 1083 | |
| 1084 (define_insn "branch_equality_inverted" | |
| 1085 [(set (pc) | |
| 1086 (if_then_else | |
| 1087 (match_operator:SI 0 "equality_op" | |
| 1088 [(match_operand:SI 2 "register_operand" "d") | |
| 1089 (match_operand:SI 3 "register_operand" "d")]) | |
| 1090 (pc) | |
| 1091 (label_ref (match_operand 1 "" ""))))] | |
| 1092 "" | |
| 1093 "* | |
| 1094 { | |
| 1095 return iq2000_output_conditional_branch (insn, | |
| 1096 operands, | |
| 1097 /*two_operands_p=*/1, | |
| 1098 /*float_p=*/0, | |
| 1099 /*inverted_p=*/1, | |
| 1100 get_attr_length (insn)); | |
| 1101 }" | |
| 1102 [(set_attr "type" "branch") | |
| 1103 (set_attr "mode" "none")]) | |
| 1104 | |
| 1105 | |
| 1106 ;; Recognize bbi and bbin instructions. These use two unusual template | |
| 1107 ;; patterns, %Ax and %Px. %Ax outputs an 'i' if operand `x' is a LABEL_REF | |
| 1108 ;; otherwise it outputs an 'in'. %Px does nothing if `x' is PC | |
| 1109 ;; and outputs the operand if `x' is a LABEL_REF. | |
| 1110 | |
| 1111 (define_insn "" | |
| 1112 [(set (pc) | |
| 1113 (if_then_else | |
| 1114 (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "r") | |
| 1115 (const_int 1) | |
| 1116 (match_operand:SI 1 "arith_operand" "I")) | |
| 1117 (const_int 0)) | |
| 1118 (match_operand 2 "pc_or_label_operand" "") | |
| 1119 (match_operand 3 "pc_or_label_operand" "")))] | |
| 1120 "" | |
| 1121 "bb%A2\\t%0(31-%1),%P2%P3" | |
| 1122 [(set_attr "length" "4") | |
| 1123 (set_attr "type" "branch")]) | |
| 1124 | |
| 1125 (define_insn "" | |
| 1126 [(set (pc) | |
| 1127 (if_then_else | |
| 1128 (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "r") | |
| 1129 (const_int 1) | |
| 1130 (match_operand:SI 1 "arith_operand" "I")) | |
| 1131 (const_int 0)) | |
| 1132 (match_operand 2 "pc_or_label_operand" "") | |
| 1133 (match_operand 3 "pc_or_label_operand" "")))] | |
| 1134 "" | |
| 1135 "bb%A3\\t%0(31-%1),%P2%P3" | |
| 1136 [(set_attr "length" "4") | |
| 1137 (set_attr "type" "branch")]) | |
| 1138 | |
| 1139 (define_insn "" | |
| 1140 [(set (pc) | |
| 1141 (if_then_else | |
| 1142 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r") | |
| 1143 (const_int 1) | |
| 1144 (match_operand:SI 1 "arith_operand" "I")) | |
| 1145 (const_int 0)) | |
| 1146 (match_operand 2 "pc_or_label_operand" "") | |
| 1147 (match_operand 3 "pc_or_label_operand" "")))] | |
| 1148 "" | |
| 1149 "bb%A2\\t%0(31-%1),%P2%P3" | |
| 1150 [(set_attr "length" "4") | |
| 1151 (set_attr "type" "branch")]) | |
| 1152 | |
| 1153 (define_insn "" | |
| 1154 [(set (pc) | |
| 1155 (if_then_else | |
| 1156 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r") | |
| 1157 (const_int 1) | |
| 1158 (match_operand:SI 1 "arith_operand" "I")) | |
| 1159 (const_int 0)) | |
| 1160 (match_operand 2 "pc_or_label_operand" "") | |
| 1161 (match_operand 3 "pc_or_label_operand" "")))] | |
| 1162 "" | |
| 1163 "bb%A3\\t%0(31-%1),%P2%P3" | |
| 1164 [(set_attr "length" "4") | |
| 1165 (set_attr "type" "branch")]) | |
| 1166 | |
| 1167 (define_insn "" | |
| 1168 [(set (pc) | |
| 1169 (if_then_else | |
| 1170 (eq (and:SI (match_operand:SI 0 "register_operand" "r") | |
| 1171 (match_operand:SI 1 "power_of_2_operand" "I")) | |
| 1172 (const_int 0)) | |
| 1173 (match_operand 2 "pc_or_label_operand" "") | |
| 1174 (match_operand 3 "pc_or_label_operand" "")))] | |
| 1175 "" | |
| 1176 "bb%A3\\t%0(%p1),%P2%P3" | |
| 1177 [(set_attr "length" "4") | |
| 1178 (set_attr "type" "branch")]) | |
| 1179 | |
| 1180 (define_insn "" | |
| 1181 [(set (pc) | |
| 1182 (if_then_else | |
| 1183 (ne (and:SI (match_operand:SI 0 "register_operand" "r") | |
| 1184 (match_operand:SI 1 "power_of_2_operand" "I")) | |
| 1185 (const_int 0)) | |
| 1186 (match_operand 2 "pc_or_label_operand" "") | |
| 1187 (match_operand 3 "pc_or_label_operand" "")))] | |
| 1188 "" | |
| 1189 "bb%A2\\t%0(%p1),%P2%P3" | |
| 1190 [(set_attr "length" "4") | |
| 1191 (set_attr "type" "branch")]) | |
| 1192 | |
| 1193 ;; | |
| 1194 ;; .................... | |
| 1195 ;; | |
| 1196 ;; SETTING A REGISTER FROM A COMPARISON | |
| 1197 ;; | |
| 1198 ;; .................... | |
| 1199 | |
|
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1200 (define_expand "cstoresi4" |
| 0 | 1201 [(set (match_operand:SI 0 "register_operand" "=d") |
|
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1202 (match_operator:SI 1 "ordered_comparison_operator" |
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1203 [(match_operand:SI 2 "register_operand") |
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1204 (match_operand:SI 3 "reg_or_const_operand")]))] |
| 0 | 1205 "" |
| 1206 " | |
| 1207 { | |
|
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1208 gen_int_relational (GET_CODE (operands[1]), operands[0], |
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1209 operands[2], operands[3], (int *)0); |
| 0 | 1210 DONE; |
| 1211 }") | |
| 1212 | |
| 1213 (define_insn "seq_si_zero" | |
| 1214 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1215 (eq:SI (match_operand:SI 1 "register_operand" "d") | |
| 1216 (const_int 0)))] | |
| 1217 "" | |
| 1218 "sltiu\\t%0,%1,1" | |
| 1219 [(set_attr "type" "arith") | |
| 1220 (set_attr "mode" "SI")]) | |
| 1221 | |
| 1222 (define_insn "sne_si_zero" | |
| 1223 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1224 (ne:SI (match_operand:SI 1 "register_operand" "d") | |
| 1225 (const_int 0)))] | |
| 1226 "" | |
| 1227 "sltu\\t%0,%.,%1" | |
| 1228 [(set_attr "type" "arith") | |
| 1229 (set_attr "mode" "SI")]) | |
| 1230 | |
| 1231 (define_insn "sgt_si" | |
| 1232 [(set (match_operand:SI 0 "register_operand" "=d,=d") | |
| 1233 (gt:SI (match_operand:SI 1 "register_operand" "d,d") | |
| 1234 (match_operand:SI 2 "reg_or_0_operand" "d,J")))] | |
| 1235 "" | |
| 1236 "@ | |
| 1237 slt\\t%0,%z2,%1 | |
| 1238 slt\\t%0,%z2,%1" | |
| 1239 [(set_attr "type" "arith,arith") | |
| 1240 (set_attr "mode" "SI,SI")]) | |
| 1241 | |
| 1242 (define_insn "slt_si" | |
| 1243 [(set (match_operand:SI 0 "register_operand" "=d,=d") | |
| 1244 (lt:SI (match_operand:SI 1 "register_operand" "d,d") | |
| 1245 (match_operand:SI 2 "arith_operand" "d,I")))] | |
| 1246 "" | |
| 1247 "@ | |
| 1248 slt\\t%0,%1,%2 | |
| 1249 slti\\t%0,%1,%2" | |
| 1250 [(set_attr "type" "arith,arith") | |
| 1251 (set_attr "mode" "SI,SI")]) | |
| 1252 | |
| 1253 (define_insn "sle_si_const" | |
| 1254 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1255 (le:SI (match_operand:SI 1 "register_operand" "d") | |
| 1256 (match_operand:SI 2 "small_int" "I")))] | |
| 1257 "INTVAL (operands[2]) < 32767" | |
| 1258 "* | |
| 1259 { | |
| 1260 operands[2] = GEN_INT (INTVAL (operands[2])+1); | |
| 1261 return \"slti\\t%0,%1,%2\"; | |
| 1262 }" | |
| 1263 [(set_attr "type" "arith") | |
| 1264 (set_attr "mode" "SI")]) | |
| 1265 | |
| 1266 (define_insn "sgtu_si" | |
| 1267 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1268 (gtu:SI (match_operand:SI 1 "register_operand" "d") | |
| 1269 (match_operand:SI 2 "reg_or_0_operand" "dJ")))] | |
| 1270 "" | |
| 1271 "sltu\\t%0,%z2,%1" | |
| 1272 [(set_attr "type" "arith") | |
| 1273 (set_attr "mode" "SI")]) | |
| 1274 | |
| 1275 (define_insn "sltu_si" | |
| 1276 [(set (match_operand:SI 0 "register_operand" "=d,=d") | |
| 1277 (ltu:SI (match_operand:SI 1 "register_operand" "d,d") | |
| 1278 (match_operand:SI 2 "arith_operand" "d,I")))] | |
| 1279 "" | |
| 1280 "@ | |
| 1281 sltu\\t%0,%1,%2 | |
| 1282 sltiu\\t%0,%1,%2" | |
| 1283 [(set_attr "type" "arith,arith") | |
| 1284 (set_attr "mode" "SI,SI")]) | |
| 1285 | |
| 1286 (define_insn "sleu_si_const" | |
| 1287 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1288 (leu:SI (match_operand:SI 1 "register_operand" "d") | |
| 1289 (match_operand:SI 2 "small_int" "I")))] | |
| 1290 "INTVAL (operands[2]) < 32767" | |
| 1291 "* | |
| 1292 { | |
| 1293 operands[2] = GEN_INT (INTVAL (operands[2]) + 1); | |
| 1294 return \"sltiu\\t%0,%1,%2\"; | |
| 1295 }" | |
| 1296 [(set_attr "type" "arith") | |
| 1297 (set_attr "mode" "SI")]) | |
| 1298 | |
| 1299 | |
| 1300 ;; | |
| 1301 ;; .................... | |
| 1302 ;; | |
| 1303 ;; UNCONDITIONAL BRANCHES | |
| 1304 ;; | |
| 1305 ;; .................... | |
| 1306 | |
| 1307 ;; Unconditional branches. | |
| 1308 | |
| 1309 (define_insn "jump" | |
| 1310 [(set (pc) | |
| 1311 (label_ref (match_operand 0 "" "")))] | |
| 1312 "" | |
| 1313 "* | |
| 1314 { | |
| 1315 if (GET_CODE (operands[0]) == REG) | |
| 1316 return \"j\\t%0\"; | |
| 1317 return \"j\\t%l0\"; | |
| 1318 /* return \"b\\t%l0\";*/ | |
| 1319 }" | |
| 1320 [(set_attr "type" "jump") | |
| 1321 (set_attr "mode" "none")]) | |
| 1322 | |
| 1323 (define_expand "indirect_jump" | |
| 1324 [(set (pc) (match_operand 0 "register_operand" "d"))] | |
| 1325 "" | |
| 1326 " | |
| 1327 { | |
| 1328 rtx dest; | |
| 1329 | |
| 1330 if (operands[0]) /* eliminate unused code warnings */ | |
| 1331 { | |
| 1332 dest = operands[0]; | |
| 1333 if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode) | |
| 1334 operands[0] = copy_to_mode_reg (Pmode, dest); | |
| 1335 | |
| 1336 if (!(Pmode == DImode)) | |
| 1337 emit_jump_insn (gen_indirect_jump_internal1 (operands[0])); | |
| 1338 else | |
|
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1339 internal_error (\"unimplemented functionality\"); |
| 0 | 1340 |
| 1341 DONE; | |
| 1342 } | |
| 1343 }") | |
| 1344 | |
| 1345 (define_insn "indirect_jump_internal1" | |
| 1346 [(set (pc) (match_operand:SI 0 "register_operand" "d"))] | |
| 1347 "!(Pmode == DImode)" | |
| 1348 "j\\t%0" | |
| 1349 [(set_attr "type" "jump") | |
| 1350 (set_attr "mode" "none")]) | |
| 1351 | |
| 1352 (define_expand "tablejump" | |
| 1353 [(set (pc) | |
| 1354 (match_operand 0 "register_operand" "d")) | |
| 1355 (use (label_ref (match_operand 1 "" "")))] | |
| 1356 "" | |
| 1357 " | |
| 1358 { | |
| 1359 if (operands[0]) /* eliminate unused code warnings */ | |
| 1360 { | |
| 1361 gcc_assert (GET_MODE (operands[0]) == Pmode); | |
| 1362 | |
| 1363 if (!(Pmode == DImode)) | |
| 1364 emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); | |
| 1365 else | |
|
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1366 internal_error (\"unimplemented functionality\"); |
| 0 | 1367 |
| 1368 DONE; | |
| 1369 } | |
| 1370 }") | |
| 1371 | |
| 1372 (define_insn "tablejump_internal1" | |
| 1373 [(set (pc) | |
| 1374 (match_operand:SI 0 "register_operand" "d")) | |
| 1375 (use (label_ref (match_operand 1 "" "")))] | |
| 1376 "!(Pmode == DImode)" | |
| 1377 "j\\t%0" | |
| 1378 [(set_attr "type" "jump") | |
| 1379 (set_attr "mode" "none")]) | |
| 1380 | |
| 1381 (define_expand "tablejump_internal3" | |
| 1382 [(parallel [(set (pc) | |
| 1383 (plus:SI (match_operand:SI 0 "register_operand" "d") | |
| 1384 (label_ref:SI (match_operand 1 "" "")))) | |
| 1385 (use (label_ref:SI (match_dup 1)))])] | |
| 1386 "" | |
| 1387 "") | |
| 1388 | |
| 1389 ;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise | |
| 1390 ;;; it is not valid. ??? With the USE, the condition tests may not be required | |
| 1391 ;;; any longer. | |
| 1392 | |
| 1393 ;;; ??? The length depends on the ABI. It is two for o32, and one for n32. | |
| 1394 ;;; We just use the conservative number here. | |
| 1395 | |
| 1396 (define_insn "" | |
| 1397 [(set (pc) | |
| 1398 (plus:SI (match_operand:SI 0 "register_operand" "d") | |
| 1399 (label_ref:SI (match_operand 1 "" "")))) | |
| 1400 (use (label_ref:SI (match_dup 1)))] | |
| 1401 "!(Pmode == DImode) && next_active_insn (insn) != 0 | |
| 1402 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC | |
| 1403 && PREV_INSN (next_active_insn (insn)) == operands[1]" | |
| 1404 "* | |
| 1405 { | |
| 1406 return \"j\\t%0\"; | |
| 1407 }" | |
| 1408 [(set_attr "type" "jump") | |
| 1409 (set_attr "mode" "none") | |
| 1410 (set_attr "length" "8")]) | |
| 1411 | |
| 1412 ;; | |
| 1413 ;; .................... | |
| 1414 ;; | |
| 1415 ;; Function prologue/epilogue | |
| 1416 ;; | |
| 1417 ;; .................... | |
| 1418 ;; | |
| 1419 | |
| 1420 (define_expand "prologue" | |
| 1421 [(const_int 1)] | |
| 1422 "" | |
| 1423 " | |
| 1424 { | |
| 1425 if (iq2000_isa >= 0) /* avoid unused code warnings */ | |
| 1426 { | |
| 1427 iq2000_expand_prologue (); | |
| 1428 DONE; | |
| 1429 } | |
| 1430 }") | |
| 1431 | |
| 1432 ;; Block any insns from being moved before this point, since the | |
| 1433 ;; profiling call to mcount can use various registers that aren't | |
| 1434 ;; saved or used to pass arguments. | |
| 1435 | |
| 1436 (define_insn "blockage" | |
| 1437 [(unspec_volatile [(const_int 0)] 0)] | |
| 1438 "" | |
| 1439 "" | |
| 1440 [(set_attr "type" "unknown") | |
| 1441 (set_attr "mode" "none") | |
| 1442 (set_attr "length" "0")]) | |
| 1443 | |
| 1444 (define_expand "epilogue" | |
| 1445 [(const_int 2)] | |
| 1446 "" | |
| 1447 " | |
| 1448 { | |
| 1449 if (iq2000_isa >= 0) /* avoid unused code warnings */ | |
| 1450 { | |
| 1451 iq2000_expand_epilogue (); | |
| 1452 DONE; | |
| 1453 } | |
| 1454 }") | |
| 1455 | |
| 1456 ;; Trivial return. Make it look like a normal return insn as that | |
| 1457 ;; allows jump optimizations to work better . | |
| 1458 (define_insn "return" | |
| 1459 [(return)] | |
| 1460 "iq2000_can_use_return_insn ()" | |
| 1461 "j\\t%%31" | |
| 1462 [(set_attr "type" "jump") | |
| 1463 (set_attr "mode" "none")]) | |
| 1464 | |
| 1465 ;; Normal return. | |
| 1466 | |
| 1467 (define_insn "return_internal" | |
| 1468 [(use (match_operand 0 "pmode_register_operand" "")) | |
| 1469 (return)] | |
| 1470 "" | |
| 1471 "* | |
| 1472 { | |
| 1473 return \"j\\t%0\"; | |
| 1474 }" | |
| 1475 [(set_attr "type" "jump") | |
| 1476 (set_attr "mode" "none")]) | |
| 1477 | |
| 1478 (define_insn "eh_return_internal" | |
| 1479 [(const_int 4) | |
| 1480 (return) | |
| 1481 (use (reg:SI 26)) | |
| 1482 (use (reg:SI 31))] | |
| 1483 "" | |
| 1484 "j\\t%%26" | |
| 1485 [(set_attr "type" "jump") | |
| 1486 (set_attr "mode" "none")]) | |
| 1487 | |
| 1488 (define_expand "eh_return" | |
| 1489 [(use (match_operand:SI 0 "register_operand" "r"))] | |
| 1490 "" | |
| 1491 " | |
| 1492 { | |
| 1493 iq2000_expand_eh_return (operands[0]); | |
| 1494 DONE; | |
| 1495 }") | |
| 1496 | |
| 1497 | |
| 1498 ;; | |
| 1499 ;; .................... | |
| 1500 ;; | |
| 1501 ;; FUNCTION CALLS | |
| 1502 ;; | |
| 1503 ;; .................... | |
| 1504 | |
| 1505 ;; calls.c now passes a third argument, make saber happy | |
| 1506 | |
| 1507 (define_expand "call" | |
| 1508 [(parallel [(call (match_operand 0 "memory_operand" "m") | |
| 1509 (match_operand 1 "" "i")) | |
| 1510 (clobber (reg:SI 31)) | |
| 1511 (use (match_operand 2 "" "")) ;; next_arg_reg | |
| 1512 (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx | |
| 1513 "" | |
| 1514 " | |
| 1515 { | |
| 1516 rtx addr; | |
| 1517 | |
| 1518 if (operands[0]) /* eliminate unused code warnings */ | |
| 1519 { | |
| 1520 addr = XEXP (operands[0], 0); | |
| 1521 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr))) | |
| 1522 || ! call_insn_operand (addr, VOIDmode)) | |
| 1523 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr); | |
| 1524 | |
| 1525 /* In order to pass small structures by value in registers | |
| 1526 compatibly with the IQ2000 compiler, we need to shift the value | |
| 1527 into the high part of the register. Function_arg has encoded | |
| 1528 a PARALLEL rtx, holding a vector of adjustments to be made | |
| 1529 as the next_arg_reg variable, so we split up the insns, | |
| 1530 and emit them separately. */ | |
| 1531 | |
| 1532 if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL) | |
| 1533 { | |
| 1534 rtvec adjust = XVEC (operands[2], 0); | |
| 1535 int num = GET_NUM_ELEM (adjust); | |
| 1536 int i; | |
| 1537 | |
| 1538 for (i = 0; i < num; i++) | |
| 1539 emit_insn (RTVEC_ELT (adjust, i)); | |
| 1540 } | |
| 1541 | |
| 1542 emit_call_insn (gen_call_internal0 (operands[0], operands[1], | |
| 1543 gen_rtx_REG (SImode, | |
| 1544 GP_REG_FIRST + 31))); | |
| 1545 DONE; | |
| 1546 } | |
| 1547 }") | |
| 1548 | |
| 1549 (define_expand "call_internal0" | |
| 1550 [(parallel [(call (match_operand 0 "" "") | |
| 1551 (match_operand 1 "" "")) | |
| 1552 (clobber (match_operand:SI 2 "" ""))])] | |
| 1553 "" | |
| 1554 "") | |
| 1555 | |
| 1556 (define_insn "call_internal1" | |
| 1557 [(call (mem (match_operand 0 "call_insn_operand" "ri")) | |
| 1558 (match_operand 1 "" "i")) | |
| 1559 (clobber (match_operand:SI 2 "register_operand" "=d"))] | |
| 1560 "" | |
| 1561 "* | |
| 1562 { | |
| 1563 register rtx target = operands[0]; | |
| 1564 | |
| 1565 if (GET_CODE (target) == CONST_INT) | |
| 1566 return \"li\\t%@,%0\\n\\tjalr\\t%2,%@\"; | |
| 1567 else if (CONSTANT_ADDRESS_P (target)) | |
| 1568 return \"jal\\t%0\"; | |
| 1569 else | |
| 1570 return \"jalr\\t%2,%0\"; | |
| 1571 }" | |
| 1572 [(set_attr "type" "call") | |
| 1573 (set_attr "mode" "none")]) | |
| 1574 | |
| 1575 ;; calls.c now passes a fourth argument, make saber happy | |
| 1576 | |
| 1577 (define_expand "call_value" | |
|
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diff
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|
1578 [(parallel [(set (match_operand 0 "register_operand" "=d") |
| 0 | 1579 (call (match_operand 1 "memory_operand" "m") |
| 1580 (match_operand 2 "" "i"))) | |
| 1581 (clobber (reg:SI 31)) | |
| 1582 (use (match_operand 3 "" ""))])] ;; next_arg_reg | |
| 1583 "" | |
| 1584 " | |
| 1585 { | |
| 1586 rtx addr; | |
| 1587 | |
| 1588 if (operands[0]) /* eliminate unused code warning */ | |
| 1589 { | |
| 1590 addr = XEXP (operands[1], 0); | |
| 1591 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr))) | |
| 1592 || ! call_insn_operand (addr, VOIDmode)) | |
| 1593 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr); | |
| 1594 | |
| 1595 /* In order to pass small structures by value in registers | |
| 1596 compatibly with the IQ2000 compiler, we need to shift the value | |
| 1597 into the high part of the register. Function_arg has encoded | |
| 1598 a PARALLEL rtx, holding a vector of adjustments to be made | |
| 1599 as the next_arg_reg variable, so we split up the insns, | |
| 1600 and emit them separately. */ | |
| 1601 | |
| 1602 if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL) | |
| 1603 { | |
| 1604 rtvec adjust = XVEC (operands[3], 0); | |
| 1605 int num = GET_NUM_ELEM (adjust); | |
| 1606 int i; | |
| 1607 | |
| 1608 for (i = 0; i < num; i++) | |
| 1609 emit_insn (RTVEC_ELT (adjust, i)); | |
| 1610 } | |
| 1611 | |
| 1612 if (GET_CODE (operands[0]) == PARALLEL && XVECLEN (operands[0], 0) > 1) | |
| 1613 { | |
| 1614 emit_call_insn (gen_call_value_multiple_internal0 | |
| 1615 (XEXP (XVECEXP (operands[0], 0, 0), 0), | |
| 1616 operands[1], operands[2], | |
| 1617 XEXP (XVECEXP (operands[0], 0, 1), 0), | |
| 1618 gen_rtx_REG (SImode, GP_REG_FIRST + 31))); | |
| 1619 DONE; | |
| 1620 } | |
| 1621 | |
| 1622 /* We have a call returning a DImode structure in an FP reg. | |
| 1623 Strip off the now unnecessary PARALLEL. */ | |
| 1624 if (GET_CODE (operands[0]) == PARALLEL) | |
| 1625 operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0); | |
| 1626 | |
| 1627 emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2], | |
| 1628 gen_rtx_REG (SImode, | |
| 1629 GP_REG_FIRST + 31))); | |
| 1630 | |
| 1631 DONE; | |
| 1632 } | |
| 1633 }") | |
| 1634 | |
| 1635 (define_expand "call_value_internal0" | |
| 1636 [(parallel [(set (match_operand 0 "" "") | |
| 1637 (call (match_operand 1 "" "") | |
| 1638 (match_operand 2 "" ""))) | |
| 1639 (clobber (match_operand:SI 3 "" ""))])] | |
| 1640 "" | |
| 1641 "") | |
| 1642 | |
| 1643 (define_insn "call_value_internal1" | |
|
67
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1644 [(set (match_operand 0 "register_operand" "=d") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1645 (call (mem (match_operand 1 "call_insn_operand" "r")) |
| 0 | 1646 (match_operand 2 "" "i"))) |
| 1647 (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| 1648 "" | |
| 1649 "* | |
| 1650 { | |
| 1651 register rtx target = operands[1]; | |
| 1652 | |
| 1653 if (GET_CODE (target) == CONST_INT) | |
| 1654 return \"li\\t%@,%1\\n\\tjalr\\t%3,%@\"; | |
| 1655 else if (CONSTANT_ADDRESS_P (target)) | |
| 1656 return \"jal\\t%1\"; | |
| 1657 else | |
| 1658 return \"jalr\\t%3,%1\"; | |
| 1659 }" | |
| 1660 [(set_attr "type" "call") | |
| 1661 (set_attr "mode" "none")]) | |
| 1662 | |
| 1663 (define_expand "call_value_multiple_internal0" | |
| 1664 [(parallel [(set (match_operand 0 "" "") | |
| 1665 (call (match_operand 1 "" "") | |
| 1666 (match_operand 2 "" ""))) | |
| 1667 (set (match_operand 3 "" "") | |
| 1668 (call (match_dup 1) | |
| 1669 (match_dup 2))) | |
| 1670 (clobber (match_operand:SI 4 "" ""))])] | |
| 1671 "" | |
| 1672 "") | |
| 1673 | |
| 1674 ;; ??? May eventually need all 6 versions of the call patterns with multiple | |
| 1675 ;; return values. | |
| 1676 | |
| 1677 (define_insn "call_value_multiple_internal1" | |
|
67
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1678 [(set (match_operand 0 "register_operand" "=d") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1679 (call (mem (match_operand 1 "call_insn_operand" "r")) |
| 0 | 1680 (match_operand 2 "" "i"))) |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1681 (set (match_operand 3 "register_operand" "=d") |
| 0 | 1682 (call (mem (match_dup 1)) |
| 1683 (match_dup 2))) | |
| 1684 (clobber (match_operand:SI 4 "register_operand" "=d"))] | |
| 1685 "" | |
| 1686 "* | |
| 1687 { | |
| 1688 register rtx target = operands[1]; | |
| 1689 | |
| 1690 if (GET_CODE (target) == CONST_INT) | |
| 1691 return \"li\\t%@,%1\\n\\tjalr\\t%4,%@\"; | |
| 1692 else if (CONSTANT_ADDRESS_P (target)) | |
| 1693 return \"jal\\t%1\"; | |
| 1694 else | |
| 1695 return \"jalr\\t%4,%1\"; | |
| 1696 }" | |
| 1697 [(set_attr "type" "call") | |
| 1698 (set_attr "mode" "none")]) | |
| 1699 | |
| 1700 ;; Call subroutine returning any type. | |
| 1701 | |
| 1702 (define_expand "untyped_call" | |
| 1703 [(parallel [(call (match_operand 0 "" "") | |
| 1704 (const_int 0)) | |
| 1705 (match_operand 1 "" "") | |
| 1706 (match_operand 2 "" "")])] | |
| 1707 "" | |
| 1708 " | |
| 1709 { | |
| 1710 if (operands[0]) /* silence statement not reached warnings */ | |
| 1711 { | |
| 1712 int i; | |
| 1713 | |
| 1714 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx)); | |
| 1715 | |
| 1716 for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
| 1717 { | |
| 1718 rtx set = XVECEXP (operands[2], 0, i); | |
| 1719 emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
| 1720 } | |
| 1721 | |
| 1722 emit_insn (gen_blockage ()); | |
| 1723 DONE; | |
| 1724 } | |
| 1725 }") | |
| 1726 | |
| 1727 ;; | |
| 1728 ;; .................... | |
| 1729 ;; | |
| 1730 ;; MISC. | |
| 1731 ;; | |
| 1732 ;; .................... | |
| 1733 ;; | |
| 1734 | |
| 1735 (define_insn "nop" | |
| 1736 [(const_int 0)] | |
| 1737 "" | |
| 1738 "nop" | |
| 1739 [(set_attr "type" "nop") | |
| 1740 (set_attr "mode" "none")]) | |
| 1741 | |
| 1742 | |
| 1743 ;; For the rare case where we need to load an address into a register | |
| 1744 ;; that cannot be recognized by the normal movsi/addsi instructions. | |
| 1745 ;; I have no idea how many insns this can actually generate. It should | |
| 1746 ;; be rare, so over-estimating as 10 instructions should not have any | |
| 1747 ;; real performance impact. | |
| 1748 (define_insn "leasi" | |
| 1749 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1750 (match_operand:SI 1 "address_operand" "p"))] | |
| 1751 "Pmode == SImode" | |
| 1752 "* | |
| 1753 { | |
| 1754 rtx xoperands [3]; | |
| 1755 | |
| 1756 xoperands[0] = operands[0]; | |
| 1757 xoperands[1] = XEXP (operands[1], 0); | |
| 1758 xoperands[2] = XEXP (operands[1], 1); | |
| 1759 output_asm_insn (\"addiu\\t%0,%1,%2\", xoperands); | |
| 1760 return \"\"; | |
| 1761 }" | |
| 1762 [(set_attr "type" "arith") | |
| 1763 (set_attr "mode" "SI") | |
| 1764 (set_attr "length" "40")]) | |
| 1765 | |
| 1766 (define_insn "ado16" | |
| 1767 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1768 (unspec:SI [(match_operand:SI 1 "register_operand" "r") | |
| 1769 (match_operand:SI 2 "register_operand" "r")] | |
| 1770 UNSPEC_ADO16))] | |
| 1771 "" | |
| 1772 "ado16\\t%0, %1, %2" | |
| 1773 ) | |
| 1774 | |
| 1775 (define_insn "ram" | |
| 1776 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1777 (unspec:SI [(match_operand:SI 1 "register_operand" "r") | |
| 1778 (match_operand:SI 2 "const_int_operand" "I") | |
| 1779 (match_operand:SI 3 "const_int_operand" "I") | |
| 1780 (match_operand:SI 4 "const_int_operand" "I")] | |
| 1781 UNSPEC_RAM))] | |
| 1782 "" | |
| 1783 "ram\\t%0, %1, %2, %3, %4" | |
| 1784 ) | |
| 1785 | |
| 1786 (define_insn "chkhdr" | |
| 1787 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "=r") | |
| 1788 (match_operand:SI 1 "register_operand" "r")] | |
| 1789 UNSPEC_CHKHDR)] | |
| 1790 "" | |
| 1791 "* return iq2000_fill_delay_slot (\"chkhdr\\t%0, %1\", DELAY_LOAD, operands, insn);" | |
| 1792 [(set_attr "dslot" "not_in_dslot")] | |
| 1793 ) | |
| 1794 | |
| 1795 (define_insn "pkrl" | |
| 1796 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1797 (match_operand:SI 1 "register_operand" "r")] | |
| 1798 UNSPEC_PKRL)] | |
| 1799 "" | |
| 1800 "* return iq2000_fill_delay_slot (\"pkrl\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 1801 [(set_attr "dslot" "not_in_dslot")] | |
| 1802 ) | |
| 1803 | |
| 1804 (define_insn "cfc0" | |
| 1805 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1806 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1807 UNSPEC_CFC0))] | |
| 1808 "" | |
| 1809 "* return iq2000_fill_delay_slot (\"cfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1810 [(set_attr "dslot" "ok_in_dslot")] | |
| 1811 ) | |
| 1812 | |
| 1813 (define_insn "cfc1" | |
| 1814 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1815 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1816 UNSPEC_CFC1))] | |
| 1817 "" | |
| 1818 "* return iq2000_fill_delay_slot (\"cfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1819 [(set_attr "dslot" "ok_in_dslot")] | |
| 1820 ) | |
| 1821 | |
| 1822 (define_insn "cfc2" | |
| 1823 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1824 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1825 UNSPEC_CFC2))] | |
| 1826 "" | |
| 1827 "* return iq2000_fill_delay_slot (\"cfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1828 [(set_attr "dslot" "not_in_dslot")] | |
| 1829 ) | |
| 1830 | |
| 1831 (define_insn "cfc3" | |
| 1832 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1833 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1834 UNSPEC_CFC3))] | |
| 1835 "" | |
| 1836 "* return iq2000_fill_delay_slot (\"cfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1837 [(set_attr "dslot" "not_in_dslot")] | |
| 1838 ) | |
| 1839 | |
| 1840 (define_insn "ctc0" | |
| 1841 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ") | |
| 1842 (match_operand:SI 1 "const_int_operand" "I")] | |
| 1843 UNSPEC_CTC0)] | |
| 1844 "" | |
| 1845 "* return iq2000_fill_delay_slot (\"ctc0\\t%z0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1846 [(set_attr "dslot" "ok_in_dslot")] | |
| 1847 ) | |
| 1848 | |
| 1849 (define_insn "ctc1" | |
| 1850 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ") | |
| 1851 (match_operand:SI 1 "const_int_operand" "I")] | |
| 1852 UNSPEC_CTC1)] | |
| 1853 "" | |
| 1854 "* return iq2000_fill_delay_slot (\"ctc1\\t%z0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1855 [(set_attr "dslot" "ok_in_dslot")] | |
| 1856 ) | |
| 1857 | |
| 1858 (define_insn "ctc2" | |
| 1859 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ") | |
| 1860 (match_operand:SI 1 "const_int_operand" "I")] | |
| 1861 UNSPEC_CTC2)] | |
| 1862 "" | |
| 1863 "* return iq2000_fill_delay_slot (\"ctc2\\t%z0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1864 [(set_attr "dslot" "ok_in_dslot")] | |
| 1865 ) | |
| 1866 | |
| 1867 (define_insn "ctc3" | |
| 1868 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ") | |
| 1869 (match_operand:SI 1 "const_int_operand" "I")] | |
| 1870 UNSPEC_CTC3)] | |
| 1871 "" | |
| 1872 "* return iq2000_fill_delay_slot (\"ctc3\\t%z0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1873 [(set_attr "dslot" "ok_in_dslot")] | |
| 1874 ) | |
| 1875 | |
| 1876 (define_insn "mfc0" | |
| 1877 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1878 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1879 UNSPEC_MFC0))] | |
| 1880 "" | |
| 1881 "* return iq2000_fill_delay_slot (\"mfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1882 [(set_attr "dslot" "ok_in_dslot")] | |
| 1883 ) | |
| 1884 | |
| 1885 (define_insn "mfc1" | |
| 1886 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1887 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1888 UNSPEC_MFC1))] | |
| 1889 "" | |
| 1890 "* return iq2000_fill_delay_slot (\"mfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1891 [(set_attr "dslot" "ok_in_dslot")] | |
| 1892 ) | |
| 1893 | |
| 1894 (define_insn "mfc2" | |
| 1895 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1896 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1897 UNSPEC_MFC2))] | |
| 1898 "" | |
| 1899 "* return iq2000_fill_delay_slot (\"mfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1900 [(set_attr "dslot" "not_in_dslot")] | |
| 1901 ) | |
| 1902 | |
| 1903 (define_insn "mfc3" | |
| 1904 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1905 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1906 UNSPEC_MFC3))] | |
| 1907 "" | |
| 1908 "* return iq2000_fill_delay_slot (\"mfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1909 [(set_attr "dslot" "not_in_dslot")] | |
| 1910 ) | |
| 1911 | |
| 1912 (define_insn "mtc0" | |
| 1913 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1914 (match_operand:SI 1 "const_int_operand" "I")] | |
| 1915 UNSPEC_MTC0)] | |
| 1916 "" | |
| 1917 "* return iq2000_fill_delay_slot (\"mtc0\\t%0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1918 [(set_attr "dslot" "ok_in_dslot")] | |
| 1919 ) | |
| 1920 | |
| 1921 (define_insn "mtc1" | |
| 1922 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1923 (match_operand:SI 1 "const_int_operand" "I")] | |
| 1924 UNSPEC_MTC1)] | |
| 1925 "" | |
| 1926 "* return iq2000_fill_delay_slot (\"mtc1\\t%0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1927 [(set_attr "dslot" "ok_in_dslot")] | |
| 1928 ) | |
| 1929 | |
| 1930 (define_insn "mtc2" | |
| 1931 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1932 (match_operand:SI 1 "const_int_operand" "I")] | |
| 1933 UNSPEC_MTC2)] | |
| 1934 "" | |
| 1935 "* return iq2000_fill_delay_slot (\"mtc2\\t%0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1936 [(set_attr "dslot" "ok_in_dslot")] | |
| 1937 ) | |
| 1938 | |
| 1939 (define_insn "mtc3" | |
| 1940 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1941 (match_operand:SI 1 "const_int_operand" "I")] | |
| 1942 UNSPEC_MTC3)] | |
| 1943 "" | |
| 1944 "* return iq2000_fill_delay_slot (\"mtc3\\t%0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1945 [(set_attr "dslot" "ok_in_dslot")] | |
| 1946 ) | |
| 1947 | |
| 1948 (define_insn "lur" | |
| 1949 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1950 (match_operand:SI 1 "register_operand" "r")] | |
| 1951 UNSPEC_LUR)] | |
| 1952 "" | |
| 1953 "* return iq2000_fill_delay_slot (\"lur\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 1954 [(set_attr "dslot" "not_in_dslot")] | |
| 1955 ) | |
| 1956 | |
| 1957 (define_insn "rb" | |
| 1958 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1959 (match_operand:SI 1 "register_operand" "r")] | |
| 1960 UNSPEC_RB)] | |
| 1961 "" | |
| 1962 "* return iq2000_fill_delay_slot (\"rb\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 1963 [(set_attr "dslot" "not_in_dslot")] | |
| 1964 ) | |
| 1965 | |
| 1966 (define_insn "rx" | |
| 1967 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1968 (match_operand:SI 1 "register_operand" "r")] | |
| 1969 UNSPEC_RX)] | |
| 1970 "" | |
| 1971 "* return iq2000_fill_delay_slot (\"rx\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 1972 [(set_attr "dslot" "not_in_dslot")] | |
| 1973 ) | |
| 1974 | |
| 1975 (define_insn "srrd" | |
| 1976 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
| 1977 UNSPEC_SRRD)] | |
| 1978 "" | |
| 1979 "* return iq2000_fill_delay_slot (\"srrd\\t%0\", DELAY_NONE, operands, insn);" | |
| 1980 [(set_attr "dslot" "not_in_dslot")] | |
| 1981 ) | |
| 1982 | |
| 1983 (define_insn "srwr" | |
| 1984 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1985 (match_operand:SI 1 "register_operand" "r")] | |
| 1986 UNSPEC_SRWR)] | |
| 1987 "" | |
| 1988 "* return iq2000_fill_delay_slot (\"srwr\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 1989 [(set_attr "dslot" "not_in_dslot")] | |
| 1990 ) | |
| 1991 | |
| 1992 (define_insn "wb" | |
| 1993 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1994 (match_operand:SI 1 "register_operand" "r")] | |
| 1995 UNSPEC_WB)] | |
| 1996 "" | |
| 1997 "* return iq2000_fill_delay_slot (\"wb\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 1998 [(set_attr "dslot" "not_in_dslot")] | |
| 1999 ) | |
| 2000 | |
| 2001 (define_insn "wx" | |
| 2002 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2003 (match_operand:SI 1 "register_operand" "r")] | |
| 2004 UNSPEC_WX)] | |
| 2005 "" | |
| 2006 "* return iq2000_fill_delay_slot (\"wx\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2007 [(set_attr "dslot" "not_in_dslot")] | |
| 2008 ) | |
| 2009 | |
| 2010 (define_insn "luc32" | |
| 2011 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2012 (match_operand:SI 1 "register_operand" "r")] | |
| 2013 UNSPEC_LUC32)] | |
| 2014 "" | |
| 2015 "* return iq2000_fill_delay_slot (\"luc32\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2016 [(set_attr "dslot" "not_in_dslot")] | |
| 2017 ) | |
| 2018 | |
| 2019 (define_insn "luc32l" | |
| 2020 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2021 (match_operand:SI 1 "register_operand" "r")] | |
| 2022 UNSPEC_LUC32L)] | |
| 2023 "" | |
| 2024 "* return iq2000_fill_delay_slot (\"luc32l\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2025 [(set_attr "dslot" "not_in_dslot")] | |
| 2026 ) | |
| 2027 | |
| 2028 (define_insn "luc64" | |
| 2029 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2030 (match_operand:SI 1 "register_operand" "r")] | |
| 2031 UNSPEC_LUC64)] | |
| 2032 "" | |
| 2033 "* return iq2000_fill_delay_slot (\"luc64\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2034 [(set_attr "dslot" "not_in_dslot")] | |
| 2035 ) | |
| 2036 | |
| 2037 (define_insn "luc64l" | |
| 2038 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2039 (match_operand:SI 1 "register_operand" "r")] | |
| 2040 UNSPEC_LUC64L)] | |
| 2041 "" | |
| 2042 "* return iq2000_fill_delay_slot (\"luc64l\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2043 [(set_attr "dslot" "not_in_dslot")] | |
| 2044 ) | |
| 2045 | |
| 2046 (define_insn "luk" | |
| 2047 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2048 (match_operand:SI 1 "register_operand" "r")] | |
| 2049 UNSPEC_LUK)] | |
| 2050 "" | |
| 2051 "* return iq2000_fill_delay_slot (\"luk\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2052 [(set_attr "dslot" "ok_in_dslot")] | |
| 2053 ) | |
| 2054 | |
| 2055 (define_insn "lulck" | |
| 2056 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
| 2057 UNSPEC_LULCK)] | |
| 2058 "" | |
| 2059 "* return iq2000_fill_delay_slot (\"lulck\\t%0\", DELAY_NONE, operands, insn);" | |
| 2060 [(set_attr "dslot" "not_in_dslot")] | |
| 2061 ) | |
| 2062 | |
| 2063 (define_insn "lum32" | |
| 2064 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2065 (match_operand:SI 1 "register_operand" "r")] | |
| 2066 UNSPEC_LUM32)] | |
| 2067 "" | |
| 2068 "* return iq2000_fill_delay_slot (\"lum32\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2069 [(set_attr "dslot" "not_in_dslot")] | |
| 2070 ) | |
| 2071 | |
| 2072 (define_insn "lum32l" | |
| 2073 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2074 (match_operand:SI 1 "register_operand" "r")] | |
| 2075 UNSPEC_LUM32L)] | |
| 2076 "" | |
| 2077 "* return iq2000_fill_delay_slot (\"lum32l\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2078 [(set_attr "dslot" "not_in_dslot")] | |
| 2079 ) | |
| 2080 | |
| 2081 (define_insn "lum64" | |
| 2082 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2083 (match_operand:SI 1 "register_operand" "r")] | |
| 2084 UNSPEC_LUM64)] | |
| 2085 "" | |
| 2086 "* return iq2000_fill_delay_slot (\"lum64\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2087 [(set_attr "dslot" "not_in_dslot")] | |
| 2088 ) | |
| 2089 | |
| 2090 (define_insn "lum64l" | |
| 2091 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2092 (match_operand:SI 1 "register_operand" "r")] | |
| 2093 UNSPEC_LUM64L)] | |
| 2094 "" | |
| 2095 "* return iq2000_fill_delay_slot (\"lum64l\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2096 [(set_attr "dslot" "not_in_dslot")] | |
| 2097 ) | |
| 2098 | |
| 2099 (define_insn "lurl" | |
| 2100 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2101 (match_operand:SI 1 "register_operand" "r")] | |
| 2102 UNSPEC_LURL)] | |
| 2103 "" | |
| 2104 "* return iq2000_fill_delay_slot (\"lurl\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2105 [(set_attr "dslot" "not_in_dslot")] | |
| 2106 ) | |
| 2107 | |
| 2108 (define_insn "mrgb" | |
| 2109 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 2110 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r") | |
| 2111 (match_operand:SI 2 "register_operand" "r") | |
| 2112 (match_operand:SI 3 "const_int_operand" "I")] | |
| 2113 UNSPEC_MRGB))] | |
| 2114 "" | |
| 2115 "* return iq2000_fill_delay_slot (\"mrgb\\t%0, %1, %2, %3\", DELAY_LOAD, operands, insn);" | |
| 2116 [(set_attr "dslot" "ok_in_dslot")] | |
| 2117 ) | |
| 2118 | |
| 2119 (define_insn "srrdl" | |
| 2120 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
| 2121 UNSPEC_SRRDL)] | |
| 2122 "" | |
| 2123 "* return iq2000_fill_delay_slot (\"srrdl\\t%0\", DELAY_NONE, operands, insn);" | |
| 2124 [(set_attr "dslot" "not_in_dslot")] | |
| 2125 ) | |
| 2126 | |
| 2127 (define_insn "srulck" | |
| 2128 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
| 2129 UNSPEC_SRULCK)] | |
| 2130 "" | |
| 2131 "* return iq2000_fill_delay_slot (\"srulck\\t%0\", DELAY_NONE, operands, insn);" | |
| 2132 [(set_attr "dslot" "not_in_dslot")] | |
| 2133 ) | |
| 2134 | |
| 2135 (define_insn "srwru" | |
| 2136 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2137 (match_operand:SI 1 "register_operand" "r")] | |
| 2138 UNSPEC_SRWRU)] | |
| 2139 "" | |
| 2140 "* return iq2000_fill_delay_slot (\"srwru\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2141 [(set_attr "dslot" "not_in_dslot")] | |
| 2142 ) | |
| 2143 | |
| 2144 (define_insn "trapqfl" | |
| 2145 [(unspec_volatile:SI [(const_int 1)] UNSPEC_TRAPQFL)] | |
| 2146 "" | |
| 2147 "* return iq2000_fill_delay_slot (\"trapqfl\", DELAY_NONE, operands, insn);" | |
| 2148 [(set_attr "dslot" "not_in_dslot")] | |
| 2149 ) | |
| 2150 | |
| 2151 (define_insn "trapqne" | |
| 2152 [(unspec_volatile:SI [(const_int 2)] UNSPEC_TRAPQNE)] | |
| 2153 "" | |
| 2154 "* return iq2000_fill_delay_slot (\"trapqne\", DELAY_NONE, operands, insn);" | |
| 2155 [(set_attr "dslot" "not_in_dslot")] | |
| 2156 ) | |
| 2157 | |
| 2158 (define_insn "traprel" | |
| 2159 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
| 2160 UNSPEC_TRAPREL)] | |
| 2161 "" | |
| 2162 "* return iq2000_fill_delay_slot (\"traprel %0\", DELAY_NONE, operands, insn);" | |
| 2163 [(set_attr "dslot" "not_in_dslot")] | |
| 2164 ) | |
| 2165 | |
| 2166 (define_insn "wbu" | |
| 2167 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2168 (match_operand:SI 1 "register_operand" "r")] | |
| 2169 UNSPEC_WBU)] | |
| 2170 "" | |
| 2171 "* return iq2000_fill_delay_slot (\"wbu\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2172 [(set_attr "dslot" "not_in_dslot")] | |
| 2173 ) | |
| 2174 | |
| 2175 (define_insn "syscall" | |
| 2176 [(unspec_volatile:SI [(const_int 2)] UNSPEC_SYSCALL)] | |
| 2177 "" | |
| 2178 "syscall" | |
| 2179 [(set_attr "dslot" "not_in_dslot")] | |
| 2180 ) |