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annotate gcc/config/rs6000/rs6000.opt @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents 77e2b8dfacca
children 04ced10e8804
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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1 ; Options for the rs6000 port of the compiler
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2 ;
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3 ; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010 Free Software
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4 ; Foundation, Inc.
0
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5 ; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
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6 ;
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7 ; This file is part of GCC.
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8 ;
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9 ; GCC is free software; you can redistribute it and/or modify it under
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10 ; the terms of the GNU General Public License as published by the Free
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11 ; Software Foundation; either version 3, or (at your option) any later
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12 ; version.
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13 ;
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14 ; GCC is distributed in the hope that it will be useful, but WITHOUT
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15 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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16 ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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17 ; License for more details.
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18 ;
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19 ; You should have received a copy of the GNU General Public License
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20 ; along with GCC; see the file COPYING3. If not see
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21 ; <http://www.gnu.org/licenses/>.
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23 HeaderInclude
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24 config/rs6000/rs6000-opts.h
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25
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26 ;; Current processor
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27 TargetVariable
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28 enum processor_type rs6000_cpu = PROCESSOR_RIOS1
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29
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30 ;; Always emit branch hint bits.
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31 TargetVariable
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32 unsigned char rs6000_always_hint
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33
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34 ;; Schedule instructions for group formation.
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35 TargetVariable
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36 unsigned char rs6000_sched_groups
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37
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38 ;; Align branch targets.
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39 TargetVariable
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40 unsigned char rs6000_align_branch_targets
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41
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42 ;; Support for -msched-costly-dep option.
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43 TargetVariable
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44 enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly
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45
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46 ;; Support for -minsert-sched-nops option.
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47 TargetVariable
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48 enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none
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49
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50 ;; Size of long double.
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51 TargetVariable
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52 unsigned char rs6000_long_double_type_size
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53
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54 ;; IEEE quad extended precision long double.
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55 TargetVariable
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56 unsigned char rs6000_ieeequad
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57
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58 ;; Nonzero to use AltiVec ABI.
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59 TargetVariable
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60 unsigned char rs6000_altivec_abi
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61
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62 ;; Nonzero if we want SPE SIMD instructions.
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63 TargetVariable
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64 int rs6000_spe
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65
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66 ;; Nonzero if we want SPE ABI extensions.
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67 TargetVariable
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68 unsigned char rs6000_spe_abi
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69
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70 ;; Nonzero if floating point operations are done in the GPRs.
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71 TargetVariable
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72 unsigned char rs6000_float_gprs
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73
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74 ;; Nonzero if we want Darwin's struct-by-value-in-regs ABI.
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75 TargetVariable
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76 unsigned char rs6000_darwin64_abi
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77
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78 ;; Non-zero to allow overriding loop alignment.
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79 TargetVariable
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80 unsigned char can_override_loop_align
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81
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82 ;; Which small data model to use (for System V targets only)
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83 TargetVariable
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84 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA
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85
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86 ;; Bit size of immediate TLS offsets and string from which it is decoded.
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87 TargetVariable
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88 int rs6000_tls_size = 32
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89
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90 ;; ABI enumeration available for subtarget to use.
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91 TargetVariable
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92 enum rs6000_abi rs6000_current_abi = ABI_NONE
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93
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94 ;; Type of traceback to use.
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95 TargetVariable
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96 enum rs6000_traceback_type rs6000_traceback = traceback_default
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97
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98 ;; Control alignment for fields within structures.
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99 TargetVariable
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100 unsigned char rs6000_alignment_flags
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101
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102 ;; Code model for 64-bit linux.
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103 TargetVariable
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104 enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL
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105
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106 ;; What type of reciprocal estimation instructions to generate
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107 TargetVariable
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108 unsigned int rs6000_recip_control
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109
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110 ;; -mcpu=<xxx> as an index into the processor_target_table or -1
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111 TargetVariable
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112 int rs6000_cpu_index = -1
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113
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114 ;; -mtune=<xxx> as an index into the processor_target_table or -1
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115 TargetVariable
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116 int rs6000_tune_index = -1
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117
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118 ;; Debug flags
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119 TargetVariable
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120 unsigned int rs6000_debug
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121
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122 ;; Save for target_flags_explicit
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123 TargetSave
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124 int rs6000_target_flags_explicit
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125
0
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126 mpower
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127 Target Report RejectNegative Mask(POWER)
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128 Use POWER instruction set
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129
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130 mno-power
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131 Target Report RejectNegative
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132 Do not use POWER instruction set
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133
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134 mpower2
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135 Target Report Mask(POWER2)
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136 Use POWER2 instruction set
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137
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138 mpowerpc
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139 Target Report RejectNegative Mask(POWERPC)
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140 Use PowerPC instruction set
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141
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142 mno-powerpc
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143 Target Report RejectNegative
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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144 Do not use PowerPC instruction set
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145
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146 mpowerpc64
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147 Target Report Mask(POWERPC64)
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148 Use PowerPC-64 instruction set
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149
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150 mpowerpc-gpopt
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151 Target Report Mask(PPC_GPOPT) Save
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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152 Use PowerPC General Purpose group optional instructions
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153
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154 mpowerpc-gfxopt
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155 Target Report Mask(PPC_GFXOPT) Save
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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156 Use PowerPC Graphics group optional instructions
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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157
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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158 mmfcrf
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159 Target Report Mask(MFCRF) Save
0
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160 Use PowerPC V2.01 single field mfcr instruction
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161
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162 mpopcntb
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163 Target Report Mask(POPCNTB) Save
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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164 Use PowerPC V2.02 popcntb instruction
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165
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166 mfprnd
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167 Target Report Mask(FPRND) Save
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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168 Use PowerPC V2.02 floating point rounding instructions
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169
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170 mcmpb
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171 Target Report Mask(CMPB) Save
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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172 Use PowerPC V2.05 compare bytes instruction
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173
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174 mmfpgpr
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175 Target Report Mask(MFPGPR) Save
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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176 Use extended PowerPC V2.05 move floating point to/from GPR instructions
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177
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178 maltivec
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diff changeset
179 Target Report Mask(ALTIVEC) Save
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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180 Use AltiVec instructions
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181
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182 mhard-dfp
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183 Target Report Mask(DFP) Save
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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184 Use decimal floating point instructions
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185
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186 mmulhw
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187 Target Report Mask(MULHW) Save
0
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188 Use 4xx half-word multiply instructions
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189
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190 mdlmzb
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191 Target Report Mask(DLMZB) Save
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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192 Use 4xx string-search dlmzb instruction
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193
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194 mmultiple
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195 Target Report Mask(MULTIPLE) Save
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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196 Generate load/store multiple instructions
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197
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198 mstring
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199 Target Report Mask(STRING) Save
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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200 Generate string instructions for block moves
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201
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202 mnew-mnemonics
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203 Target Report RejectNegative Mask(NEW_MNEMONICS)
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204 Use new mnemonics for PowerPC architecture
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205
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206 mold-mnemonics
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207 Target Report RejectNegative InverseMask(NEW_MNEMONICS)
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208 Use old mnemonics for PowerPC architecture
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209
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210 msoft-float
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211 Target Report RejectNegative Mask(SOFT_FLOAT)
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212 Do not use hardware floating point
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213
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214 mhard-float
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215 Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT)
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216 Use hardware floating point
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217
55
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218 mpopcntd
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219 Target Report Mask(POPCNTD) Save
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220 Use PowerPC V2.06 popcntd instruction
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221
67
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diff changeset
222 mfriz
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223 Target Report Var(TARGET_FRIZ) Init(-1) Save
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224 Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions
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225
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226 mveclibabi=
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227 Target RejectNegative Joined Var(rs6000_veclibabi_name)
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228 Vector library ABI to use
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229
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230 mvsx
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231 Target Report Mask(VSX) Save
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diff changeset
232 Use vector/scalar (VSX) instructions
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233
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234 mvsx-scalar-double
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diff changeset
235 Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(-1)
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236 ; If -mvsx, use VSX arithmetic instructions for scalar double (on by default)
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237
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238 mvsx-scalar-memory
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diff changeset
239 Target Undocumented Report Var(TARGET_VSX_SCALAR_MEMORY)
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240 ; If -mvsx, use VSX scalar memory reference instructions for scalar double (off by default)
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241
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242 mvsx-align-128
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diff changeset
243 Target Undocumented Report Var(TARGET_VSX_ALIGN_128)
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244 ; If -mvsx, set alignment to 128 bits instead of 32/64
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245
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246 mallow-movmisalign
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247 Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1)
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248 ; Allow/disallow the movmisalign in DF/DI vectors
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249
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250 mallow-df-permute
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diff changeset
251 Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE)
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252 ; Allow/disallow permutation of DF/DI vectors
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253
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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254 msched-groups
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diff changeset
255 Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1)
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256 ; Explicitly set/unset whether rs6000_sched_groups is set
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257
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258 malways-hint
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259 Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1)
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260 ; Explicitly set/unset whether rs6000_always_hint is set
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261
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262 malign-branch-targets
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263 Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1)
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264 ; Explicitly set/unset whether rs6000_align_branch_targets is set
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diff changeset
265
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diff changeset
266 mvectorize-builtins
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diff changeset
267 Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1)
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268 ; Explicitly control whether we vectorize the builtins or not.
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269
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270 mno-update
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271 Target Report RejectNegative Mask(NO_UPDATE) Save
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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272 Do not generate load/store with update instructions
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273
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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274 mupdate
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275 Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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276 Generate load/store with update instructions
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277
67
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278 msingle-pic-base
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279 Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0)
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280 Do not load the PIC register in function prologues
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281
0
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282 mavoid-indexed-addresses
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283 Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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284 Avoid generation of indexed load/store instructions when possible
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285
55
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286 mtls-markers
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287 Target Report Var(tls_markers) Init(1) Save
55
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diff changeset
288 Mark __tls_get_addr calls with argument info
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289
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290 msched-epilog
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291 Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save
55
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292
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293 msched-prolog
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294 Target Report Var(TARGET_SCHED_PROLOG) Save
55
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diff changeset
295 Schedule the start and end of the procedure
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296
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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297 maix-struct-return
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298 Target Report RejectNegative Var(aix_struct_return) Save
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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299 Return all structures in memory (AIX default)
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300
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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301 msvr4-struct-return
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302 Target Report RejectNegative Var(aix_struct_return,0) Save
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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303 Return small structures in registers (SVR4 default)
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304
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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305 mxl-compat
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306 Target Report Var(TARGET_XL_COMPAT) Save
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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307 Conform more closely to IBM XLC semantics
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308
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309 mrecip
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310 Target Report
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311 Generate software reciprocal divide and square root for better throughput.
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312
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313 mrecip=
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314 Target Report RejectNegative Joined
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315 Generate software reciprocal divide and square root for better throughput.
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316
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diff changeset
317 mrecip-precision
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318 Target Report Mask(RECIP_PRECISION) Save
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diff changeset
319 Assume that the reciprocal estimate instructions provide more accuracy.
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320
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321 mno-fp-in-toc
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322 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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323 Do not place floating point constants in TOC
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324
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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325 mfp-in-toc
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326 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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327 Place floating point constants in TOC
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328
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329 mno-sum-in-toc
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330 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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331 Do not place symbol+offset constants in TOC
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332
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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333 msum-in-toc
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334 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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diff changeset
335 Place symbol+offset constants in TOC
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336
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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337 ; Output only one TOC entry per module. Normally linking fails if
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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338 ; there are more than 16K unique variables/constants in an executable. With
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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339 ; this option, linking fails only if there are more than 16K modules, or
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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340 ; if there are more than 16K unique variables/constant in a single module.
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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341 ;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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342 ; This is at the cost of having 2 extra loads and one extra store per
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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343 ; function, and one less allocable register.
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344 mminimal-toc
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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345 Target Report Mask(MINIMAL_TOC)
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346 Use only one TOC entry per procedure
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347
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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348 mfull-toc
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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349 Target Report
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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350 Put everything in the regular TOC
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351
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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352 mvrsave
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diff changeset
353 Target Report Var(TARGET_ALTIVEC_VRSAVE) Save
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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354 Generate VRSAVE instructions when generating AltiVec code
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355
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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diff changeset
356 mvrsave=
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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diff changeset
357 Target RejectNegative Joined
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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358 -mvrsave=yes/no Deprecated option. Use -mvrsave/-mno-vrsave instead
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359
67
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diff changeset
360 mblock-move-inline-limit=
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361 Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save
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diff changeset
362 Specify how many bytes should be moved inline before calling out to memcpy/memmove
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363
0
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364 misel
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diff changeset
365 Target Report Mask(ISEL) Save
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
366 Generate isel instructions
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367
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368 misel=
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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diff changeset
369 Target RejectNegative Joined
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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370 -misel=yes/no Deprecated option. Use -misel/-mno-isel instead
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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diff changeset
371
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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372 mspe
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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diff changeset
373 Target
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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374 Generate SPE SIMD instructions on E500
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375
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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376 mpaired
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377 Target Var(rs6000_paired_float) Save
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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378 Generate PPC750CL paired-single instructions
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379
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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380 mspe=
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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diff changeset
381 Target RejectNegative Joined
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
382 -mspe=yes/no Deprecated option. Use -mspe/-mno-spe instead
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
383
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
384 mdebug=
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
385 Target RejectNegative Joined
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
386 -mdebug= Enable debug output
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
387
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
388 mabi=
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
389 Target RejectNegative Joined
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
390 -mabi= Specify ABI to use
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
391
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
392 mcpu=
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
393 Target RejectNegative Joined
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
394 -mcpu= Use features of and schedule code for given CPU
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
395
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
396 mtune=
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
397 Target RejectNegative Joined
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
398 -mtune= Schedule code for given CPU
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
399
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
400 mtraceback=
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
401 Target RejectNegative Joined
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
402 -mtraceback= Select full, part, or no traceback table
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
403
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
404 mlongcall
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
405 Target Report Var(rs6000_default_long_calls) Save
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
406 Avoid all range limits on call instructions
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
407
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
408 mgen-cell-microcode
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
409 Target Report Var(rs6000_gen_cell_microcode) Init(-1) Save
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
410 Generate Cell microcode
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
411
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
412 mwarn-cell-microcode
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
413 Target Var(rs6000_warn_cell_microcode) Init(0) Warning Save
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
414 Warn when a Cell microcoded instruction is emitted
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
415
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
416 mwarn-altivec-long
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
417 Target Var(rs6000_warn_altivec_long) Init(1) Save
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
418 Warn about deprecated 'vector long ...' AltiVec type usage
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
419
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
420 mfloat-gprs=
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
421 Target RejectNegative Joined
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
422 -mfloat-gprs= Select GPR floating point method
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
423
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
424 mlong-double-
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
425 Target RejectNegative Joined UInteger
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
426 -mlong-double-<n> Specify size of long double (64 or 128 bits)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
427
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
428 msched-costly-dep=
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
429 Target RejectNegative Joined
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
430 Determine which dependences between insns are considered costly
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
431
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
432 minsert-sched-nops=
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
433 Target RejectNegative Joined
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
434 Specify which post scheduling nop insertion scheme to apply
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
435
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
436 malign-
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
437 Target RejectNegative Joined
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
438 Specify alignment of structure fields default/natural
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
439
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
440 mprioritize-restricted-insns=
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
441 Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
442 Specify scheduling priority for dispatch slot restricted insns
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
443
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
444 msingle-float
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
445 Target RejectNegative Var(rs6000_single_float) Save
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
446 Single-precision floating point unit
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
447
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
448 mdouble-float
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
449 Target RejectNegative Var(rs6000_double_float) Save
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
450 Double-precision floating point unit
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
451
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
452 msimple-fpu
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
453 Target RejectNegative Var(rs6000_simple_fpu) Save
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
454 Floating point unit does not support divide & sqrt
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
455
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
456 mfpu=
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
457 Target RejectNegative Joined
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
458 -mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
459
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
460 mxilinx-fpu
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
461 Target Var(rs6000_xilinx_fpu) Save
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
462 Specify Xilinx FPU.
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
463
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
464