Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/rs6000/rs6000.h @ 158:494b0b89df80 default tip
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| author | Shinji KONO <kono@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Mon, 25 May 2020 18:13:55 +0900 |
| parents | 1830386684a0 |
| children |
| rev | line source |
|---|---|
| 0 | 1 /* Definitions of target machine for GNU compiler, for IBM RS/6000. |
| 145 | 2 Copyright (C) 1992-2020 Free Software Foundation, Inc. |
| 0 | 3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
| 4 | |
| 5 This file is part of GCC. | |
| 6 | |
| 7 GCC is free software; you can redistribute it and/or modify it | |
| 8 under the terms of the GNU General Public License as published | |
| 9 by the Free Software Foundation; either version 3, or (at your | |
| 10 option) any later version. | |
| 11 | |
| 12 GCC is distributed in the hope that it will be useful, but WITHOUT | |
| 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 15 License for more details. | |
| 16 | |
| 17 Under Section 7 of GPL version 3, you are granted additional | |
| 18 permissions described in the GCC Runtime Library Exception, version | |
| 19 3.1, as published by the Free Software Foundation. | |
| 20 | |
| 21 You should have received a copy of the GNU General Public License and | |
| 22 a copy of the GCC Runtime Library Exception along with this program; | |
| 23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
| 24 <http://www.gnu.org/licenses/>. */ | |
| 25 | |
| 26 /* Note that some other tm.h files include this one and then override | |
| 27 many of the definitions. */ | |
| 28 | |
|
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29 #ifndef RS6000_OPTS_H |
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30 #include "config/rs6000/rs6000-opts.h" |
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31 #endif |
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32 |
| 131 | 33 /* 128-bit floating point precision values. */ |
| 34 #ifndef RS6000_MODES_H | |
| 35 #include "config/rs6000/rs6000-modes.h" | |
| 36 #endif | |
| 37 | |
| 0 | 38 /* Definitions for the object file format. These are set at |
| 39 compile-time. */ | |
| 40 | |
| 41 #define OBJECT_XCOFF 1 | |
| 42 #define OBJECT_ELF 2 | |
| 43 #define OBJECT_MACHO 4 | |
| 44 | |
| 45 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) | |
| 46 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) | |
| 47 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) | |
| 48 | |
| 49 #ifndef TARGET_AIX | |
| 50 #define TARGET_AIX 0 | |
| 51 #endif | |
| 52 | |
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53 #ifndef TARGET_AIX_OS |
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54 #define TARGET_AIX_OS 0 |
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55 #endif |
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56 |
| 145 | 57 /* Turn off TOC support if pc-relative addressing is used. */ |
| 58 #define TARGET_TOC (TARGET_HAS_TOC && !TARGET_PCREL) | |
| 59 | |
| 60 /* On 32-bit systems without a TOC or pc-relative addressing, we need to use | |
| 61 ADDIS/ADDI to load up the address of a symbol. */ | |
| 62 #define TARGET_NO_TOC_OR_PCREL (!TARGET_HAS_TOC && !TARGET_PCREL) | |
| 63 | |
| 0 | 64 /* Control whether function entry points use a "dot" symbol when |
| 65 ABI_AIX. */ | |
| 66 #define DOT_SYMBOLS 1 | |
| 67 | |
| 68 /* Default string to use for cpu if not specified. */ | |
| 69 #ifndef TARGET_CPU_DEFAULT | |
| 70 #define TARGET_CPU_DEFAULT ((char *)0) | |
| 71 #endif | |
| 72 | |
| 73 /* If configured for PPC405, support PPC405CR Erratum77. */ | |
| 74 #ifdef CONFIG_PPC405CR | |
| 75 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) | |
| 76 #else | |
| 77 #define PPC405_ERRATUM77 0 | |
| 78 #endif | |
| 79 | |
| 145 | 80 #ifndef SUBTARGET_DRIVER_SELF_SPECS |
| 81 # define SUBTARGET_DRIVER_SELF_SPECS "" | |
| 82 #endif | |
| 83 | |
| 84 /* Only for use in the testsuite: -mdejagnu-cpu= simply overrides -mcpu=. | |
| 85 With older versions of Dejagnu the command line arguments you set in | |
| 86 RUNTESTFLAGS override those set in the testcases; with this option, | |
| 87 the testcase will always win. Ditto for -mdejagnu-tune=. */ | |
| 88 #define DRIVER_SELF_SPECS \ | |
| 89 "%{mdejagnu-cpu=*: %<mcpu=* -mcpu=%*}", \ | |
| 90 "%{mdejagnu-tune=*: %<mtune=* -mtune=%*}", \ | |
| 91 "%{mdejagnu-*: %<mdejagnu-*}", \ | |
| 92 SUBTARGET_DRIVER_SELF_SPECS | |
| 93 | |
| 94 #if CHECKING_P | |
| 95 #define ASM_OPT_ANY "" | |
| 96 #else | |
| 97 #define ASM_OPT_ANY " -many" | |
| 98 #endif | |
| 99 | |
|
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100 /* Common ASM definitions used by ASM_SPEC among the various targets for |
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101 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to |
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102 provide the default assembler options if the user uses -mcpu=native, so if |
| 131 | 103 you make changes here, make them also there. PR63177: Do not pass -mpower8 |
| 104 to the assembler if -mpower9-vector was also used. */ | |
| 0 | 105 #define ASM_CPU_SPEC \ |
| 145 | 106 "%{mcpu=native: %(asm_cpu_native); \ |
| 107 mcpu=power9: -mpower9; \ | |
| 108 mcpu=power8|mcpu=powerpc64le: %{mpower9-vector: -mpower9;: -mpower8}; \ | |
| 109 mcpu=power7: -mpower7; \ | |
| 110 mcpu=power6x: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \ | |
| 111 mcpu=power6: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \ | |
| 112 mcpu=power5+: -mpower5; \ | |
| 113 mcpu=power5: -mpower5; \ | |
| 114 mcpu=power4: -mpower4; \ | |
| 115 mcpu=power3: -mppc64; \ | |
| 116 mcpu=powerpc: -mppc; \ | |
| 117 mcpu=powerpc64: -mppc64; \ | |
| 118 mcpu=a2: -ma2; \ | |
| 119 mcpu=cell: -mcell; \ | |
| 120 mcpu=rs64: -mppc64; \ | |
| 121 mcpu=401: -mppc; \ | |
| 122 mcpu=403: -m403; \ | |
| 123 mcpu=405: -m405; \ | |
| 124 mcpu=405fp: -m405; \ | |
| 125 mcpu=440: -m440; \ | |
| 126 mcpu=440fp: -m440; \ | |
| 127 mcpu=464: -m440; \ | |
| 128 mcpu=464fp: -m440; \ | |
| 129 mcpu=476: -m476; \ | |
| 130 mcpu=476fp: -m476; \ | |
| 131 mcpu=505: -mppc; \ | |
| 132 mcpu=601: -m601; \ | |
| 133 mcpu=602: -mppc; \ | |
| 134 mcpu=603: -mppc; \ | |
| 135 mcpu=603e: -mppc; \ | |
| 136 mcpu=ec603e: -mppc; \ | |
| 137 mcpu=604: -mppc; \ | |
| 138 mcpu=604e: -mppc; \ | |
| 139 mcpu=620: -mppc64; \ | |
| 140 mcpu=630: -mppc64; \ | |
| 141 mcpu=740: -mppc; \ | |
| 142 mcpu=750: -mppc; \ | |
| 143 mcpu=G3: -mppc; \ | |
| 144 mcpu=7400: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ | |
| 145 mcpu=7450: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ | |
| 146 mcpu=G4: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ | |
| 147 mcpu=801: -mppc; \ | |
| 148 mcpu=821: -mppc; \ | |
| 149 mcpu=823: -mppc; \ | |
| 150 mcpu=860: -mppc; \ | |
| 151 mcpu=970: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \ | |
| 152 mcpu=G5: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \ | |
| 153 mcpu=8540: -me500; \ | |
| 154 mcpu=8548: -me500; \ | |
| 155 mcpu=e300c2: -me300; \ | |
| 156 mcpu=e300c3: -me300; \ | |
| 157 mcpu=e500mc: -me500mc; \ | |
| 158 mcpu=e500mc64: -me500mc64; \ | |
| 159 mcpu=e5500: -me5500; \ | |
| 160 mcpu=e6500: -me6500; \ | |
| 161 mcpu=titan: -mtitan; \ | |
| 162 mcpu=future: -mfuture; \ | |
| 163 !mcpu*: %{mpower9-vector: -mpower9; \ | |
| 164 mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \ | |
| 165 mvsx: -mpower7; \ | |
| 166 mpowerpc64: -mppc64;: %(asm_default)}; \ | |
| 167 :%eMissing -mcpu option in ASM_CPU_SPEC?\n} \ | |
| 168 %{mvsx: -mvsx -maltivec; maltivec: -maltivec}" \ | |
| 169 ASM_OPT_ANY | |
| 0 | 170 |
| 171 #define CPP_DEFAULT_SPEC "" | |
| 172 | |
| 173 #define ASM_DEFAULT_SPEC "" | |
| 145 | 174 #define ASM_DEFAULT_EXTRA "" |
| 0 | 175 |
| 176 /* This macro defines names of additional specifications to put in the specs | |
| 177 that can be used in various specifications like CC1_SPEC. Its definition | |
| 178 is an initializer with a subgrouping for each command option. | |
| 179 | |
| 180 Each subgrouping contains a string constant, that defines the | |
| 181 specification name, and a string constant that used by the GCC driver | |
| 182 program. | |
| 183 | |
| 184 Do not define this macro if it does not need to do anything. */ | |
| 185 | |
| 186 #define SUBTARGET_EXTRA_SPECS | |
| 187 | |
| 188 #define EXTRA_SPECS \ | |
| 189 { "cpp_default", CPP_DEFAULT_SPEC }, \ | |
| 190 { "asm_cpu", ASM_CPU_SPEC }, \ | |
|
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191 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ |
| 145 | 192 { "asm_default", ASM_DEFAULT_SPEC ASM_DEFAULT_EXTRA }, \ |
| 0 | 193 { "cc1_cpu", CC1_CPU_SPEC }, \ |
| 194 SUBTARGET_EXTRA_SPECS | |
| 195 | |
| 196 /* -mcpu=native handling only makes sense with compiler running on | |
| 197 an PowerPC chip. If changing this condition, also change | |
| 198 the condition in driver-rs6000.c. */ | |
| 199 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) | |
| 200 /* In driver-rs6000.c. */ | |
| 201 extern const char *host_detect_local_cpu (int argc, const char **argv); | |
| 202 #define EXTRA_SPEC_FUNCTIONS \ | |
| 203 { "local_cpu_detect", host_detect_local_cpu }, | |
| 204 #define HAVE_LOCAL_CPU_DETECT | |
|
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205 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" |
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206 |
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207 #else |
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208 #define ASM_CPU_NATIVE_SPEC "%(asm_default)" |
| 0 | 209 #endif |
| 210 | |
| 211 #ifndef CC1_CPU_SPEC | |
| 212 #ifdef HAVE_LOCAL_CPU_DETECT | |
| 213 #define CC1_CPU_SPEC \ | |
| 214 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ | |
| 215 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
| 216 #else | |
| 217 #define CC1_CPU_SPEC "" | |
| 218 #endif | |
| 219 #endif | |
| 220 | |
| 221 /* Architecture type. */ | |
| 222 | |
| 223 /* Define TARGET_MFCRF if the target assembler does not support the | |
| 224 optional field operand for mfcr. */ | |
| 225 | |
| 226 #ifndef HAVE_AS_MFCRF | |
| 227 #undef TARGET_MFCRF | |
| 228 #define TARGET_MFCRF 0 | |
| 229 #endif | |
| 230 | |
| 231 #ifndef TARGET_SECURE_PLT | |
| 232 #define TARGET_SECURE_PLT 0 | |
| 233 #endif | |
| 234 | |
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235 #ifndef TARGET_CMODEL |
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236 #define TARGET_CMODEL CMODEL_SMALL |
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237 #endif |
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238 |
| 0 | 239 #define TARGET_32BIT (! TARGET_64BIT) |
| 240 | |
| 241 #ifndef HAVE_AS_TLS | |
| 242 #define HAVE_AS_TLS 0 | |
| 243 #endif | |
| 244 | |
| 145 | 245 #ifndef HAVE_AS_PLTSEQ |
| 246 #define HAVE_AS_PLTSEQ 0 | |
| 247 #endif | |
| 248 | |
| 249 #ifndef TARGET_PLTSEQ | |
| 250 #define TARGET_PLTSEQ 0 | |
| 251 #endif | |
| 252 | |
| 111 | 253 #ifndef TARGET_LINK_STACK |
| 254 #define TARGET_LINK_STACK 0 | |
| 255 #endif | |
| 256 | |
| 257 #ifndef SET_TARGET_LINK_STACK | |
| 258 #define SET_TARGET_LINK_STACK(X) do { } while (0) | |
| 259 #endif | |
| 260 | |
| 261 #ifndef TARGET_FLOAT128_ENABLE_TYPE | |
| 262 #define TARGET_FLOAT128_ENABLE_TYPE 0 | |
| 263 #endif | |
| 264 | |
| 0 | 265 /* Return 1 for a symbol ref for a thread-local storage symbol. */ |
| 266 #define RS6000_SYMBOL_REF_TLS_P(RTX) \ | |
| 145 | 267 (SYMBOL_REF_P (RTX) && SYMBOL_REF_TLS_MODEL (RTX) != 0) |
| 0 | 268 |
| 269 #ifdef IN_LIBGCC2 | |
| 270 /* For libgcc2 we make sure this is a compile time constant */ | |
| 271 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) | |
| 272 #undef TARGET_POWERPC64 | |
| 273 #define TARGET_POWERPC64 1 | |
| 274 #else | |
| 275 #undef TARGET_POWERPC64 | |
| 276 #define TARGET_POWERPC64 0 | |
| 277 #endif | |
| 278 #else | |
| 279 /* The option machinery will define this. */ | |
| 280 #endif | |
| 281 | |
| 131 | 282 #define TARGET_DEFAULT (MASK_MULTIPLE) |
| 0 | 283 |
| 284 /* Define generic processor types based upon current deployment. */ | |
| 285 #define PROCESSOR_COMMON PROCESSOR_PPC601 | |
| 286 #define PROCESSOR_POWERPC PROCESSOR_PPC604 | |
| 287 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A | |
| 288 | |
| 289 /* Define the default processor. This is overridden by other tm.h files. */ | |
| 111 | 290 #define PROCESSOR_DEFAULT PROCESSOR_PPC603 |
| 0 | 291 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A |
| 292 | |
| 111 | 293 /* Specify the dialect of assembler to use. Only new mnemonics are supported |
| 294 starting with GCC 4.8, i.e. just one dialect, but for backwards | |
| 295 compatibility with older inline asm ASSEMBLER_DIALECT needs to be | |
| 296 defined. */ | |
| 297 #define ASSEMBLER_DIALECT 1 | |
| 0 | 298 |
| 299 /* Debug support */ | |
|
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300 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */ |
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301 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */ |
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302 #define MASK_DEBUG_REG 0x04 /* debug register handling */ |
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303 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ |
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304 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */ |
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305 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ |
| 111 | 306 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ |
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307 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ |
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308 | MASK_DEBUG_ARG \ |
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309 | MASK_DEBUG_REG \ |
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310 | MASK_DEBUG_ADDR \ |
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311 | MASK_DEBUG_COST \ |
| 111 | 312 | MASK_DEBUG_TARGET \ |
| 313 | MASK_DEBUG_BUILTIN) | |
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314 |
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315 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) |
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316 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) |
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317 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) |
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318 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) |
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319 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) |
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320 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) |
| 111 | 321 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) |
| 322 | |
| 323 /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM | |
| 324 long double format that uses a pair of doubles, or IEEE 128-bit floating | |
| 325 point. KFmode was added as a way to represent IEEE 128-bit floating point, | |
| 326 even if the default for long double is the IBM long double format. | |
| 327 Similarly IFmode is the IBM long double format even if the default is IEEE | |
| 328 128-bit. Don't allow IFmode if -msoft-float. */ | |
| 329 #define FLOAT128_IEEE_P(MODE) \ | |
| 131 | 330 ((TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ |
| 331 && ((MODE) == TFmode || (MODE) == TCmode)) \ | |
| 111 | 332 || ((MODE) == KFmode) || ((MODE) == KCmode)) |
| 333 | |
| 334 #define FLOAT128_IBM_P(MODE) \ | |
| 131 | 335 ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ |
| 336 && ((MODE) == TFmode || (MODE) == TCmode)) \ | |
| 111 | 337 || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode))) |
| 338 | |
| 339 /* Helper macros to say whether a 128-bit floating point type can go in a | |
| 340 single vector register, or whether it needs paired scalar values. */ | |
| 341 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)) | |
| 342 | |
| 343 #define FLOAT128_2REG_P(MODE) \ | |
| 344 (FLOAT128_IBM_P (MODE) \ | |
| 345 || ((MODE) == TDmode) \ | |
| 346 || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))) | |
| 347 | |
| 348 /* Return true for floating point that does not use a vector register. */ | |
| 349 #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \ | |
| 350 (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE)) | |
| 351 | |
| 352 /* Describe the vector unit used for arithmetic operations. */ | |
|
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353 extern enum rs6000_vector rs6000_vector_unit[]; |
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354 |
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355 #define VECTOR_UNIT_NONE_P(MODE) \ |
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356 (rs6000_vector_unit[(MODE)] == VECTOR_NONE) |
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357 |
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358 #define VECTOR_UNIT_VSX_P(MODE) \ |
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359 (rs6000_vector_unit[(MODE)] == VECTOR_VSX) |
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360 |
| 111 | 361 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \ |
| 362 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR) | |
| 363 | |
|
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364 #define VECTOR_UNIT_ALTIVEC_P(MODE) \ |
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365 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) |
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366 |
| 111 | 367 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \ |
| 368 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ | |
| 369 (int)VECTOR_VSX, \ | |
| 370 (int)VECTOR_P8_VECTOR)) | |
| 371 | |
| 372 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either | |
| 373 altivec (VMX) or VSX vector instructions. P8 vector support is upwards | |
| 374 compatible, so allow it as well, rather than changing all of the uses of the | |
| 375 macro. */ | |
|
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376 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ |
| 111 | 377 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ |
| 378 (int)VECTOR_ALTIVEC, \ | |
| 379 (int)VECTOR_P8_VECTOR)) | |
|
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380 |
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381 /* Describe whether to use VSX loads or Altivec loads. For now, just use the |
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382 same unit as the vector unit we are using, but we may want to migrate to |
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383 using VSX style loads even for types handled by altivec. */ |
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384 extern enum rs6000_vector rs6000_vector_mem[]; |
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385 |
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386 #define VECTOR_MEM_NONE_P(MODE) \ |
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387 (rs6000_vector_mem[(MODE)] == VECTOR_NONE) |
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388 |
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389 #define VECTOR_MEM_VSX_P(MODE) \ |
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390 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) |
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391 |
| 111 | 392 #define VECTOR_MEM_P8_VECTOR_P(MODE) \ |
| 393 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) | |
| 394 | |
|
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395 #define VECTOR_MEM_ALTIVEC_P(MODE) \ |
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396 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) |
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397 |
| 111 | 398 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \ |
| 399 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ | |
| 400 (int)VECTOR_VSX, \ | |
| 401 (int)VECTOR_P8_VECTOR)) | |
| 402 | |
|
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403 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ |
| 111 | 404 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ |
| 405 (int)VECTOR_ALTIVEC, \ | |
| 406 (int)VECTOR_P8_VECTOR)) | |
|
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407 |
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408 /* Return the alignment of a given vector type, which is set based on the |
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409 vector unit use. VSX for instance can load 32 or 64 bit aligned words |
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410 without problems, while Altivec requires 128-bit aligned vectors. */ |
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411 extern int rs6000_vector_align[]; |
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412 |
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413 #define VECTOR_ALIGN(MODE) \ |
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414 ((rs6000_vector_align[(MODE)] != 0) \ |
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415 ? rs6000_vector_align[(MODE)] \ |
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416 : (int)GET_MODE_BITSIZE ((MODE))) |
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417 |
| 111 | 418 /* Element number of the 64-bit value in a 128-bit vector that can be accessed |
| 419 with scalar instructions. */ | |
| 420 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1) | |
| 421 | |
| 422 /* Element number of the 64-bit value in a 128-bit vector that can be accessed | |
| 423 with the ISA 3.0 MFVSRLD instructions. */ | |
| 424 #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0) | |
| 425 | |
| 0 | 426 /* Alignment options for fields in structures for sub-targets following |
| 427 AIX-like ABI. | |
| 428 ALIGN_POWER word-aligns FP doubles (default AIX ABI). | |
| 429 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). | |
| 430 | |
| 431 Override the macro definitions when compiling libobjc to avoid undefined | |
| 432 reference to rs6000_alignment_flags due to library's use of GCC alignment | |
| 433 macros which use the macros below. */ | |
| 434 | |
| 435 #ifndef IN_TARGET_LIBS | |
| 436 #define MASK_ALIGN_POWER 0x00000000 | |
| 437 #define MASK_ALIGN_NATURAL 0x00000001 | |
| 438 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) | |
| 439 #else | |
| 440 #define TARGET_ALIGN_NATURAL 0 | |
| 441 #endif | |
| 442 | |
| 131 | 443 /* We use values 126..128 to pick the appropriate long double type (IFmode, |
| 444 KFmode, TFmode). */ | |
| 445 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64) | |
| 0 | 446 #define TARGET_IEEEQUAD rs6000_ieeequad |
| 447 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi | |
|
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448 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) |
| 0 | 449 |
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450 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. |
| 131 | 451 Enable 32-bit fcfid's on any of the switches for newer ISA machines. */ |
| 111 | 452 #define TARGET_FCFID (TARGET_POWERPC64 \ |
| 453 || TARGET_PPC_GPOPT /* 970/power4 */ \ | |
| 454 || TARGET_POPCNTB /* ISA 2.02 */ \ | |
| 455 || TARGET_CMPB /* ISA 2.05 */ \ | |
| 131 | 456 || TARGET_POPCNTD) /* ISA 2.06 */ |
|
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457 |
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458 #define TARGET_FCTIDZ TARGET_FCFID |
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459 #define TARGET_STFIWX TARGET_PPC_GFXOPT |
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460 #define TARGET_LFIWAX TARGET_CMPB |
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461 #define TARGET_LFIWZX TARGET_POPCNTD |
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462 #define TARGET_FCFIDS TARGET_POPCNTD |
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463 #define TARGET_FCFIDU TARGET_POPCNTD |
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464 #define TARGET_FCFIDUS TARGET_POPCNTD |
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465 #define TARGET_FCTIDUZ TARGET_POPCNTD |
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466 #define TARGET_FCTIWUZ TARGET_POPCNTD |
| 111 | 467 #define TARGET_CTZ TARGET_MODULO |
| 468 #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64) | |
| 145 | 469 #define TARGET_MADDLD TARGET_MODULO |
| 111 | 470 |
| 471 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) | |
| 472 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) | |
| 473 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64) | |
| 474 #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ | |
| 475 && TARGET_POWERPC64) | |
| 476 #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ | |
| 477 && TARGET_POWERPC64) | |
| 478 | |
| 479 /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */ | |
| 480 #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT | |
| 481 #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT) | |
| 482 | |
| 483 /* This wants to be set for p8 and newer. On p7, overlapping unaligned | |
| 484 loads are slow. */ | |
| 485 #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX | |
| 486 | |
| 487 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present | |
| 488 in power7, so conditionalize them on p8 features. TImode syncs need quad | |
| 489 memory support. */ | |
| 490 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \ | |
| 491 || TARGET_QUAD_MEMORY_ATOMIC \ | |
| 492 || TARGET_DIRECT_MOVE) | |
| 493 | |
| 494 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC | |
| 495 | |
| 496 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need | |
| 497 to allocate the SDmode stack slot to get the value into the proper location | |
| 498 in the register. */ | |
| 499 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP) | |
| 500 | |
| 501 /* ISA 3.0 has new min/max functions that don't need fast math that are being | |
| 502 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct | |
| 503 answers if the arguments are not in the normal range. */ | |
| 131 | 504 #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ |
| 505 && (TARGET_P9_MINMAX || !flag_trapping_math)) | |
| 111 | 506 |
| 507 /* In switching from using target_flags to using rs6000_isa_flags, the options | |
| 508 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map | |
| 509 OPTION_MASK_<xxx> back into MASK_<xxx>. */ | |
| 510 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC | |
| 511 #define MASK_CMPB OPTION_MASK_CMPB | |
| 512 #define MASK_CRYPTO OPTION_MASK_CRYPTO | |
| 513 #define MASK_DFP OPTION_MASK_DFP | |
| 514 #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE | |
| 515 #define MASK_DLMZB OPTION_MASK_DLMZB | |
| 516 #define MASK_EABI OPTION_MASK_EABI | |
| 517 #define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD | |
| 518 #define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW | |
| 519 #define MASK_FPRND OPTION_MASK_FPRND | |
| 520 #define MASK_P8_FUSION OPTION_MASK_P8_FUSION | |
| 521 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT | |
| 522 #define MASK_HTM OPTION_MASK_HTM | |
| 523 #define MASK_ISEL OPTION_MASK_ISEL | |
| 524 #define MASK_MFCRF OPTION_MASK_MFCRF | |
| 525 #define MASK_MULHW OPTION_MASK_MULHW | |
| 526 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE | |
| 527 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE | |
| 528 #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR | |
| 529 #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR | |
| 530 #define MASK_P9_MISC OPTION_MASK_P9_MISC | |
| 531 #define MASK_POPCNTB OPTION_MASK_POPCNTB | |
| 532 #define MASK_POPCNTD OPTION_MASK_POPCNTD | |
| 533 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT | |
| 534 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT | |
| 535 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION | |
| 536 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT | |
| 537 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN | |
| 538 #define MASK_UPDATE OPTION_MASK_UPDATE | |
| 539 #define MASK_VSX OPTION_MASK_VSX | |
| 145 | 540 #define MASK_FUTURE OPTION_MASK_FUTURE |
| 111 | 541 |
| 542 #ifndef IN_LIBGCC2 | |
| 543 #define MASK_POWERPC64 OPTION_MASK_POWERPC64 | |
| 544 #endif | |
| 545 | |
| 546 #ifdef TARGET_64BIT | |
| 547 #define MASK_64BIT OPTION_MASK_64BIT | |
| 548 #endif | |
| 549 | |
| 550 #ifdef TARGET_LITTLE_ENDIAN | |
| 551 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN | |
| 552 #endif | |
| 553 | |
| 554 #ifdef TARGET_REGNAMES | |
| 555 #define MASK_REGNAMES OPTION_MASK_REGNAMES | |
| 556 #endif | |
| 557 | |
| 558 #ifdef TARGET_PROTOTYPE | |
| 559 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE | |
| 560 #endif | |
| 561 | |
| 562 #ifdef TARGET_MODULO | |
| 563 #define RS6000_BTM_MODULO OPTION_MASK_MODULO | |
| 564 #endif | |
| 565 | |
| 566 | |
| 567 /* For power systems, we want to enable Altivec and VSX builtins even if the | |
| 568 user did not use -maltivec or -mvsx to allow the builtins to be used inside | |
| 569 of #pragma GCC target or the target attribute to change the code level for a | |
| 131 | 570 given system. */ |
| 111 | 571 |
| 131 | 572 #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \ |
| 573 || TARGET_PPC_GPOPT /* 970/power4 */ \ | |
| 574 || TARGET_POPCNTB /* ISA 2.02 */ \ | |
| 575 || TARGET_CMPB /* ISA 2.05 */ \ | |
| 576 || TARGET_POPCNTD /* ISA 2.06 */ \ | |
| 577 || TARGET_ALTIVEC \ | |
| 578 || TARGET_VSX \ | |
| 579 || TARGET_HARD_FLOAT) | |
| 111 | 580 |
| 581 /* E500 cores only support plain "sync", not lwsync. */ | |
| 582 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ | |
| 583 || rs6000_cpu == PROCESSOR_PPC8548) | |
| 584 | |
| 585 | |
| 131 | 586 /* Which machine supports the various reciprocal estimate instructions. */ |
| 587 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT) | |
| 111 | 588 |
| 131 | 589 #define TARGET_FRE (TARGET_HARD_FLOAT \ |
|
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590 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) |
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591 |
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592 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ |
| 131 | 593 && TARGET_PPC_GFXOPT) |
|
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594 |
| 131 | 595 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \ |
| 596 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) | |
| 111 | 597 |
| 598 /* Macro to say whether we can do optimizations where we need to do parts of | |
| 599 the calculation in 64-bit GPRs and then is transfered to the vector | |
| 131 | 600 registers. */ |
| 111 | 601 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \ |
| 602 && TARGET_P8_VECTOR \ | |
| 131 | 603 && TARGET_POWERPC64) |
| 111 | 604 |
|
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605 /* Whether the various reciprocal divide/square root estimate instructions |
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606 exist, and whether we should automatically generate code for the instruction |
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607 by default. */ |
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608 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ |
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609 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */ |
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610 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */ |
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611 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */ |
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612 |
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613 extern unsigned char rs6000_recip_bits[]; |
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614 |
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615 #define RS6000_RECIP_HAVE_RE_P(MODE) \ |
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616 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE) |
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617 |
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618 #define RS6000_RECIP_AUTO_RE_P(MODE) \ |
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619 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE) |
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620 |
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621 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \ |
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622 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE) |
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623 |
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624 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ |
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625 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) |
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626 |
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627 /* The default CPU for TARGET_OPTION_OVERRIDE. */ |
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628 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT |
| 0 | 629 |
| 630 /* Target pragma. */ | |
| 631 #define REGISTER_TARGET_PRAGMAS() do { \ | |
| 632 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ | |
|
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633 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ |
| 0 | 634 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ |
| 111 | 635 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \ |
| 0 | 636 } while (0) |
| 637 | |
| 638 /* Target #defines. */ | |
| 639 #define TARGET_CPU_CPP_BUILTINS() \ | |
| 640 rs6000_cpu_cpp_builtins (pfile) | |
| 641 | |
| 145 | 642 /* Target CPU versions for D. */ |
| 643 #define TARGET_D_CPU_VERSIONS rs6000_d_target_versions | |
| 644 | |
| 0 | 645 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order |
| 646 we're compiling for. Some configurations may need to override it. */ | |
| 647 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ | |
| 648 do \ | |
| 649 { \ | |
| 650 if (BYTES_BIG_ENDIAN) \ | |
| 651 { \ | |
| 652 builtin_define ("__BIG_ENDIAN__"); \ | |
| 653 builtin_define ("_BIG_ENDIAN"); \ | |
| 654 builtin_assert ("machine=bigendian"); \ | |
| 655 } \ | |
| 656 else \ | |
| 657 { \ | |
| 658 builtin_define ("__LITTLE_ENDIAN__"); \ | |
| 659 builtin_define ("_LITTLE_ENDIAN"); \ | |
| 660 builtin_assert ("machine=littleendian"); \ | |
| 661 } \ | |
| 662 } \ | |
| 663 while (0) | |
| 664 | |
| 665 /* Target machine storage layout. */ | |
| 666 | |
| 667 /* Define this macro if it is advisable to hold scalars in registers | |
| 668 in a wider mode than that declared by the program. In such cases, | |
| 669 the value is constrained to be within the bounds of the declared | |
| 670 type, but kept valid in the wider mode. The signedness of the | |
| 671 extension may differ from that of the type. */ | |
| 672 | |
| 673 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ | |
| 674 if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
| 111 | 675 && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \ |
| 0 | 676 (MODE) = TARGET_32BIT ? SImode : DImode; |
| 677 | |
| 678 /* Define this if most significant bit is lowest numbered | |
| 679 in instructions that operate on numbered bit-fields. */ | |
| 680 /* That is true on RS/6000. */ | |
| 681 #define BITS_BIG_ENDIAN 1 | |
| 682 | |
| 683 /* Define this if most significant byte of a word is the lowest numbered. */ | |
| 684 /* That is true on RS/6000. */ | |
| 685 #define BYTES_BIG_ENDIAN 1 | |
| 686 | |
| 687 /* Define this if most significant word of a multiword number is lowest | |
| 688 numbered. | |
| 689 | |
| 690 For RS/6000 we can decide arbitrarily since there are no machine | |
| 691 instructions for them. Might as well be consistent with bits and bytes. */ | |
| 692 #define WORDS_BIG_ENDIAN 1 | |
| 693 | |
| 111 | 694 /* This says that for the IBM long double the larger magnitude double |
| 695 comes first. It's really a two element double array, and arrays | |
| 696 don't index differently between little- and big-endian. */ | |
| 697 #define LONG_DOUBLE_LARGE_FIRST 1 | |
| 698 | |
| 0 | 699 #define MAX_BITS_PER_WORD 64 |
| 700 | |
| 701 /* Width of a word, in units (bytes). */ | |
| 702 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) | |
| 703 #ifdef IN_LIBGCC2 | |
| 704 #define MIN_UNITS_PER_WORD UNITS_PER_WORD | |
| 705 #else | |
| 706 #define MIN_UNITS_PER_WORD 4 | |
| 707 #endif | |
| 708 #define UNITS_PER_FP_WORD 8 | |
| 709 #define UNITS_PER_ALTIVEC_WORD 16 | |
|
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710 #define UNITS_PER_VSX_WORD 16 |
| 0 | 711 |
| 712 /* Type used for ptrdiff_t, as a string used in a declaration. */ | |
| 713 #define PTRDIFF_TYPE "int" | |
| 714 | |
| 715 /* Type used for size_t, as a string used in a declaration. */ | |
| 716 #define SIZE_TYPE "long unsigned int" | |
| 717 | |
| 718 /* Type used for wchar_t, as a string used in a declaration. */ | |
| 719 #define WCHAR_TYPE "short unsigned int" | |
| 720 | |
| 721 /* Width of wchar_t in bits. */ | |
| 722 #define WCHAR_TYPE_SIZE 16 | |
| 723 | |
| 724 /* A C expression for the size in bits of the type `short' on the | |
| 725 target machine. If you don't define this, the default is half a | |
| 726 word. (If this would be less than one storage unit, it is | |
| 727 rounded up to one unit.) */ | |
| 728 #define SHORT_TYPE_SIZE 16 | |
| 729 | |
| 730 /* A C expression for the size in bits of the type `int' on the | |
| 731 target machine. If you don't define this, the default is one | |
| 732 word. */ | |
| 733 #define INT_TYPE_SIZE 32 | |
| 734 | |
| 735 /* A C expression for the size in bits of the type `long' on the | |
| 736 target machine. If you don't define this, the default is one | |
| 737 word. */ | |
| 738 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) | |
| 739 | |
| 740 /* A C expression for the size in bits of the type `long long' on the | |
| 741 target machine. If you don't define this, the default is two | |
| 742 words. */ | |
| 743 #define LONG_LONG_TYPE_SIZE 64 | |
| 744 | |
| 745 /* A C expression for the size in bits of the type `float' on the | |
| 746 target machine. If you don't define this, the default is one | |
| 747 word. */ | |
| 748 #define FLOAT_TYPE_SIZE 32 | |
| 749 | |
| 750 /* A C expression for the size in bits of the type `double' on the | |
| 751 target machine. If you don't define this, the default is two | |
| 752 words. */ | |
| 753 #define DOUBLE_TYPE_SIZE 64 | |
| 754 | |
| 131 | 755 /* A C expression for the size in bits of the type `long double' on the target |
| 756 machine. If you don't define this, the default is two words. */ | |
| 0 | 757 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size |
| 758 | |
| 759 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ | |
| 760 #define WIDEST_HARDWARE_FP_SIZE 64 | |
| 761 | |
| 762 /* Width in bits of a pointer. | |
| 763 See also the macro `Pmode' defined below. */ | |
|
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764 extern unsigned rs6000_pointer_size; |
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765 #define POINTER_SIZE rs6000_pointer_size |
| 0 | 766 |
| 767 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
| 768 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) | |
| 769 | |
| 770 /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
|
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771 #define STACK_BOUNDARY \ |
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772 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ |
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773 ? 64 : 128) |
| 0 | 774 |
| 775 /* Allocation boundary (in *bits*) for the code of a function. */ | |
| 776 #define FUNCTION_BOUNDARY 32 | |
| 777 | |
| 778 /* No data type wants to be aligned rounder than this. */ | |
| 779 #define BIGGEST_ALIGNMENT 128 | |
| 780 | |
| 781 /* Alignment of field after `int : 0' in a structure. */ | |
| 782 #define EMPTY_FIELD_BOUNDARY 32 | |
| 783 | |
| 784 /* Every structure's size must be a multiple of this. */ | |
| 785 #define STRUCTURE_SIZE_BOUNDARY 8 | |
| 786 | |
| 787 /* A bit-field declared as `int' forces `int' alignment for the struct. */ | |
| 788 #define PCC_BITFIELD_TYPE_MATTERS 1 | |
| 789 | |
| 111 | 790 enum data_align { align_abi, align_opt, align_both }; |
| 791 | |
| 792 /* A C expression to compute the alignment for a variables in the | |
| 793 local store. TYPE is the data type, and ALIGN is the alignment | |
| 794 that the object would ordinarily have. */ | |
| 795 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
| 796 rs6000_data_alignment (TYPE, ALIGN, align_both) | |
| 797 | |
| 798 /* Make arrays of chars word-aligned for the same reasons. */ | |
| 799 #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
| 800 rs6000_data_alignment (TYPE, ALIGN, align_opt) | |
| 801 | |
| 802 /* Align vectors to 128 bits. */ | |
| 803 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ | |
| 804 rs6000_data_alignment (TYPE, ALIGN, align_abi) | |
| 0 | 805 |
| 806 /* Nonzero if move instructions will actually fail to work | |
| 807 when given unaligned data. */ | |
| 808 #define STRICT_ALIGNMENT 0 | |
| 809 | |
| 810 /* Standard register usage. */ | |
| 811 | |
| 812 /* Number of actual hardware registers. | |
| 813 The hardware registers are assigned numbers for the compiler | |
| 814 from 0 to just below FIRST_PSEUDO_REGISTER. | |
| 815 All registers that the compiler knows about must be given numbers, | |
| 816 even those that are not normally considered general registers. | |
| 817 | |
| 818 RS/6000 has 32 fixed-point registers, 32 floating-point registers, | |
| 111 | 819 a count register, a link register, and 8 condition register fields, |
| 820 which we view here as separate registers. AltiVec adds 32 vector | |
| 821 registers and a VRsave register. | |
| 0 | 822 |
| 823 In addition, the difference between the frame and argument pointers is | |
| 824 a function of the number of registers saved, so we need to have a | |
| 825 register for AP that will later be eliminated in favor of SP or FP. | |
| 826 This is a normal register, but it is fixed. | |
| 827 | |
| 828 We also create a pseudo register for float/int conversions, that will | |
| 829 really represent the memory location used. It is represented here as | |
| 830 a register, in order to work around problems in allocating stack storage | |
| 831 in inline functions. | |
| 832 | |
| 833 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame | |
| 145 | 834 pointer, which is eventually eliminated in favor of SP or FP. */ |
| 835 | |
| 836 #define FIRST_PSEUDO_REGISTER 111 | |
| 0 | 837 |
| 838 /* Use standard DWARF numbering for DWARF debugging information. */ | |
| 111 | 839 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0) |
| 0 | 840 |
| 841 /* Use gcc hard register numbering for eh_frame. */ | |
| 842 #define DWARF_FRAME_REGNUM(REGNO) (REGNO) | |
| 843 | |
| 844 /* Map register numbers held in the call frame info that gcc has | |
| 845 collected using DWARF_FRAME_REGNUM to those that should be output in | |
| 111 | 846 .debug_frame and .eh_frame. */ |
| 847 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ | |
| 145 | 848 rs6000_dbx_register_number ((REGNO), (FOR_EH) ? 2 : 1) |
| 0 | 849 |
| 850 /* 1 for registers that have pervasive standard uses | |
| 851 and are not available for the register allocator. | |
| 852 | |
| 853 On RS/6000, r1 is used for the stack. On Darwin, r2 is available | |
| 854 as a local register; for all other OS's r2 is the TOC pointer. | |
| 855 | |
| 856 On System V implementations, r13 is fixed and not available for use. */ | |
| 857 | |
| 858 #define FIXED_REGISTERS \ | |
| 145 | 859 {/* GPRs */ \ |
| 860 0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ | |
| 0 | 861 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
| 145 | 862 /* FPRs */ \ |
| 0 | 863 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
| 864 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 145 | 865 /* VRs */ \ |
| 0 | 866 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
| 867 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 145 | 868 /* lr ctr ca ap */ \ |
| 869 0, 0, 1, 1, \ | |
| 870 /* cr0..cr7 */ \ | |
| 871 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 872 /* vrsave vscr sfp */ \ | |
| 873 1, 1, 1 \ | |
| 0 | 874 } |
| 875 | |
| 876 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that | |
| 877 the entire set of `FIXED_REGISTERS' be included. | |
| 878 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). | |
| 879 This macro is optional. If not specified, it defaults to the value | |
| 880 of `CALL_USED_REGISTERS'. */ | |
| 881 | |
| 882 #define CALL_REALLY_USED_REGISTERS \ | |
| 145 | 883 {/* GPRs */ \ |
| 884 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ | |
| 0 | 885 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
| 145 | 886 /* FPRs */ \ |
| 0 | 887 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ |
| 888 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 145 | 889 /* VRs */ \ |
| 0 | 890 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
| 891 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 145 | 892 /* lr ctr ca ap */ \ |
| 893 1, 1, 1, 1, \ | |
| 894 /* cr0..cr7 */ \ | |
| 895 1, 1, 0, 0, 0, 1, 1, 1, \ | |
| 896 /* vrsave vscr sfp */ \ | |
| 897 0, 0, 0 \ | |
| 0 | 898 } |
| 899 | |
| 900 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) | |
| 901 | |
| 902 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) | |
| 111 | 903 #define FIRST_SAVED_FP_REGNO (14+32) |
| 904 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13) | |
| 0 | 905 |
| 906 /* List the order in which to allocate registers. Each register must be | |
| 907 listed once, even those in FIXED_REGISTERS. | |
| 908 | |
| 909 We allocate in the following order: | |
| 910 fp0 (not saved or used for anything) | |
| 911 fp13 - fp2 (not saved; incoming fp arg registers) | |
| 912 fp1 (not saved; return value) | |
| 913 fp31 - fp14 (saved; order given to save least number) | |
| 111 | 914 cr7, cr5 (not saved or special) |
| 915 cr6 (not saved, but used for vector operations) | |
| 0 | 916 cr1 (not saved, but used for FP operations) |
| 917 cr0 (not saved, but used for arithmetic operations) | |
| 918 cr4, cr3, cr2 (saved) | |
| 111 | 919 r9 (not saved; best for TImode) |
| 920 r10, r8-r4 (not saved; highest first for less conflict with params) | |
| 921 r3 (not saved; return value register) | |
| 922 r11 (not saved; later alloc to help shrink-wrap) | |
| 0 | 923 r0 (not saved; cannot be base reg) |
| 924 r31 - r13 (saved; order given to save least number) | |
| 925 r12 (not saved; if used for DImode or DFmode would use r13) | |
| 926 ctr (not saved; when we have the choice ctr is better) | |
| 927 lr (saved) | |
| 111 | 928 r1, r2, ap, ca (fixed) |
| 0 | 929 v0 - v1 (not saved or used for anything) |
| 930 v13 - v3 (not saved; incoming vector arg registers) | |
| 931 v2 (not saved; incoming vector arg reg; return value) | |
| 932 v19 - v14 (not saved or used for anything) | |
| 933 v31 - v20 (saved; order given to save least number) | |
| 934 vrsave, vscr (fixed) | |
| 935 sfp (fixed) | |
| 936 */ | |
| 937 | |
| 938 #if FIXED_R2 == 1 | |
| 939 #define MAYBE_R2_AVAILABLE | |
| 940 #define MAYBE_R2_FIXED 2, | |
| 941 #else | |
| 942 #define MAYBE_R2_AVAILABLE 2, | |
| 943 #define MAYBE_R2_FIXED | |
| 944 #endif | |
| 945 | |
| 111 | 946 #if FIXED_R13 == 1 |
| 947 #define EARLY_R12 12, | |
| 948 #define LATE_R12 | |
| 949 #else | |
| 950 #define EARLY_R12 | |
| 951 #define LATE_R12 12, | |
| 952 #endif | |
| 953 | |
| 0 | 954 #define REG_ALLOC_ORDER \ |
| 955 {32, \ | |
| 111 | 956 /* move fr13 (ie 45) later, so if we need TFmode, it does */ \ |
| 957 /* not use fr14 which is a saved register. */ \ | |
| 958 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \ | |
| 0 | 959 33, \ |
| 960 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ | |
| 961 50, 49, 48, 47, 46, \ | |
| 145 | 962 100, 107, 105, 106, 101, 104, 103, 102, \ |
| 111 | 963 MAYBE_R2_AVAILABLE \ |
| 964 9, 10, 8, 7, 6, 5, 4, \ | |
| 965 3, EARLY_R12 11, 0, \ | |
| 0 | 966 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ |
| 111 | 967 18, 17, 16, 15, 14, 13, LATE_R12 \ |
| 145 | 968 97, 96, \ |
| 969 1, MAYBE_R2_FIXED 99, 98, \ | |
| 0 | 970 /* AltiVec registers. */ \ |
| 145 | 971 64, 65, \ |
| 972 77, 76, 75, 74, 73, 72, 71, 70, 69, 68, 67, \ | |
| 973 66, \ | |
| 974 83, 82, 81, 80, 79, 78, \ | |
| 975 95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84, \ | |
| 976 108, 109, \ | |
| 977 110 \ | |
| 0 | 978 } |
| 979 | |
| 980 /* True if register is floating-point. */ | |
| 981 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
| 982 | |
| 983 /* True if register is a condition register. */ | |
| 984 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) | |
| 985 | |
| 986 /* True if register is a condition register, but not cr0. */ | |
| 987 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) | |
| 988 | |
| 989 /* True if register is an integer register. */ | |
| 990 #define INT_REGNO_P(N) \ | |
| 991 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) | |
| 992 | |
|
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993 /* True if register is the CA register. */ |
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994 #define CA_REGNO_P(N) ((N) == CA_REGNO) |
| 0 | 995 |
| 996 /* True if register is an AltiVec register. */ | |
| 997 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) | |
| 998 | |
|
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999 /* True if register is a VSX register. */ |
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1000 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) |
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1001 |
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1002 /* Alternate name for any vector register supporting floating point, no matter |
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1003 which instruction set(s) are available. */ |
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1004 #define VFLOAT_REGNO_P(N) \ |
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1005 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) |
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1006 |
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1007 /* Alternate name for any vector register supporting integer, no matter which |
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1008 instruction set(s) are available. */ |
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1009 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) |
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1010 |
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1011 /* Alternate name for any vector register supporting logical operations, no |
| 111 | 1012 matter which instruction set(s) are available. Allow GPRs as well as the |
| 1013 vector registers. */ | |
| 1014 #define VLOGICAL_REGNO_P(N) \ | |
| 1015 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \ | |
| 1016 || (TARGET_VSX && FP_REGNO_P (N))) \ | |
|
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1017 |
|
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1018 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate |
| 111 | 1019 enough space to account for vectors in FP regs. However, TFmode/TDmode |
| 1020 should not use VSX instructions to do a caller save. */ | |
| 1021 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ | |
| 1022 ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \ | |
| 1023 ? (MODE) \ | |
| 1024 : TARGET_VSX \ | |
| 1025 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ | |
| 1026 && FP_REGNO_P (REGNO) \ | |
| 1027 ? V2DFmode \ | |
| 1028 : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \ | |
| 1029 ? DFmode \ | |
| 1030 : (MODE) == TDmode && FP_REGNO_P (REGNO) \ | |
| 1031 ? DImode \ | |
| 145 | 1032 : choose_hard_reg_mode ((REGNO), (NREGS), NULL)) |
|
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1033 |
|
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1034 #define VSX_VECTOR_MODE(MODE) \ |
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1035 ((MODE) == V4SFmode \ |
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1036 || (MODE) == V2DFmode) \ |
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1037 |
| 111 | 1038 /* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not |
| 1039 really a vector, but we want to treat it as a vector for moves, and | |
| 1040 such. */ | |
| 1041 | |
| 1042 #define ALTIVEC_VECTOR_MODE(MODE) \ | |
| 1043 ((MODE) == V16QImode \ | |
| 1044 || (MODE) == V8HImode \ | |
| 1045 || (MODE) == V4SFmode \ | |
| 1046 || (MODE) == V4SImode \ | |
| 1047 || FLOAT128_VECTOR_P (MODE)) | |
| 1048 | |
| 1049 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ | |
| 1050 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ | |
| 1051 || (MODE) == V2DImode || (MODE) == V1TImode) | |
| 0 | 1052 |
| 1053 /* Post-reload, we can't use any new AltiVec registers, as we already | |
| 1054 emitted the vrsave mask. */ | |
| 1055 | |
| 1056 #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
| 1057 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) | |
| 1058 | |
| 1059 /* Specify the cost of a branch insn; roughly the number of extra insns that | |
| 1060 should be added to avoid a branch. | |
| 1061 | |
| 1062 Set this to 3 on the RS/6000 since that is roughly the average cost of an | |
| 1063 unscheduled conditional branch. */ | |
| 1064 | |
| 1065 #define BRANCH_COST(speed_p, predictable_p) 3 | |
| 1066 | |
| 1067 /* Override BRANCH_COST heuristic which empirically produces worse | |
| 1068 performance for removing short circuiting from the logical ops. */ | |
| 1069 | |
| 1070 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 | |
| 1071 | |
| 1072 /* Specify the registers used for certain standard purposes. | |
| 1073 The values of these macros are register numbers. */ | |
| 1074 | |
| 1075 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ | |
| 1076 /* #define PC_REGNUM */ | |
| 1077 | |
| 1078 /* Register to use for pushing function arguments. */ | |
| 1079 #define STACK_POINTER_REGNUM 1 | |
| 1080 | |
| 1081 /* Base register for access to local variables of the function. */ | |
| 1082 #define HARD_FRAME_POINTER_REGNUM 31 | |
| 1083 | |
| 1084 /* Base register for access to local variables of the function. */ | |
| 145 | 1085 #define FRAME_POINTER_REGNUM 110 |
| 0 | 1086 |
| 1087 /* Base register for access to arguments of the function. */ | |
| 145 | 1088 #define ARG_POINTER_REGNUM 99 |
| 0 | 1089 |
| 1090 /* Place to put static chain when calling a function that requires it. */ | |
| 1091 #define STATIC_CHAIN_REGNUM 11 | |
| 1092 | |
| 111 | 1093 /* Base register for access to thread local storage variables. */ |
| 1094 #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2) | |
| 1095 | |
| 0 | 1096 |
| 1097 /* Define the classes of registers for register constraints in the | |
| 1098 machine description. Also define ranges of constants. | |
| 1099 | |
| 1100 One of the classes must always be named ALL_REGS and include all hard regs. | |
| 1101 If there is more than one class, another class must be named NO_REGS | |
| 1102 and contain no registers. | |
| 1103 | |
| 1104 The name GENERAL_REGS must be the name of a class (or an alias for | |
| 1105 another name such as ALL_REGS). This is the class of registers | |
| 1106 that is allowed by "g" or "r" in a register constraint. | |
| 1107 Also, registers outside this class are allocated only when | |
| 1108 instructions express preferences for them. | |
| 1109 | |
| 1110 The classes must be numbered in nondecreasing order; that is, | |
| 1111 a larger-numbered class must never be contained completely | |
| 1112 in a smaller-numbered class. | |
| 1113 | |
| 1114 For any two classes, it is very desirable that there be another | |
| 1115 class that represents their union. */ | |
| 1116 | |
|
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1117 /* The RS/6000 has three types of registers, fixed-point, floating-point, and |
| 111 | 1118 condition registers, plus three special registers, CTR, and the link |
|
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1119 register. AltiVec adds a vector register class. VSX registers overlap the |
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1120 FPR registers and the Altivec registers. |
| 0 | 1121 |
| 1122 However, r0 is special in that it cannot be used as a base register. | |
| 1123 So make a class for registers valid as base registers. | |
| 1124 | |
| 1125 Also, cr0 is the only condition code register that can be used in | |
| 1126 arithmetic insns, so make a separate class for it. */ | |
| 1127 | |
| 1128 enum reg_class | |
| 1129 { | |
| 1130 NO_REGS, | |
| 1131 BASE_REGS, | |
| 1132 GENERAL_REGS, | |
| 1133 FLOAT_REGS, | |
| 1134 ALTIVEC_REGS, | |
|
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1135 VSX_REGS, |
| 0 | 1136 VRSAVE_REGS, |
| 1137 VSCR_REGS, | |
| 145 | 1138 GEN_OR_FLOAT_REGS, |
| 1139 GEN_OR_VSX_REGS, | |
| 0 | 1140 LINK_REGS, |
| 1141 CTR_REGS, | |
| 1142 LINK_OR_CTR_REGS, | |
| 1143 SPECIAL_REGS, | |
| 1144 SPEC_OR_GEN_REGS, | |
| 1145 CR0_REGS, | |
| 1146 CR_REGS, | |
| 1147 NON_FLOAT_REGS, | |
|
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1148 CA_REGS, |
| 0 | 1149 ALL_REGS, |
| 1150 LIM_REG_CLASSES | |
| 1151 }; | |
| 1152 | |
| 1153 #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
| 1154 | |
| 1155 /* Give names of register classes as strings for dump file. */ | |
| 1156 | |
| 1157 #define REG_CLASS_NAMES \ | |
| 1158 { \ | |
| 1159 "NO_REGS", \ | |
| 1160 "BASE_REGS", \ | |
| 1161 "GENERAL_REGS", \ | |
| 1162 "FLOAT_REGS", \ | |
| 1163 "ALTIVEC_REGS", \ | |
|
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1164 "VSX_REGS", \ |
| 0 | 1165 "VRSAVE_REGS", \ |
| 1166 "VSCR_REGS", \ | |
| 145 | 1167 "GEN_OR_FLOAT_REGS", \ |
| 1168 "GEN_OR_VSX_REGS", \ | |
| 0 | 1169 "LINK_REGS", \ |
| 1170 "CTR_REGS", \ | |
| 1171 "LINK_OR_CTR_REGS", \ | |
| 1172 "SPECIAL_REGS", \ | |
| 1173 "SPEC_OR_GEN_REGS", \ | |
| 1174 "CR0_REGS", \ | |
| 1175 "CR_REGS", \ | |
| 1176 "NON_FLOAT_REGS", \ | |
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1177 "CA_REGS", \ |
| 0 | 1178 "ALL_REGS" \ |
| 1179 } | |
| 1180 | |
| 1181 /* Define which registers fit in which classes. | |
| 1182 This is an initializer for a vector of HARD_REG_SET | |
| 1183 of length N_REG_CLASSES. */ | |
| 1184 | |
| 111 | 1185 #define REG_CLASS_CONTENTS \ |
| 1186 { \ | |
| 1187 /* NO_REGS. */ \ | |
| 1188 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ | |
| 1189 /* BASE_REGS. */ \ | |
| 145 | 1190 { 0xfffffffe, 0x00000000, 0x00000000, 0x00004008 }, \ |
| 111 | 1191 /* GENERAL_REGS. */ \ |
| 145 | 1192 { 0xffffffff, 0x00000000, 0x00000000, 0x00004008 }, \ |
| 111 | 1193 /* FLOAT_REGS. */ \ |
| 1194 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \ | |
| 1195 /* ALTIVEC_REGS. */ \ | |
| 145 | 1196 { 0x00000000, 0x00000000, 0xffffffff, 0x00000000 }, \ |
| 111 | 1197 /* VSX_REGS. */ \ |
| 145 | 1198 { 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ |
| 111 | 1199 /* VRSAVE_REGS. */ \ |
| 145 | 1200 { 0x00000000, 0x00000000, 0x00000000, 0x00001000 }, \ |
| 111 | 1201 /* VSCR_REGS. */ \ |
| 145 | 1202 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \ |
| 1203 /* GEN_OR_FLOAT_REGS. */ \ | |
| 1204 { 0xffffffff, 0xffffffff, 0x00000000, 0x00004008 }, \ | |
| 1205 /* GEN_OR_VSX_REGS. */ \ | |
| 1206 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00004008 }, \ | |
| 111 | 1207 /* LINK_REGS. */ \ |
| 145 | 1208 { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, \ |
| 111 | 1209 /* CTR_REGS. */ \ |
| 145 | 1210 { 0x00000000, 0x00000000, 0x00000000, 0x00000002 }, \ |
| 111 | 1211 /* LINK_OR_CTR_REGS. */ \ |
| 145 | 1212 { 0x00000000, 0x00000000, 0x00000000, 0x00000003 }, \ |
| 111 | 1213 /* SPECIAL_REGS. */ \ |
| 145 | 1214 { 0x00000000, 0x00000000, 0x00000000, 0x00001003 }, \ |
| 111 | 1215 /* SPEC_OR_GEN_REGS. */ \ |
| 145 | 1216 { 0xffffffff, 0x00000000, 0x00000000, 0x0000500b }, \ |
| 111 | 1217 /* CR0_REGS. */ \ |
| 145 | 1218 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, \ |
| 111 | 1219 /* CR_REGS. */ \ |
| 145 | 1220 { 0x00000000, 0x00000000, 0x00000000, 0x00000ff0 }, \ |
| 111 | 1221 /* NON_FLOAT_REGS. */ \ |
| 145 | 1222 { 0xffffffff, 0x00000000, 0x00000000, 0x00004ffb }, \ |
| 111 | 1223 /* CA_REGS. */ \ |
| 145 | 1224 { 0x00000000, 0x00000000, 0x00000000, 0x00000004 }, \ |
| 111 | 1225 /* ALL_REGS. */ \ |
| 145 | 1226 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00007fff } \ |
| 0 | 1227 } |
| 1228 | |
| 1229 /* The same information, inverted: | |
| 1230 Return the class number of the smallest class containing | |
| 1231 reg number REGNO. This could be a conditional expression | |
| 1232 or could index an array. */ | |
| 1233 | |
|
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1234 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; |
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1235 |
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1236 #define REGNO_REG_CLASS(REGNO) \ |
| 111 | 1237 (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\ |
|
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1238 rs6000_regno_regclass[(REGNO)]) |
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1239 |
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1240 /* Register classes for various constraints that are based on the target |
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1241 switches. */ |
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1242 enum r6000_reg_class_enum { |
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1243 RS6000_CONSTRAINT_d, /* fpr registers for double values */ |
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1244 RS6000_CONSTRAINT_f, /* fpr registers for single values */ |
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1245 RS6000_CONSTRAINT_v, /* Altivec registers */ |
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1246 RS6000_CONSTRAINT_wa, /* Any VSX register */ |
| 111 | 1247 RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */ |
| 1248 RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ | |
| 1249 RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ | |
| 1250 RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */ | |
|
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1251 RS6000_CONSTRAINT_MAX |
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1252 }; |
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1253 |
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1254 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; |
| 0 | 1255 |
| 1256 /* The class value for index registers, and the one for base regs. */ | |
| 1257 #define INDEX_REG_CLASS GENERAL_REGS | |
| 1258 #define BASE_REG_CLASS BASE_REGS | |
| 1259 | |
|
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1260 /* Return whether a given register class can hold VSX objects. */ |
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1261 #define VSX_REG_CLASS_P(CLASS) \ |
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1262 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) |
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1263 |
| 111 | 1264 /* Return whether a given register class targets general purpose registers. */ |
| 1265 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS) | |
| 1266 | |
| 0 | 1267 /* Given an rtx X being reloaded into a reg required to be |
| 1268 in class CLASS, return the class of reg to actually use. | |
| 1269 In general this is just CLASS; but on some machines | |
| 1270 in some cases it is preferable to use a more restrictive class. | |
| 1271 | |
| 1272 On the RS/6000, we have to return NO_REGS when we want to reload a | |
| 1273 floating-point CONST_DOUBLE to force it to be copied to memory. | |
| 1274 | |
| 1275 We also don't want to reload integer values into floating-point | |
| 1276 registers if we can at all help it. In fact, this can | |
| 1277 cause reload to die, if it tries to generate a reload of CTR | |
| 1278 into a FP register and discovers it doesn't have the memory location | |
| 1279 required. | |
| 1280 | |
| 1281 ??? Would it be a good idea to have reload do the converse, that is | |
| 1282 try to reload floating modes into FP registers if possible? | |
| 1283 */ | |
| 1284 | |
| 1285 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ | |
|
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1286 rs6000_preferred_reload_class_ptr (X, CLASS) |
| 0 | 1287 |
| 1288 /* Return the register class of a scratch register needed to copy IN into | |
| 1289 or out of a register in CLASS in MODE. If it can be done directly, | |
| 1290 NO_REGS is returned. */ | |
| 1291 | |
| 1292 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ | |
|
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1293 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) |
| 0 | 1294 |
| 1295 /* Return the maximum number of consecutive registers | |
| 1296 needed to represent mode MODE in a register of class CLASS. | |
| 1297 | |
|
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1298 On RS/6000, this is the size of MODE in words, except in the FP regs, where |
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1299 a single reg is enough for two words, unless we have VSX, where the FP |
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1300 registers can hold 128 bits. */ |
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1301 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] |
| 0 | 1302 |
| 1303 /* Stack layout; function entry, exit and calling. */ | |
| 1304 | |
| 1305 /* Define this if pushing a word on the stack | |
| 1306 makes the stack pointer a smaller address. */ | |
| 111 | 1307 #define STACK_GROWS_DOWNWARD 1 |
| 0 | 1308 |
| 1309 /* Offsets recorded in opcodes are a multiple of this alignment factor. */ | |
| 1310 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) | |
| 1311 | |
| 1312 /* Define this to nonzero if the nominal address of the stack frame | |
| 1313 is at the high-address end of the local variables; | |
| 1314 that is, each additional local variable allocated | |
| 1315 goes at a more negative offset in the frame. | |
| 1316 | |
| 1317 On the RS/6000, we grow upwards, from the area after the outgoing | |
| 1318 arguments. */ | |
| 111 | 1319 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \ |
| 1320 || (flag_sanitize & SANITIZE_ADDRESS) != 0) | |
| 0 | 1321 |
| 1322 /* Size of the fixed area on the stack */ | |
| 1323 #define RS6000_SAVE_AREA \ | |
| 111 | 1324 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \ |
| 0 | 1325 << (TARGET_64BIT ? 1 : 0)) |
| 1326 | |
| 111 | 1327 /* Stack offset for toc save slot. */ |
| 1328 #define RS6000_TOC_SAVE_SLOT \ | |
| 1329 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0)) | |
| 0 | 1330 |
| 1331 /* Align an address */ | |
| 111 | 1332 #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a)) |
| 0 | 1333 |
| 1334 /* Offset within stack frame to start allocating local variables at. | |
| 1335 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
| 1336 first local allocated. Otherwise, it is the offset to the BEGINNING | |
| 1337 of the first local allocated. | |
| 1338 | |
| 1339 On the RS/6000, the frame pointer is the same as the stack pointer, | |
| 1340 except for dynamic allocations. So we start after the fixed area and | |
| 111 | 1341 outgoing parameter area. |
| 1342 | |
| 1343 If the function uses dynamic stack space (CALLS_ALLOCA is set), that | |
| 1344 space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the | |
| 1345 sizes of the fixed area and the parameter area must be a multiple of | |
| 1346 STACK_BOUNDARY. */ | |
| 1347 | |
| 1348 #define RS6000_STARTING_FRAME_OFFSET \ | |
| 1349 (cfun->calls_alloca \ | |
| 1350 ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \ | |
| 1351 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \ | |
|
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1352 : (RS6000_ALIGN (crtl->outgoing_args_size, \ |
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1353 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ |
| 0 | 1354 + RS6000_SAVE_AREA)) |
| 1355 | |
| 1356 /* Offset from the stack pointer register to an item dynamically | |
| 1357 allocated on the stack, e.g., by `alloca'. | |
| 1358 | |
| 1359 The default value for this macro is `STACK_POINTER_OFFSET' plus the | |
| 1360 length of the outgoing arguments. The default is correct for most | |
| 111 | 1361 machines. See `function.c' for details. |
| 1362 | |
| 1363 This value must be a multiple of STACK_BOUNDARY (hard coded in | |
| 1364 `emit-rtl.c'). */ | |
| 0 | 1365 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ |
| 131 | 1366 RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \ |
| 1367 + STACK_POINTER_OFFSET, \ | |
| 111 | 1368 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) |
| 0 | 1369 |
| 1370 /* If we generate an insn to push BYTES bytes, | |
| 1371 this says how many the stack pointer really advances by. | |
| 1372 On RS/6000, don't define this because there are no push insns. */ | |
| 1373 /* #define PUSH_ROUNDING(BYTES) */ | |
| 1374 | |
| 1375 /* Offset of first parameter from the argument pointer register value. | |
| 1376 On the RS/6000, we define the argument pointer to the start of the fixed | |
| 1377 area. */ | |
| 1378 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA | |
| 1379 | |
| 1380 /* Offset from the argument pointer register value to the top of | |
| 1381 stack. This is different from FIRST_PARM_OFFSET because of the | |
| 1382 register save area. */ | |
| 1383 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 | |
| 1384 | |
| 1385 /* Define this if stack space is still allocated for a parameter passed | |
| 1386 in a register. The value is the number of bytes allocated to this | |
| 1387 area. */ | |
| 111 | 1388 #define REG_PARM_STACK_SPACE(FNDECL) \ |
| 1389 rs6000_reg_parm_stack_space ((FNDECL), false) | |
| 1390 | |
| 1391 /* Define this macro if space guaranteed when compiling a function body | |
| 1392 is different to space required when making a call, a situation that | |
| 1393 can arise with K&R style function definitions. */ | |
| 1394 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \ | |
| 1395 rs6000_reg_parm_stack_space ((FNDECL), true) | |
| 0 | 1396 |
| 1397 /* Define this if the above stack space is to be considered part of the | |
| 1398 space allocated by the caller. */ | |
| 1399 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 | |
| 1400 | |
| 1401 /* This is the difference between the logical top of stack and the actual sp. | |
| 1402 | |
| 1403 For the RS/6000, sp points past the fixed area. */ | |
| 1404 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA | |
| 1405 | |
| 1406 /* Define this if the maximum size of all the outgoing args is to be | |
| 1407 accumulated and pushed during the prologue. The amount can be | |
| 1408 found in the variable crtl->outgoing_args_size. */ | |
| 1409 #define ACCUMULATE_OUTGOING_ARGS 1 | |
| 1410 | |
| 1411 /* Define how to find the value returned by a library function | |
| 1412 assuming the value has mode MODE. */ | |
| 1413 | |
| 1414 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) | |
| 1415 | |
| 1416 /* DRAFT_V4_STRUCT_RET defaults off. */ | |
| 1417 #define DRAFT_V4_STRUCT_RET 0 | |
| 1418 | |
| 1419 /* Let TARGET_RETURN_IN_MEMORY control what happens. */ | |
| 1420 #define DEFAULT_PCC_STRUCT_RETURN 0 | |
| 1421 | |
| 1422 /* Mode of stack savearea. | |
| 1423 FUNCTION is VOIDmode because calling convention maintains SP. | |
| 1424 BLOCK needs Pmode for SP. | |
| 1425 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ | |
| 1426 #define STACK_SAVEAREA_MODE(LEVEL) \ | |
| 1427 (LEVEL == SAVE_FUNCTION ? VOIDmode \ | |
| 111 | 1428 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode) |
| 0 | 1429 |
| 1430 /* Minimum and maximum general purpose registers used to hold arguments. */ | |
| 1431 #define GP_ARG_MIN_REG 3 | |
| 1432 #define GP_ARG_MAX_REG 10 | |
| 1433 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) | |
| 1434 | |
| 1435 /* Minimum and maximum floating point registers used to hold arguments. */ | |
| 1436 #define FP_ARG_MIN_REG 33 | |
| 1437 #define FP_ARG_AIX_MAX_REG 45 | |
| 1438 #define FP_ARG_V4_MAX_REG 40 | |
| 111 | 1439 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \ |
| 1440 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG) | |
| 0 | 1441 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) |
| 1442 | |
| 1443 /* Minimum and maximum AltiVec registers used to hold arguments. */ | |
| 1444 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) | |
| 1445 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) | |
| 1446 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) | |
| 1447 | |
| 111 | 1448 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */ |
| 1449 #define AGGR_ARG_NUM_REG 8 | |
| 1450 | |
| 0 | 1451 /* Return registers */ |
| 1452 #define GP_ARG_RETURN GP_ARG_MIN_REG | |
| 1453 #define FP_ARG_RETURN FP_ARG_MIN_REG | |
| 1454 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) | |
| 111 | 1455 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \ |
| 1456 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) | |
| 1457 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \ | |
| 1458 ? (ALTIVEC_ARG_RETURN \ | |
| 1459 + (TARGET_FLOAT128_TYPE ? 1 : 0)) \ | |
| 1460 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) | |
| 0 | 1461 |
| 1462 /* Flags for the call/call_value rtl operations set up by function_arg */ | |
| 1463 #define CALL_NORMAL 0x00000000 /* no special processing */ | |
| 1464 /* Bits in 0x00000001 are unused. */ | |
| 1465 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ | |
| 1466 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ | |
| 1467 #define CALL_LONG 0x00000008 /* always call indirect */ | |
| 1468 #define CALL_LIBCALL 0x00000010 /* libcall */ | |
| 1469 | |
| 145 | 1470 /* Identify PLT sequence for rs6000_pltseq_template. */ |
| 1471 enum rs6000_pltseq_enum { | |
| 1472 RS6000_PLTSEQ_TOCSAVE, | |
| 1473 RS6000_PLTSEQ_PLT16_HA, | |
| 1474 RS6000_PLTSEQ_PLT16_LO, | |
| 1475 RS6000_PLTSEQ_MTCTR, | |
| 1476 RS6000_PLTSEQ_PLT_PCREL34 | |
| 1477 }; | |
| 1478 | |
| 1479 #define IS_V4_FP_ARGS(OP) \ | |
| 1480 ((INTVAL (OP) & (CALL_V4_CLEAR_FP_ARGS | CALL_V4_SET_FP_ARGS)) != 0) | |
| 1481 | |
| 0 | 1482 /* We don't have prologue and epilogue functions to save/restore |
| 1483 everything for most ABIs. */ | |
| 1484 #define WORLD_SAVE_P(INFO) 0 | |
| 1485 | |
| 1486 /* 1 if N is a possible register number for a function value | |
| 1487 as seen by the caller. | |
| 1488 | |
| 1489 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ | |
| 1490 #define FUNCTION_VALUE_REGNO_P(N) \ | |
| 1491 ((N) == GP_ARG_RETURN \ | |
| 111 | 1492 || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \ |
| 1493 && TARGET_HARD_FLOAT) \ | |
| 1494 || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \ | |
| 1495 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) | |
| 0 | 1496 |
| 1497 /* 1 if N is a possible register number for function argument passing. | |
| 1498 On RS/6000, these are r3-r10 and fp1-fp13. | |
| 1499 On AltiVec, v2 - v13 are used for passing vectors. */ | |
| 1500 #define FUNCTION_ARG_REGNO_P(N) \ | |
| 111 | 1501 (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \ |
| 1502 || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \ | |
| 0 | 1503 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ |
| 111 | 1504 || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \ |
| 1505 && TARGET_HARD_FLOAT)) | |
| 0 | 1506 |
| 1507 /* Define a data type for recording info about an argument list | |
| 1508 during the scan of that argument list. This data type should | |
| 1509 hold all necessary information about the function itself | |
| 1510 and about the args processed so far, enough to enable macros | |
| 1511 such as FUNCTION_ARG to determine where the next arg should go. | |
| 1512 | |
| 1513 On the RS/6000, this is a structure. The first element is the number of | |
| 1514 total argument words, the second is used to store the next | |
| 1515 floating-point register number, and the third says how many more args we | |
| 1516 have prototype types for. | |
| 1517 | |
| 1518 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is | |
| 1519 the next available GP register, `fregno' is the next available FP | |
| 1520 register, and `words' is the number of words used on the stack. | |
| 1521 | |
| 1522 The varargs/stdarg support requires that this structure's size | |
| 1523 be a multiple of sizeof(int). */ | |
| 1524 | |
| 1525 typedef struct rs6000_args | |
| 1526 { | |
| 1527 int words; /* # words used for passing GP registers */ | |
| 1528 int fregno; /* next available FP register */ | |
| 1529 int vregno; /* next available AltiVec register */ | |
| 1530 int nargs_prototype; /* # args left in the current prototype */ | |
| 1531 int prototype; /* Whether a prototype was defined */ | |
| 1532 int stdarg; /* Whether function is a stdarg function. */ | |
| 1533 int call_cookie; /* Do special things for this call */ | |
| 1534 int sysv_gregno; /* next available GP register */ | |
| 1535 int intoffset; /* running offset in struct (darwin64) */ | |
| 1536 int use_stack; /* any part of struct on stack (darwin64) */ | |
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1537 int floats_in_gpr; /* count of SFmode floats taking up |
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1538 GPR space (darwin64) */ |
| 0 | 1539 int named; /* false for varargs params */ |
|
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1540 int escapes; /* if function visible outside tu */ |
| 111 | 1541 int libcall; /* If this is a compiler generated call. */ |
| 0 | 1542 } CUMULATIVE_ARGS; |
| 1543 | |
| 1544 /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
| 1545 for a call to a function whose data type is FNTYPE. | |
| 1546 For a library call, FNTYPE is 0. */ | |
| 1547 | |
|
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1548 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
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1549 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \ |
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1550 N_NAMED_ARGS, FNDECL, VOIDmode) |
| 0 | 1551 |
| 1552 /* Similar, but when scanning the definition of a procedure. We always | |
| 1553 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ | |
| 1554 | |
| 1555 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ | |
|
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1556 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \ |
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1557 1000, current_function_decl, VOIDmode) |
| 0 | 1558 |
| 1559 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ | |
| 1560 | |
| 1561 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ | |
|
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1562 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \ |
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1563 0, NULL_TREE, MODE) |
| 0 | 1564 |
| 1565 #define PAD_VARARGS_DOWN \ | |
| 111 | 1566 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD) |
| 0 | 1567 |
| 1568 /* Output assembler code to FILE to increment profiler label # LABELNO | |
| 1569 for profiling a function entry. */ | |
| 1570 | |
| 1571 #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
| 1572 output_function_profiler ((FILE), (LABELNO)); | |
| 1573 | |
| 1574 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
| 1575 the stack pointer does not matter. No definition is equivalent to | |
| 1576 always zero. | |
| 1577 | |
| 1578 On the RS/6000, this is nonzero because we can restore the stack from | |
| 1579 its backpointer, which we maintain. */ | |
| 1580 #define EXIT_IGNORE_STACK 1 | |
| 1581 | |
| 1582 /* Define this macro as a C expression that is nonzero for registers | |
| 1583 that are used by the epilogue or the return' pattern. The stack | |
| 1584 and frame pointer registers are already be assumed to be used as | |
| 1585 needed. */ | |
| 1586 | |
| 1587 #define EPILOGUE_USES(REGNO) \ | |
| 1588 ((reload_completed && (REGNO) == LR_REGNO) \ | |
| 1589 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ | |
|
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1590 || (crtl->calls_eh_return \ |
| 0 | 1591 && TARGET_AIX \ |
| 1592 && (REGNO) == 2)) | |
| 1593 | |
| 1594 | |
| 1595 /* Length in units of the trampoline for entering a nested function. */ | |
| 1596 | |
| 1597 #define TRAMPOLINE_SIZE rs6000_trampoline_size () | |
| 1598 | |
| 1599 /* Definitions for __builtin_return_address and __builtin_frame_address. | |
| 111 | 1600 __builtin_return_address (0) should give link register (LR_REGNO), enable |
| 0 | 1601 this. */ |
| 1602 /* This should be uncommented, so that the link register is used, but | |
| 1603 currently this would result in unmatched insns and spilling fixed | |
| 1604 registers so we'll leave it for another day. When these problems are | |
| 1605 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. | |
| 1606 (mrs) */ | |
| 1607 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ | |
| 1608 | |
| 1609 /* Number of bytes into the frame return addresses can be found. See | |
| 1610 rs6000_stack_info in rs6000.c for more information on how the different | |
| 1611 abi's store the return address. */ | |
| 111 | 1612 #define RETURN_ADDRESS_OFFSET \ |
| 1613 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0)) | |
| 0 | 1614 |
| 145 | 1615 /* The current return address is in the link register. The return address |
| 0 | 1616 of anything farther back is accessed normally at an offset of 8 from the |
| 1617 frame pointer. */ | |
| 1618 #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
| 1619 (rs6000_return_addr (COUNT, FRAME)) | |
| 1620 | |
| 1621 | |
| 1622 /* Definitions for register eliminations. | |
| 1623 | |
| 1624 We have two registers that can be eliminated on the RS/6000. First, the | |
| 1625 frame pointer register can often be eliminated in favor of the stack | |
| 1626 pointer register. Secondly, the argument pointer register can always be | |
| 1627 eliminated; it is replaced with either the stack or frame pointer. | |
| 1628 | |
| 1629 In addition, we use the elimination mechanism to see if r30 is needed | |
| 1630 Initially we assume that it isn't. If it is, we spill it. This is done | |
| 1631 by making it an eliminable register. We replace it with itself so that | |
| 1632 if it isn't needed, then existing uses won't be modified. */ | |
| 1633 | |
| 1634 /* This is an array of structures. Each structure initializes one pair | |
| 1635 of eliminable registers. The "from" register number is given first, | |
| 1636 followed by "to". Eliminations of the same "from" register are listed | |
| 1637 in order of preference. */ | |
| 1638 #define ELIMINABLE_REGS \ | |
| 1639 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 1640 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 1641 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
| 1642 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 1643 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
| 1644 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } | |
| 1645 | |
| 1646 /* Define the offset between two registers, one to be eliminated, and the other | |
| 1647 its replacement, at the start of a routine. */ | |
| 1648 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
| 1649 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) | |
| 1650 | |
| 1651 /* Addressing modes, and classification of registers for them. */ | |
| 1652 | |
| 1653 #define HAVE_PRE_DECREMENT 1 | |
| 1654 #define HAVE_PRE_INCREMENT 1 | |
| 1655 #define HAVE_PRE_MODIFY_DISP 1 | |
| 1656 #define HAVE_PRE_MODIFY_REG 1 | |
| 1657 | |
| 1658 /* Macros to check register numbers against specific register classes. */ | |
| 1659 | |
| 1660 /* These assume that REGNO is a hard or pseudo reg number. | |
| 1661 They give nonzero only if REGNO is a hard reg of the suitable class | |
| 1662 or a pseudo reg currently allocated to a suitable hard reg. | |
| 1663 Since they use reg_renumber, they are safe only once reg_renumber | |
| 111 | 1664 has been allocated, which happens in reginfo.c during register |
| 1665 allocation. */ | |
| 0 | 1666 |
| 1667 #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
| 145 | 1668 (HARD_REGISTER_NUM_P (REGNO) \ |
| 1669 ? (REGNO) <= 31 \ | |
| 1670 || (REGNO) == ARG_POINTER_REGNUM \ | |
| 0 | 1671 || (REGNO) == FRAME_POINTER_REGNUM \ |
| 1672 : (reg_renumber[REGNO] >= 0 \ | |
| 145 | 1673 && (reg_renumber[REGNO] <= 31 \ |
| 1674 || reg_renumber[REGNO] == ARG_POINTER_REGNUM \ | |
| 0 | 1675 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) |
| 1676 | |
| 1677 #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
| 145 | 1678 (HARD_REGISTER_NUM_P (REGNO) \ |
| 1679 ? ((REGNO) > 0 && (REGNO) <= 31) \ | |
| 1680 || (REGNO) == ARG_POINTER_REGNUM \ | |
| 0 | 1681 || (REGNO) == FRAME_POINTER_REGNUM \ |
| 1682 : (reg_renumber[REGNO] > 0 \ | |
| 145 | 1683 && (reg_renumber[REGNO] <= 31 \ |
| 1684 || reg_renumber[REGNO] == ARG_POINTER_REGNUM \ | |
| 0 | 1685 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) |
|
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1686 |
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1687 /* Nonzero if X is a hard reg that can be used as an index |
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1688 or if it is a pseudo reg in the non-strict case. */ |
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1689 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ |
| 145 | 1690 ((!(STRICT) && !HARD_REGISTER_P (X)) \ |
|
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1691 || REGNO_OK_FOR_INDEX_P (REGNO (X))) |
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1692 |
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1693 /* Nonzero if X is a hard reg that can be used as a base reg |
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1694 or if it is a pseudo reg in the non-strict case. */ |
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1695 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ |
| 145 | 1696 ((!(STRICT) && !HARD_REGISTER_P (X)) \ |
|
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1697 || REGNO_OK_FOR_BASE_P (REGNO (X))) |
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1698 |
| 0 | 1699 |
| 1700 /* Maximum number of registers that can appear in a valid memory address. */ | |
| 1701 | |
| 1702 #define MAX_REGS_PER_ADDRESS 2 | |
| 1703 | |
| 1704 /* Recognize any constant value that is a valid address. */ | |
| 1705 | |
| 1706 #define CONSTANT_ADDRESS_P(X) \ | |
| 145 | 1707 (GET_CODE (X) == LABEL_REF || SYMBOL_REF_P (X) \ |
| 1708 || CONST_INT_P (X) || GET_CODE (X) == CONST \ | |
| 0 | 1709 || GET_CODE (X) == HIGH) |
| 1710 | |
| 1711 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) | |
| 1712 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ | |
| 1713 && EASY_VECTOR_15((n) >> 1) \ | |
| 1714 && ((n) & 1) == 0) | |
| 1715 | |
|
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1716 #define EASY_VECTOR_MSB(n,mode) \ |
| 111 | 1717 ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \ |
|
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1718 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) |
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1719 |
| 0 | 1720 |
| 1721 #define FIND_BASE_TERM rs6000_find_base_term | |
| 1722 | |
| 1723 /* The register number of the register used to address a table of | |
| 1724 static data addresses in memory. In some cases this register is | |
| 1725 defined by a processor's "application binary interface" (ABI). | |
| 1726 When this macro is defined, RTL is generated for this register | |
| 1727 once, as with the stack pointer and frame pointer registers. If | |
| 1728 this macro is not defined, it is up to the machine-dependent files | |
| 1729 to allocate such a register (if necessary). */ | |
| 1730 | |
| 1731 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 | |
| 111 | 1732 #define PIC_OFFSET_TABLE_REGNUM \ |
| 1733 (TARGET_TOC ? TOC_REGISTER \ | |
| 1734 : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \ | |
| 1735 : INVALID_REGNUM) | |
| 0 | 1736 |
| 1737 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) | |
| 1738 | |
| 1739 /* Define this macro if the register defined by | |
| 1740 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define | |
| 1741 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ | |
| 1742 | |
| 1743 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ | |
| 1744 | |
| 1745 /* A C expression that is nonzero if X is a legitimate immediate | |
| 1746 operand on the target machine when generating position independent | |
| 1747 code. You can assume that X satisfies `CONSTANT_P', so you need | |
| 1748 not check this. You can also assume FLAG_PIC is true, so you need | |
| 1749 not check it either. You need not define this macro if all | |
| 1750 constants (including `SYMBOL_REF') can be immediate operands when | |
| 1751 generating position independent code. */ | |
| 1752 | |
| 1753 /* #define LEGITIMATE_PIC_OPERAND_P (X) */ | |
| 1754 | |
| 1755 /* Specify the machine mode that this machine uses | |
| 1756 for the index in the tablejump instruction. */ | |
| 1757 #define CASE_VECTOR_MODE SImode | |
| 1758 | |
| 1759 /* Define as C expression which evaluates to nonzero if the tablejump | |
| 1760 instruction expects the table to contain offsets from the address of the | |
| 1761 table. | |
| 1762 Do not define this if the table should contain absolute addresses. */ | |
| 1763 #define CASE_VECTOR_PC_RELATIVE 1 | |
| 1764 | |
| 1765 /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
| 1766 #define DEFAULT_SIGNED_CHAR 0 | |
| 1767 | |
| 1768 /* An integer expression for the size in bits of the largest integer machine | |
| 1769 mode that should actually be used. */ | |
| 1770 | |
| 1771 /* Allow pairs of registers to be used, which is the intent of the default. */ | |
| 1772 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) | |
| 1773 | |
| 1774 /* Max number of bytes we can move from memory to memory | |
| 1775 in one reasonably fast instruction. */ | |
| 1776 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) | |
| 1777 #define MAX_MOVE_MAX 8 | |
| 1778 | |
| 1779 /* Nonzero if access to memory by bytes is no faster than for words. | |
| 1780 Also nonzero if doing byte operations (specifically shifts) in registers | |
| 1781 is undesirable. */ | |
| 1782 #define SLOW_BYTE_ACCESS 1 | |
| 1783 | |
| 1784 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
| 1785 will either zero-extend or sign-extend. The value of this macro should | |
| 1786 be the code that says which one of the two operations is implicitly | |
| 1787 done, UNKNOWN if none. */ | |
| 1788 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
| 1789 | |
| 1790 /* Define if loading short immediate values into registers sign extends. */ | |
| 111 | 1791 #define SHORT_IMMEDIATES_SIGN_EXTEND 1 |
| 0 | 1792 |
| 1793 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ | |
| 1794 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
| 111 | 1795 ((VALUE) = GET_MODE_BITSIZE (MODE), 2) |
| 1796 | |
| 1797 /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of | |
| 1798 zero. The hardware instructions added in Power9 and the sequences using | |
| 1799 popcount return 32 or 64. */ | |
| 1800 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
| 1801 (TARGET_CTZ || TARGET_POPCNTD \ | |
| 1802 ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \ | |
| 1803 : ((VALUE) = -1, 2)) | |
| 0 | 1804 |
| 1805 /* Specify the machine mode that pointers have. | |
| 1806 After generation of rtl, the compiler makes no further distinction | |
| 1807 between pointers and any other objects of this machine mode. */ | |
| 111 | 1808 extern scalar_int_mode rs6000_pmode; |
| 1809 #define Pmode rs6000_pmode | |
| 0 | 1810 |
| 1811 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ | |
| 1812 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) | |
| 1813 | |
| 1814 /* Mode of a function address in a call instruction (for indexing purposes). | |
| 1815 Doesn't matter on RS/6000. */ | |
| 1816 #define FUNCTION_MODE SImode | |
| 1817 | |
| 1818 /* Define this if addresses of constant functions | |
| 1819 shouldn't be put through pseudo regs where they can be cse'd. | |
| 1820 Desirable on machines where ordinary constants are expensive | |
| 1821 but a CALL with constant address is cheap. */ | |
| 111 | 1822 #define NO_FUNCTION_CSE 1 |
| 0 | 1823 |
| 1824 /* Define this to be nonzero if shift instructions ignore all but the low-order | |
| 1825 few bits. | |
| 1826 | |
| 1827 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED | |
| 1828 have been dropped from the PowerPC architecture. */ | |
| 111 | 1829 #define SHIFT_COUNT_TRUNCATED 0 |
| 0 | 1830 |
| 1831 /* Adjust the length of an INSN. LENGTH is the currently-computed length and | |
| 1832 should be adjusted to reflect any required changes. This macro is used when | |
| 1833 there is some systematic length adjustment required that would be difficult | |
| 145 | 1834 to express in the length attribute. |
| 1835 | |
| 1836 In the PowerPC, we use this to adjust the length of an instruction if one or | |
| 1837 more prefixed instructions are generated, using the attribute | |
| 1838 num_prefixed_insns. A prefixed instruction is 8 bytes instead of 4, but the | |
| 1839 hardware requires that a prefied instruciton does not cross a 64-byte | |
| 1840 boundary. This means the compiler has to assume the length of the first | |
| 1841 prefixed instruction is 12 bytes instead of 8 bytes. Since the length is | |
| 1842 already set for the non-prefixed instruction, we just need to udpate for the | |
| 1843 difference. */ | |
| 1844 | |
| 1845 #define ADJUST_INSN_LENGTH(INSN,LENGTH) \ | |
| 1846 (LENGTH) = rs6000_adjust_insn_length ((INSN), (LENGTH)) | |
| 0 | 1847 |
| 1848 /* Given a comparison code (EQ, NE, etc.) and the first operand of a | |
| 1849 COMPARE, return the mode to be used for the comparison. For | |
| 1850 floating-point, CCFPmode should be used. CCUNSmode should be used | |
| 1851 for unsigned comparisons. CCEQmode should be used when we are | |
| 1852 doing an inequality comparison on the result of a | |
| 1853 comparison. CCmode should be used in all other cases. */ | |
| 1854 | |
| 1855 #define SELECT_CC_MODE(OP,X,Y) \ | |
| 1856 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ | |
| 1857 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ | |
| 1858 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ | |
| 1859 ? CCEQmode : CCmode)) | |
| 1860 | |
| 1861 /* Can the condition code MODE be safely reversed? This is safe in | |
| 1862 all cases on this port, because at present it doesn't use the | |
| 1863 trapping FP comparisons (fcmpo). */ | |
| 1864 #define REVERSIBLE_CC_MODE(MODE) 1 | |
| 1865 | |
| 1866 /* Given a condition code and a mode, return the inverse condition. */ | |
| 1867 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) | |
| 1868 | |
| 1869 | |
| 111 | 1870 /* Target cpu costs. */ |
| 1871 | |
| 1872 struct processor_costs { | |
| 1873 const int mulsi; /* cost of SImode multiplication. */ | |
| 1874 const int mulsi_const; /* cost of SImode multiplication by constant. */ | |
| 1875 const int mulsi_const9; /* cost of SImode mult by short constant. */ | |
| 1876 const int muldi; /* cost of DImode multiplication. */ | |
| 1877 const int divsi; /* cost of SImode division. */ | |
| 1878 const int divdi; /* cost of DImode division. */ | |
| 1879 const int fp; /* cost of simple SFmode and DFmode insns. */ | |
| 1880 const int dmul; /* cost of DFmode multiplication (and fmadd). */ | |
| 1881 const int sdiv; /* cost of SFmode division (fdivs). */ | |
| 1882 const int ddiv; /* cost of DFmode division (fdiv). */ | |
| 1883 const int cache_line_size; /* cache line size in bytes. */ | |
| 1884 const int l1_cache_size; /* size of l1 cache, in kilobytes. */ | |
| 1885 const int l2_cache_size; /* size of l2 cache, in kilobytes. */ | |
| 1886 const int simultaneous_prefetches; /* number of parallel prefetch | |
| 1887 operations. */ | |
| 1888 const int sfdf_convert; /* cost of SF->DF conversion. */ | |
| 1889 }; | |
| 1890 | |
| 1891 extern const struct processor_costs *rs6000_cost; | |
| 1892 | |
| 0 | 1893 /* Control the assembler format that we output. */ |
| 1894 | |
| 1895 /* A C string constant describing how to begin a comment in the target | |
| 1896 assembler language. The compiler assumes that the comment will end at | |
| 1897 the end of the line. */ | |
| 1898 #define ASM_COMMENT_START " #" | |
| 1899 | |
| 1900 /* Flag to say the TOC is initialized */ | |
| 1901 extern int toc_initialized; | |
| 1902 | |
| 1903 /* Macro to output a special constant pool entry. Go to WIN if we output | |
| 1904 it. Otherwise, it is written the usual way. | |
| 1905 | |
| 1906 On the RS/6000, toc entries are handled this way. */ | |
| 1907 | |
| 1908 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ | |
| 1909 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ | |
| 1910 { \ | |
| 1911 output_toc (FILE, X, LABELNO, MODE); \ | |
| 1912 goto WIN; \ | |
| 1913 } \ | |
| 1914 } | |
| 1915 | |
| 1916 #ifdef HAVE_GAS_WEAK | |
| 1917 #define RS6000_WEAK 1 | |
| 1918 #else | |
| 1919 #define RS6000_WEAK 0 | |
| 1920 #endif | |
| 1921 | |
| 1922 #if RS6000_WEAK | |
| 1923 /* Used in lieu of ASM_WEAKEN_LABEL. */ | |
| 111 | 1924 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ |
| 1925 rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL)) | |
| 0 | 1926 #endif |
| 1927 | |
| 1928 #if HAVE_GAS_WEAKREF | |
| 1929 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ | |
| 1930 do \ | |
| 1931 { \ | |
| 1932 fputs ("\t.weakref\t", (FILE)); \ | |
| 1933 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
| 1934 fputs (", ", (FILE)); \ | |
| 1935 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
| 1936 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ | |
| 1937 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ | |
| 1938 { \ | |
| 1939 fputs ("\n\t.weakref\t.", (FILE)); \ | |
| 1940 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
| 1941 fputs (", .", (FILE)); \ | |
| 1942 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
| 1943 } \ | |
| 1944 fputc ('\n', (FILE)); \ | |
| 1945 } while (0) | |
| 1946 #endif | |
| 1947 | |
| 1948 /* This implements the `alias' attribute. */ | |
| 1949 #undef ASM_OUTPUT_DEF_FROM_DECLS | |
| 1950 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ | |
| 1951 do \ | |
| 1952 { \ | |
| 1953 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ | |
| 1954 const char *name = IDENTIFIER_POINTER (TARGET); \ | |
| 1955 if (TREE_CODE (DECL) == FUNCTION_DECL \ | |
| 1956 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ | |
| 1957 { \ | |
| 1958 if (TREE_PUBLIC (DECL)) \ | |
| 1959 { \ | |
| 1960 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ | |
| 1961 { \ | |
| 1962 fputs ("\t.globl\t.", FILE); \ | |
| 1963 RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
| 1964 putc ('\n', FILE); \ | |
| 1965 } \ | |
| 1966 } \ | |
| 1967 else if (TARGET_XCOFF) \ | |
| 1968 { \ | |
| 111 | 1969 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ |
| 1970 { \ | |
| 1971 fputs ("\t.lglobl\t.", FILE); \ | |
| 1972 RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
| 1973 putc ('\n', FILE); \ | |
| 1974 fputs ("\t.lglobl\t", FILE); \ | |
| 1975 RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
| 1976 putc ('\n', FILE); \ | |
| 1977 } \ | |
| 0 | 1978 } \ |
| 1979 fputs ("\t.set\t.", FILE); \ | |
| 1980 RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
| 1981 fputs (",.", FILE); \ | |
| 1982 RS6000_OUTPUT_BASENAME (FILE, name); \ | |
| 1983 fputc ('\n', FILE); \ | |
| 1984 } \ | |
| 1985 ASM_OUTPUT_DEF (FILE, alias, name); \ | |
| 1986 } \ | |
| 1987 while (0) | |
| 1988 | |
| 1989 #define TARGET_ASM_FILE_START rs6000_file_start | |
| 1990 | |
| 1991 /* Output to assembler file text saying following lines | |
| 1992 may contain character constants, extra white space, comments, etc. */ | |
| 1993 | |
| 1994 #define ASM_APP_ON "" | |
| 1995 | |
| 1996 /* Output to assembler file text saying following lines | |
| 1997 no longer contain unusual constructs. */ | |
| 1998 | |
| 1999 #define ASM_APP_OFF "" | |
| 2000 | |
| 2001 /* How to refer to registers in assembler output. | |
| 2002 This sequence is indexed by compiler's hard-register-number (see above). */ | |
| 2003 | |
| 2004 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ | |
| 2005 | |
| 2006 #define REGISTER_NAMES \ | |
| 2007 { \ | |
| 2008 &rs6000_reg_names[ 0][0], /* r0 */ \ | |
| 2009 &rs6000_reg_names[ 1][0], /* r1 */ \ | |
| 145 | 2010 &rs6000_reg_names[ 2][0], /* r2 */ \ |
| 0 | 2011 &rs6000_reg_names[ 3][0], /* r3 */ \ |
| 2012 &rs6000_reg_names[ 4][0], /* r4 */ \ | |
| 2013 &rs6000_reg_names[ 5][0], /* r5 */ \ | |
| 2014 &rs6000_reg_names[ 6][0], /* r6 */ \ | |
| 2015 &rs6000_reg_names[ 7][0], /* r7 */ \ | |
| 2016 &rs6000_reg_names[ 8][0], /* r8 */ \ | |
| 2017 &rs6000_reg_names[ 9][0], /* r9 */ \ | |
| 2018 &rs6000_reg_names[10][0], /* r10 */ \ | |
| 2019 &rs6000_reg_names[11][0], /* r11 */ \ | |
| 2020 &rs6000_reg_names[12][0], /* r12 */ \ | |
| 2021 &rs6000_reg_names[13][0], /* r13 */ \ | |
| 2022 &rs6000_reg_names[14][0], /* r14 */ \ | |
| 2023 &rs6000_reg_names[15][0], /* r15 */ \ | |
| 2024 &rs6000_reg_names[16][0], /* r16 */ \ | |
| 2025 &rs6000_reg_names[17][0], /* r17 */ \ | |
| 2026 &rs6000_reg_names[18][0], /* r18 */ \ | |
| 2027 &rs6000_reg_names[19][0], /* r19 */ \ | |
| 2028 &rs6000_reg_names[20][0], /* r20 */ \ | |
| 2029 &rs6000_reg_names[21][0], /* r21 */ \ | |
| 2030 &rs6000_reg_names[22][0], /* r22 */ \ | |
| 2031 &rs6000_reg_names[23][0], /* r23 */ \ | |
| 2032 &rs6000_reg_names[24][0], /* r24 */ \ | |
| 2033 &rs6000_reg_names[25][0], /* r25 */ \ | |
| 2034 &rs6000_reg_names[26][0], /* r26 */ \ | |
| 2035 &rs6000_reg_names[27][0], /* r27 */ \ | |
| 2036 &rs6000_reg_names[28][0], /* r28 */ \ | |
| 2037 &rs6000_reg_names[29][0], /* r29 */ \ | |
| 2038 &rs6000_reg_names[30][0], /* r30 */ \ | |
| 2039 &rs6000_reg_names[31][0], /* r31 */ \ | |
| 2040 \ | |
| 145 | 2041 &rs6000_reg_names[32][0], /* fr0 */ \ |
| 0 | 2042 &rs6000_reg_names[33][0], /* fr1 */ \ |
| 2043 &rs6000_reg_names[34][0], /* fr2 */ \ | |
| 2044 &rs6000_reg_names[35][0], /* fr3 */ \ | |
| 2045 &rs6000_reg_names[36][0], /* fr4 */ \ | |
| 2046 &rs6000_reg_names[37][0], /* fr5 */ \ | |
| 2047 &rs6000_reg_names[38][0], /* fr6 */ \ | |
| 2048 &rs6000_reg_names[39][0], /* fr7 */ \ | |
| 2049 &rs6000_reg_names[40][0], /* fr8 */ \ | |
| 2050 &rs6000_reg_names[41][0], /* fr9 */ \ | |
| 2051 &rs6000_reg_names[42][0], /* fr10 */ \ | |
| 2052 &rs6000_reg_names[43][0], /* fr11 */ \ | |
| 2053 &rs6000_reg_names[44][0], /* fr12 */ \ | |
| 2054 &rs6000_reg_names[45][0], /* fr13 */ \ | |
| 2055 &rs6000_reg_names[46][0], /* fr14 */ \ | |
| 2056 &rs6000_reg_names[47][0], /* fr15 */ \ | |
| 2057 &rs6000_reg_names[48][0], /* fr16 */ \ | |
| 2058 &rs6000_reg_names[49][0], /* fr17 */ \ | |
| 2059 &rs6000_reg_names[50][0], /* fr18 */ \ | |
| 2060 &rs6000_reg_names[51][0], /* fr19 */ \ | |
| 2061 &rs6000_reg_names[52][0], /* fr20 */ \ | |
| 2062 &rs6000_reg_names[53][0], /* fr21 */ \ | |
| 2063 &rs6000_reg_names[54][0], /* fr22 */ \ | |
| 2064 &rs6000_reg_names[55][0], /* fr23 */ \ | |
| 2065 &rs6000_reg_names[56][0], /* fr24 */ \ | |
| 2066 &rs6000_reg_names[57][0], /* fr25 */ \ | |
| 2067 &rs6000_reg_names[58][0], /* fr26 */ \ | |
| 2068 &rs6000_reg_names[59][0], /* fr27 */ \ | |
| 2069 &rs6000_reg_names[60][0], /* fr28 */ \ | |
| 2070 &rs6000_reg_names[61][0], /* fr29 */ \ | |
| 2071 &rs6000_reg_names[62][0], /* fr30 */ \ | |
| 2072 &rs6000_reg_names[63][0], /* fr31 */ \ | |
| 2073 \ | |
| 145 | 2074 &rs6000_reg_names[64][0], /* vr0 */ \ |
| 2075 &rs6000_reg_names[65][0], /* vr1 */ \ | |
| 2076 &rs6000_reg_names[66][0], /* vr2 */ \ | |
| 2077 &rs6000_reg_names[67][0], /* vr3 */ \ | |
| 2078 &rs6000_reg_names[68][0], /* vr4 */ \ | |
| 2079 &rs6000_reg_names[69][0], /* vr5 */ \ | |
| 2080 &rs6000_reg_names[70][0], /* vr6 */ \ | |
| 2081 &rs6000_reg_names[71][0], /* vr7 */ \ | |
| 2082 &rs6000_reg_names[72][0], /* vr8 */ \ | |
| 2083 &rs6000_reg_names[73][0], /* vr9 */ \ | |
| 2084 &rs6000_reg_names[74][0], /* vr10 */ \ | |
| 2085 &rs6000_reg_names[75][0], /* vr11 */ \ | |
| 2086 &rs6000_reg_names[76][0], /* vr12 */ \ | |
| 2087 &rs6000_reg_names[77][0], /* vr13 */ \ | |
| 2088 &rs6000_reg_names[78][0], /* vr14 */ \ | |
| 2089 &rs6000_reg_names[79][0], /* vr15 */ \ | |
| 2090 &rs6000_reg_names[80][0], /* vr16 */ \ | |
| 2091 &rs6000_reg_names[81][0], /* vr17 */ \ | |
| 2092 &rs6000_reg_names[82][0], /* vr18 */ \ | |
| 2093 &rs6000_reg_names[83][0], /* vr19 */ \ | |
| 2094 &rs6000_reg_names[84][0], /* vr20 */ \ | |
| 2095 &rs6000_reg_names[85][0], /* vr21 */ \ | |
| 2096 &rs6000_reg_names[86][0], /* vr22 */ \ | |
| 2097 &rs6000_reg_names[87][0], /* vr23 */ \ | |
| 2098 &rs6000_reg_names[88][0], /* vr24 */ \ | |
| 2099 &rs6000_reg_names[89][0], /* vr25 */ \ | |
| 2100 &rs6000_reg_names[90][0], /* vr26 */ \ | |
| 2101 &rs6000_reg_names[91][0], /* vr27 */ \ | |
| 2102 &rs6000_reg_names[92][0], /* vr28 */ \ | |
| 2103 &rs6000_reg_names[93][0], /* vr29 */ \ | |
| 2104 &rs6000_reg_names[94][0], /* vr30 */ \ | |
| 2105 &rs6000_reg_names[95][0], /* vr31 */ \ | |
| 0 | 2106 \ |
| 145 | 2107 &rs6000_reg_names[96][0], /* lr */ \ |
| 2108 &rs6000_reg_names[97][0], /* ctr */ \ | |
| 2109 &rs6000_reg_names[98][0], /* ca */ \ | |
| 2110 &rs6000_reg_names[99][0], /* ap */ \ | |
| 2111 \ | |
| 2112 &rs6000_reg_names[100][0], /* cr0 */ \ | |
| 2113 &rs6000_reg_names[101][0], /* cr1 */ \ | |
| 2114 &rs6000_reg_names[102][0], /* cr2 */ \ | |
| 2115 &rs6000_reg_names[103][0], /* cr3 */ \ | |
| 2116 &rs6000_reg_names[104][0], /* cr4 */ \ | |
| 2117 &rs6000_reg_names[105][0], /* cr5 */ \ | |
| 2118 &rs6000_reg_names[106][0], /* cr6 */ \ | |
| 2119 &rs6000_reg_names[107][0], /* cr7 */ \ | |
| 2120 \ | |
| 2121 &rs6000_reg_names[108][0], /* vrsave */ \ | |
| 2122 &rs6000_reg_names[109][0], /* vscr */ \ | |
| 2123 \ | |
| 2124 &rs6000_reg_names[110][0] /* sfp */ \ | |
| 0 | 2125 } |
| 2126 | |
| 2127 /* Table of additional register names to use in user input. */ | |
| 2128 | |
| 2129 #define ADDITIONAL_REGISTER_NAMES \ | |
| 2130 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ | |
| 2131 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ | |
| 2132 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ | |
| 2133 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ | |
| 2134 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ | |
| 2135 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ | |
| 2136 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ | |
| 2137 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ | |
| 2138 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ | |
| 2139 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ | |
| 2140 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ | |
| 2141 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ | |
| 2142 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ | |
| 2143 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ | |
| 2144 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ | |
| 2145 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ | |
| 145 | 2146 {"v0", 64}, {"v1", 65}, {"v2", 66}, {"v3", 67}, \ |
| 2147 {"v4", 68}, {"v5", 69}, {"v6", 70}, {"v7", 71}, \ | |
| 2148 {"v8", 72}, {"v9", 73}, {"v10", 74}, {"v11", 75}, \ | |
| 2149 {"v12", 76}, {"v13", 77}, {"v14", 78}, {"v15", 79}, \ | |
| 2150 {"v16", 80}, {"v17", 81}, {"v18", 82}, {"v19", 83}, \ | |
| 2151 {"v20", 84}, {"v21", 85}, {"v22", 86}, {"v23", 87}, \ | |
| 2152 {"v24", 88}, {"v25", 89}, {"v26", 90}, {"v27", 91}, \ | |
| 2153 {"v28", 92}, {"v29", 93}, {"v30", 94}, {"v31", 95}, \ | |
| 2154 {"vrsave", 108}, {"vscr", 109}, \ | |
| 111 | 2155 /* no additional names for: lr, ctr, ap */ \ |
| 145 | 2156 {"cr0", 100},{"cr1", 101},{"cr2", 102},{"cr3", 103}, \ |
| 2157 {"cr4", 104},{"cr5", 105},{"cr6", 106},{"cr7", 107}, \ | |
| 2158 {"cc", 100},{"sp", 1}, {"toc", 2}, \ | |
|
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|
2159 /* CA is only part of XER, but we do not model the other parts (yet). */ \ |
| 145 | 2160 {"xer", 98}, \ |
|
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|
2161 /* VSX registers overlaid on top of FR, Altivec registers */ \ |
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2162 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ |
|
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|
2163 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ |
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2164 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ |
|
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2165 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ |
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2166 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ |
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2167 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ |
|
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|
2168 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ |
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|
2169 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ |
| 145 | 2170 {"vs32", 64}, {"vs33", 65}, {"vs34", 66}, {"vs35", 67}, \ |
| 2171 {"vs36", 68}, {"vs37", 69}, {"vs38", 70}, {"vs39", 71}, \ | |
| 2172 {"vs40", 72}, {"vs41", 73}, {"vs42", 74}, {"vs43", 75}, \ | |
| 2173 {"vs44", 76}, {"vs45", 77}, {"vs46", 78}, {"vs47", 79}, \ | |
| 2174 {"vs48", 80}, {"vs49", 81}, {"vs50", 82}, {"vs51", 83}, \ | |
| 2175 {"vs52", 84}, {"vs53", 85}, {"vs54", 86}, {"vs55", 87}, \ | |
| 2176 {"vs56", 88}, {"vs57", 89}, {"vs58", 90}, {"vs59", 91}, \ | |
| 2177 {"vs60", 92}, {"vs61", 93}, {"vs62", 94}, {"vs63", 95}, \ | |
| 111 | 2178 } |
| 0 | 2179 |
| 2180 /* This is how to output an element of a case-vector that is relative. */ | |
| 2181 | |
| 2182 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
| 2183 do { char buf[100]; \ | |
| 2184 fputs ("\t.long ", FILE); \ | |
| 2185 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ | |
| 2186 assemble_name (FILE, buf); \ | |
| 2187 putc ('-', FILE); \ | |
| 2188 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ | |
| 2189 assemble_name (FILE, buf); \ | |
| 2190 putc ('\n', FILE); \ | |
| 2191 } while (0) | |
| 2192 | |
| 2193 /* This is how to output an assembler line | |
| 2194 that says to advance the location counter | |
| 2195 to a multiple of 2**LOG bytes. */ | |
| 2196 | |
| 2197 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
| 2198 if ((LOG) != 0) \ | |
| 2199 fprintf (FILE, "\t.align %d\n", (LOG)) | |
| 2200 | |
|
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|
2201 /* How to align the given loop. */ |
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2202 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL) |
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|
2203 |
| 111 | 2204 /* Alignment guaranteed by __builtin_malloc. */ |
| 2205 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT. | |
| 2206 However, specifying the stronger guarantee currently leads to | |
| 2207 a regression in SPEC CPU2006 437.leslie3d. The stronger | |
| 2208 guarantee should be implemented here once that's fixed. */ | |
| 2209 #define MALLOC_ABI_ALIGNMENT (64) | |
| 2210 | |
| 0 | 2211 /* Pick up the return address upon entry to a procedure. Used for |
| 2212 dwarf2 unwind information. This also enables the table driven | |
| 2213 mechanism. */ | |
| 2214 | |
| 2215 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) | |
| 2216 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) | |
| 2217 | |
| 2218 /* Describe how we implement __builtin_eh_return. */ | |
| 2219 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) | |
| 2220 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) | |
| 2221 | |
| 2222 /* Print operand X (an rtx) in assembler syntax to file FILE. | |
| 2223 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
| 2224 For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
| 2225 | |
| 2226 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
| 2227 | |
| 2228 /* Define which CODE values are valid. */ | |
| 2229 | |
| 111 | 2230 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&') |
| 0 | 2231 |
| 2232 /* Print a memory address as an operand to reference that memory location. */ | |
| 2233 | |
| 2234 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
| 2235 | |
| 111 | 2236 /* For switching between functions with different target attributes. */ |
| 2237 #define SWITCHABLE_TARGET 1 | |
| 2238 | |
| 0 | 2239 /* uncomment for disabling the corresponding default options */ |
| 2240 /* #define MACHINE_no_sched_interblock */ | |
| 2241 /* #define MACHINE_no_sched_speculative */ | |
| 2242 /* #define MACHINE_no_sched_speculative_load */ | |
| 2243 | |
| 2244 /* General flags. */ | |
| 2245 extern int frame_pointer_needed; | |
| 2246 | |
| 111 | 2247 /* Classification of the builtin functions as to which switches enable the |
| 2248 builtin, and what attributes it should have. We used to use the target | |
| 2249 flags macros, but we've run out of bits, so we now map the options into new | |
| 2250 settings used here. */ | |
| 2251 | |
| 2252 /* Builtin attributes. */ | |
| 2253 #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */ | |
| 2254 #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */ | |
| 2255 #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */ | |
| 2256 #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */ | |
| 2257 #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */ | |
| 2258 #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */ | |
| 2259 #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */ | |
| 2260 #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */ | |
| 2261 | |
| 2262 #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */ | |
| 2263 #define RS6000_BTC_CONST 0x00000100 /* Neither uses, nor | |
| 2264 modifies global state. */ | |
| 2265 #define RS6000_BTC_PURE 0x00000200 /* reads global | |
| 2266 state/mem and does | |
| 2267 not modify global state. */ | |
| 2268 #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */ | |
| 2269 #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */ | |
| 2270 | |
| 2271 /* Miscellaneous information. */ | |
| 2272 #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */ | |
| 2273 #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */ | |
| 2274 #define RS6000_BTC_CR 0x04000000 /* function references a CR. */ | |
| 2275 #define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */ | |
| 2276 #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */ | |
|
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2277 |
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2278 /* Convenience macros to document the instruction type. */ |
| 111 | 2279 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ |
| 2280 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ | |
| 2281 | |
| 2282 /* Builtin targets. For now, we reuse the masks for those options that are in | |
| 131 | 2283 target flags, and pick a random bit for ldbl128, which isn't in |
| 2284 target_flags. */ | |
| 111 | 2285 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ |
| 2286 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ | |
| 2287 #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */ | |
| 2288 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ | |
| 2289 #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ | |
| 2290 #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ | |
| 2291 #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ | |
| 2292 #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ | |
| 2293 #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ | |
| 2294 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ | |
| 2295 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ | |
| 2296 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ | |
| 2297 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ | |
| 2298 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ | |
| 2299 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ | |
| 2300 #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ | |
| 2301 #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ | |
| 2302 #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ | |
| 2303 #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ | |
| 131 | 2304 #define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */ |
| 111 | 2305 #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */ |
| 2306 #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */ | |
| 2307 | |
| 2308 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ | |
| 2309 | RS6000_BTM_VSX \ | |
| 2310 | RS6000_BTM_P8_VECTOR \ | |
| 2311 | RS6000_BTM_P9_VECTOR \ | |
| 2312 | RS6000_BTM_P9_MISC \ | |
| 2313 | RS6000_BTM_MODULO \ | |
| 2314 | RS6000_BTM_CRYPTO \ | |
| 2315 | RS6000_BTM_FRE \ | |
| 2316 | RS6000_BTM_FRES \ | |
| 2317 | RS6000_BTM_FRSQRTE \ | |
| 2318 | RS6000_BTM_FRSQRTES \ | |
| 2319 | RS6000_BTM_HTM \ | |
| 2320 | RS6000_BTM_POPCNTD \ | |
| 2321 | RS6000_BTM_CELL \ | |
| 2322 | RS6000_BTM_DFP \ | |
| 2323 | RS6000_BTM_HARD_FLOAT \ | |
| 2324 | RS6000_BTM_LDBL128 \ | |
| 131 | 2325 | RS6000_BTM_POWERPC64 \ |
| 111 | 2326 | RS6000_BTM_FLOAT128 \ |
| 2327 | RS6000_BTM_FLOAT128_HW) | |
| 2328 | |
| 2329 /* Define builtin enum index. */ | |
| 2330 | |
| 2331 #undef RS6000_BUILTIN_0 | |
| 2332 #undef RS6000_BUILTIN_1 | |
| 2333 #undef RS6000_BUILTIN_2 | |
| 2334 #undef RS6000_BUILTIN_3 | |
| 2335 #undef RS6000_BUILTIN_A | |
| 2336 #undef RS6000_BUILTIN_D | |
| 2337 #undef RS6000_BUILTIN_H | |
| 2338 #undef RS6000_BUILTIN_P | |
| 2339 #undef RS6000_BUILTIN_X | |
| 2340 | |
| 2341 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2342 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2343 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2344 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2345 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2346 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2347 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2348 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2349 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
|
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2350 |
| 0 | 2351 enum rs6000_builtins |
| 2352 { | |
|
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2353 #include "rs6000-builtin.def" |
| 0 | 2354 |
| 2355 RS6000_BUILTIN_COUNT | |
| 2356 }; | |
| 2357 | |
| 111 | 2358 #undef RS6000_BUILTIN_0 |
| 2359 #undef RS6000_BUILTIN_1 | |
| 2360 #undef RS6000_BUILTIN_2 | |
| 2361 #undef RS6000_BUILTIN_3 | |
| 2362 #undef RS6000_BUILTIN_A | |
| 2363 #undef RS6000_BUILTIN_D | |
| 2364 #undef RS6000_BUILTIN_H | |
| 2365 #undef RS6000_BUILTIN_P | |
| 2366 #undef RS6000_BUILTIN_X | |
|
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2367 |
| 145 | 2368 /* Mappings for overloaded builtins. */ |
| 2369 struct altivec_builtin_types | |
| 2370 { | |
| 2371 enum rs6000_builtins code; | |
| 2372 enum rs6000_builtins overloaded_code; | |
| 2373 signed char ret_type; | |
| 2374 signed char op1; | |
| 2375 signed char op2; | |
| 2376 signed char op3; | |
| 2377 }; | |
| 2378 extern const struct altivec_builtin_types altivec_overloaded_builtins[]; | |
| 2379 | |
| 0 | 2380 enum rs6000_builtin_type_index |
| 2381 { | |
| 2382 RS6000_BTI_NOT_OPAQUE, | |
| 2383 RS6000_BTI_opaque_V4SI, | |
| 131 | 2384 RS6000_BTI_V16QI, /* __vector signed char */ |
| 111 | 2385 RS6000_BTI_V1TI, |
|
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2386 RS6000_BTI_V2DI, |
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2387 RS6000_BTI_V2DF, |
| 0 | 2388 RS6000_BTI_V4HI, |
| 2389 RS6000_BTI_V4SI, | |
| 2390 RS6000_BTI_V4SF, | |
| 2391 RS6000_BTI_V8HI, | |
| 131 | 2392 RS6000_BTI_unsigned_V16QI, /* __vector unsigned char */ |
| 111 | 2393 RS6000_BTI_unsigned_V1TI, |
| 0 | 2394 RS6000_BTI_unsigned_V8HI, |
| 2395 RS6000_BTI_unsigned_V4SI, | |
|
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2396 RS6000_BTI_unsigned_V2DI, |
| 0 | 2397 RS6000_BTI_bool_char, /* __bool char */ |
| 2398 RS6000_BTI_bool_short, /* __bool short */ | |
| 2399 RS6000_BTI_bool_int, /* __bool int */ | |
| 131 | 2400 RS6000_BTI_bool_long_long, /* __bool long long */ |
| 2401 RS6000_BTI_pixel, /* __pixel (16 bits arranged as 4 | |
| 2402 channels of 1, 5, 5, and 5 bits | |
| 2403 respectively as packed with the | |
| 2404 vpkpx insn. __pixel is only | |
| 2405 meaningful as a vector type. | |
| 2406 There is no corresponding scalar | |
| 2407 __pixel data type.) */ | |
| 0 | 2408 RS6000_BTI_bool_V16QI, /* __vector __bool char */ |
| 2409 RS6000_BTI_bool_V8HI, /* __vector __bool short */ | |
| 2410 RS6000_BTI_bool_V4SI, /* __vector __bool int */ | |
|
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2411 RS6000_BTI_bool_V2DI, /* __vector __bool long */ |
| 0 | 2412 RS6000_BTI_pixel_V8HI, /* __vector __pixel */ |
| 2413 RS6000_BTI_long, /* long_integer_type_node */ | |
| 2414 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ | |
|
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2415 RS6000_BTI_long_long, /* long_long_integer_type_node */ |
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2416 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ |
| 131 | 2417 RS6000_BTI_INTQI, /* (signed) intQI_type_node */ |
| 0 | 2418 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ |
| 2419 RS6000_BTI_INTHI, /* intHI_type_node */ | |
| 2420 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ | |
| 131 | 2421 RS6000_BTI_INTSI, /* intSI_type_node (signed) */ |
| 0 | 2422 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ |
|
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2423 RS6000_BTI_INTDI, /* intDI_type_node */ |
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2424 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ |
| 111 | 2425 RS6000_BTI_INTTI, /* intTI_type_node */ |
| 2426 RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */ | |
| 0 | 2427 RS6000_BTI_float, /* float_type_node */ |
|
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2428 RS6000_BTI_double, /* double_type_node */ |
| 111 | 2429 RS6000_BTI_long_double, /* long_double_type_node */ |
| 2430 RS6000_BTI_dfloat64, /* dfloat64_type_node */ | |
| 2431 RS6000_BTI_dfloat128, /* dfloat128_type_node */ | |
| 0 | 2432 RS6000_BTI_void, /* void_type_node */ |
| 111 | 2433 RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */ |
| 2434 RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */ | |
| 2435 RS6000_BTI_const_str, /* pointer to const char * */ | |
| 0 | 2436 RS6000_BTI_MAX |
| 2437 }; | |
| 2438 | |
| 2439 | |
| 2440 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) | |
| 2441 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) | |
| 111 | 2442 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI]) |
|
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2443 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) |
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2444 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) |
| 0 | 2445 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) |
| 2446 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) | |
| 2447 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) | |
| 2448 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) | |
| 2449 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) | |
| 111 | 2450 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI]) |
| 0 | 2451 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) |
| 2452 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) | |
|
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2453 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) |
| 0 | 2454 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) |
| 2455 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) | |
| 2456 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) | |
| 131 | 2457 #define bool_long_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long_long]) |
| 0 | 2458 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) |
| 2459 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) | |
| 2460 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) | |
| 2461 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) | |
|
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2462 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) |
| 0 | 2463 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) |
| 2464 | |
|
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2465 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) |
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2466 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) |
| 0 | 2467 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) |
| 2468 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) | |
| 2469 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) | |
| 2470 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) | |
| 2471 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) | |
| 2472 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) | |
| 2473 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) | |
| 2474 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) | |
|
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2475 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) |
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2476 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) |
| 111 | 2477 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI]) |
| 2478 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI]) | |
| 0 | 2479 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) |
|
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2480 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) |
| 111 | 2481 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double]) |
| 2482 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64]) | |
| 2483 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128]) | |
| 0 | 2484 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) |
| 111 | 2485 #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float]) |
| 2486 #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float]) | |
| 2487 #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str]) | |
| 0 | 2488 |
| 2489 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; | |
| 2490 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; | |
| 2491 | |
| 145 | 2492 #ifndef USED_FOR_TARGET |
| 2493 /* A C structure for machine-specific, per-function data. | |
| 2494 This is added to the cfun structure. */ | |
| 2495 typedef struct GTY(()) machine_function | |
| 2496 { | |
| 2497 /* Flags if __builtin_return_address (n) with n >= 1 was used. */ | |
| 2498 int ra_needs_full_frame; | |
| 2499 /* Flags if __builtin_return_address (0) was used. */ | |
| 2500 int ra_need_lr; | |
| 2501 /* Cache lr_save_p after expansion of builtin_eh_return. */ | |
| 2502 int lr_save_state; | |
| 2503 /* Whether we need to save the TOC to the reserved stack location in the | |
| 2504 function prologue. */ | |
| 2505 bool save_toc_in_prologue; | |
| 2506 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4 | |
| 2507 varargs save area. */ | |
| 2508 HOST_WIDE_INT varargs_save_offset; | |
| 2509 /* Alternative internal arg pointer for -fsplit-stack. */ | |
| 2510 rtx split_stack_arg_pointer; | |
| 2511 bool split_stack_argp_used; | |
| 2512 /* Flag if r2 setup is needed with ELFv2 ABI. */ | |
| 2513 bool r2_setup_needed; | |
| 2514 /* The number of components we use for separate shrink-wrapping. */ | |
| 2515 int n_components; | |
| 2516 /* The components already handled by separate shrink-wrapping, which should | |
| 2517 not be considered by the prologue and epilogue. */ | |
| 2518 bool gpr_is_wrapped_separately[32]; | |
| 2519 bool fpr_is_wrapped_separately[32]; | |
| 2520 bool lr_is_wrapped_separately; | |
| 2521 bool toc_is_wrapped_separately; | |
| 2522 } machine_function; | |
| 2523 #endif | |
| 2524 | |
| 2525 | |
| 111 | 2526 #define TARGET_SUPPORTS_WIDE_INT 1 |
| 2527 | |
| 2528 #if (GCC_VERSION >= 3000) | |
| 2529 #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128 | |
| 2530 #endif | |
| 145 | 2531 |
| 2532 /* Whether a given VALUE is a valid 16 or 34-bit signed integer. */ | |
| 2533 #define SIGNED_INTEGER_NBIT_P(VALUE, N) \ | |
| 2534 IN_RANGE ((VALUE), \ | |
| 2535 -(HOST_WIDE_INT_1 << ((N)-1)), \ | |
| 2536 (HOST_WIDE_INT_1 << ((N)-1)) - 1) | |
| 2537 | |
| 2538 #define SIGNED_INTEGER_16BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 16) | |
| 2539 #define SIGNED_INTEGER_34BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 34) | |
| 2540 | |
| 2541 /* Like SIGNED_INTEGER_16BIT_P and SIGNED_INTEGER_34BIT_P, but with an extra | |
| 2542 argument that gives a length to validate a range of addresses, to allow for | |
| 2543 splitting insns into several insns, each of which has an offsettable | |
| 2544 address. */ | |
| 2545 #define SIGNED_16BIT_OFFSET_EXTRA_P(VALUE, EXTRA) \ | |
| 2546 IN_RANGE ((VALUE), \ | |
| 2547 -(HOST_WIDE_INT_1 << 15), \ | |
| 2548 (HOST_WIDE_INT_1 << 15) - 1 - (EXTRA)) | |
| 2549 | |
| 2550 #define SIGNED_34BIT_OFFSET_EXTRA_P(VALUE, EXTRA) \ | |
| 2551 IN_RANGE ((VALUE), \ | |
| 2552 -(HOST_WIDE_INT_1 << 33), \ | |
| 2553 (HOST_WIDE_INT_1 << 33) - 1 - (EXTRA)) | |
| 2554 | |
| 2555 /* Define this if some processing needs to be done before outputting the | |
| 2556 assembler code. On the PowerPC, we remember if the current insn is a normal | |
| 2557 prefixed insn where we need to emit a 'p' before the insn. */ | |
| 2558 #define FINAL_PRESCAN_INSN(INSN, OPERANDS, NOPERANDS) \ | |
| 2559 do \ | |
| 2560 { \ | |
| 2561 if (TARGET_PREFIXED) \ | |
| 2562 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS); \ | |
| 2563 } \ | |
| 2564 while (0) | |
| 2565 | |
| 2566 /* Do anything special before emitting an opcode. We use it to emit a 'p' for | |
| 2567 prefixed insns that is set in FINAL_PRESCAN_INSN. */ | |
| 2568 #define ASM_OUTPUT_OPCODE(STREAM, OPCODE) \ | |
| 2569 do \ | |
| 2570 { \ | |
| 2571 if (TARGET_PREFIXED) \ | |
| 2572 rs6000_asm_output_opcode (STREAM); \ | |
| 2573 } \ | |
| 2574 while (0) |