Mercurial > hg > Members > kono > os9 > sbc09
annotate engine.c @ 9:cb7aa75418b8
mmu and io
author | Shinji KONO <kono@ie.u-ryukyu.ac.jp> |
---|---|
date | Thu, 05 Jul 2018 16:00:19 +0900 |
parents | a6db579d8c11 |
children | 2a1338b218bf |
rev | line source |
---|---|
0 | 1 /* 6809 Simulator V09. |
2 | |
3 created 1994,1995 by L.C. Benschop. | |
4 copyleft (c) 1994-2014 by the sbc09 team, see AUTHORS for more details. | |
5 license: GNU General Public License version 2, see LICENSE for more details. | |
6 | |
7 This program simulates a 6809 processor. | |
8 | |
9 System dependencies: short must be 16 bits. | |
10 char must be 8 bits. | |
11 long must be more than 16 bits. | |
12 arrays up to 65536 bytes must be supported. | |
13 machine must be twos complement. | |
14 Most Unix machines will work. For MSODS you need long pointers | |
15 and you may have to malloc() the mem array of 65536 bytes. | |
16 | |
17 Special instructions: | |
18 SWI2 writes char to stdout from register B. | |
19 SWI3 reads char from stdout to register B, sets carry at EOF. | |
20 (or when no key available when using term control). | |
21 SWI retains its normal function. | |
22 CWAI and SYNC stop simulator. | |
23 Note: special instructions are gone for now. | |
24 | |
25 ACIA emulation at port $E000 | |
26 | |
27 Note: BIG_ENDIAN option is no longer needed. | |
28 */ | |
29 | |
30 #include <stdio.h> | |
31 #include <unistd.h> | |
32 | |
33 #define engine | |
34 #include "v09.h" | |
35 | |
36 #define USLEEP 1000 | |
37 Byte aca,acb; | |
38 Byte *breg=&aca,*areg=&acb; | |
39 static int tracetrick=0; | |
9 | 40 extern long romstart; |
0 | 41 |
4 | 42 #ifdef USE_MMU |
9 | 43 static inline Byte * mem0(Byte *iphymem, Word adr, Byte *immu) { |
44 if (adr>=0xff00) return iphymem + memsize - 0x10000 + adr; // fixed area | |
45 return & iphymem[ ( immu[ (adr) >> 13 ] <<13 ) + ((adr) & 0x1fff )]; | |
46 }; | |
5 | 47 #define mem(adr) (*mem0(iphymem, adr,immu)) |
9 | 48 #define GETWORD(a) ({Byte *phy = mem0(iphymem, a,immu); phy[0]<<8|phy[1];}) |
49 #define SETBYTE(a,n) {Byte *phy = mem0(iphymem, a,immu); if(!(phy-iphymem>=romstart)) phy[0]=n;} | |
50 #define SETWORD(a,n) {Byte *phy = mem0(iphymem, a,immu); if(!(phy-iphymem>=romstart)){phy[0]=(n)>>8;phy[1]=n;}} | |
51 | |
52 Byte * mem1(Byte *iphymem, Word adr, Byte *immu) { return mem0(iphymem,adr,immu); } | |
53 | |
4 | 54 #else |
9 | 55 |
4 | 56 #define mem(adr) mem[adr] |
57 | |
58 #define GETWORD(a) (mem(a)<<8|mem((a)+1)) | |
59 #define SETBYTE(a,n) {if(!(a>=romstart))mem(a)=n;} | |
60 #define SETWORD(a,n) if(!(a>=romstart)){mem(a)=(n)>>8;mem((a)+1)=n;} | |
9 | 61 |
62 #endif | |
63 | |
0 | 64 /* Two bytes of a word are fetched separately because of |
65 the possible wrap-around at address $ffff and alignment | |
66 */ | |
67 | |
4 | 68 #define IMMBYTE(b) b=mem(ipcreg++); |
0 | 69 #define IMMWORD(w) {w=GETWORD(ipcreg);ipcreg+=2;} |
70 | |
71 #define PUSHBYTE(b) {--isreg;SETBYTE(isreg,b)} | |
72 #define PUSHWORD(w) {isreg-=2;SETWORD(isreg,w)} | |
4 | 73 #define PULLBYTE(b) b=mem(isreg++); |
0 | 74 #define PULLWORD(w) {w=GETWORD(isreg);isreg+=2;} |
75 #define PSHUBYTE(b) {--iureg;SETBYTE(iureg,b)} | |
76 #define PSHUWORD(w) {iureg-=2;SETWORD(iureg,w)} | |
4 | 77 #define PULUBYTE(b) b=mem(iureg++); |
0 | 78 #define PULUWORD(w) {w=GETWORD(iureg);iureg+=2;} |
79 | |
80 #define SIGNED(b) ((Word)(b&0x80?b|0xff00:b)) | |
81 | |
82 #define GETDREG ((iareg<<8)|ibreg) | |
83 #define SETDREG(n) {iareg=(n)>>8;ibreg=(n);} | |
84 | |
85 /* Macros for addressing modes (postbytes have their own code) */ | |
86 #define DIRECT {IMMBYTE(eaddr) eaddr|=(idpreg<<8);} | |
87 #define IMM8 {eaddr=ipcreg++;} | |
88 #define IMM16 {eaddr=ipcreg;ipcreg+=2;} | |
89 #define EXTENDED {IMMWORD(eaddr)} | |
90 | |
91 /* macros to set status flags */ | |
92 #define SEC iccreg|=0x01; | |
93 #define CLC iccreg&=0xfe; | |
94 #define SEZ iccreg|=0x04; | |
95 #define CLZ iccreg&=0xfb; | |
96 #define SEN iccreg|=0x08; | |
97 #define CLN iccreg&=0xf7; | |
98 #define SEV iccreg|=0x02; | |
99 #define CLV iccreg&=0xfd; | |
100 #define SEH iccreg|=0x20; | |
101 #define CLH iccreg&=0xdf; | |
102 | |
103 /* set N and Z flags depending on 8 or 16 bit result */ | |
104 #define SETNZ8(b) {if(b)CLZ else SEZ if(b&0x80)SEN else CLN} | |
105 #define SETNZ16(b) {if(b)CLZ else SEZ if(b&0x8000)SEN else CLN} | |
106 | |
107 #define SETSTATUS(a,b,res) if((a^b^res)&0x10) SEH else CLH \ | |
108 if((a^b^res^(res>>1))&0x80)SEV else CLV \ | |
109 if(res&0x100)SEC else CLC SETNZ8((Byte)res) | |
110 | |
111 #define SETSTATUSD(a,b,res) {if(res&0x10000) SEC else CLC \ | |
112 if(((res>>1)^a^b^res)&0x8000) SEV else CLV \ | |
113 SETNZ16((Word)res)} | |
114 | |
115 /* Macros for branch instructions */ | |
116 #define BRANCH(f) if(!iflag){IMMBYTE(tb) if(f)ipcreg+=SIGNED(tb);}\ | |
117 else{IMMWORD(tw) if(f)ipcreg+=tw;} | |
118 #define NXORV ((iccreg&0x08)^((iccreg&0x02)<<2)) | |
119 | |
120 /* MAcros for setting/getting registers in TFR/EXG instructions */ | |
121 #define GETREG(val,reg) switch(reg) {\ | |
122 case 0: val=GETDREG;break;\ | |
123 case 1: val=ixreg;break;\ | |
124 case 2: val=iyreg;break;\ | |
125 case 3: val=iureg;break;\ | |
126 case 4: val=isreg;break;\ | |
127 case 5: val=ipcreg;break;\ | |
128 case 8: val=iareg;break;\ | |
129 case 9: val=ibreg;break;\ | |
130 case 10: val=iccreg;break;\ | |
131 case 11: val=idpreg;break;} | |
132 | |
133 #define SETREG(val,reg) switch(reg) {\ | |
134 case 0: SETDREG(val) break;\ | |
135 case 1: ixreg=val;break;\ | |
136 case 2: iyreg=val;break;\ | |
137 case 3: iureg=val;break;\ | |
138 case 4: isreg=val;break;\ | |
139 case 5: ipcreg=val;break;\ | |
140 case 8: iareg=val;break;\ | |
141 case 9: ibreg=val;break;\ | |
142 case 10: iccreg=val;break;\ | |
143 case 11: idpreg=val;break;} | |
144 | |
145 /* Macros for load and store of accumulators. Can be modified to check | |
146 for port addresses */ | |
7
a6db579d8c11
level 2 rom preparing...
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents:
5
diff
changeset
|
147 #define LOADAC(reg) if((eaddr&0xff00)!=(IOPAGE&0xff00))reg=mem(eaddr);else\ |
0 | 148 reg=do_input(eaddr&0xff); |
7
a6db579d8c11
level 2 rom preparing...
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents:
5
diff
changeset
|
149 #define STOREAC(reg) if((eaddr&0xff00)!=(IOPAGE&0xff00))SETBYTE(eaddr,reg)else\ |
0 | 150 do_output(eaddr&0xff,reg); |
151 | |
152 #define LOADREGS ixreg=xreg;iyreg=yreg;\ | |
153 iureg=ureg;isreg=sreg;\ | |
154 ipcreg=pcreg;\ | |
155 iareg=*areg;ibreg=*breg;\ | |
4 | 156 idpreg=dpreg;iccreg=ccreg;immu=mmu; |
0 | 157 |
158 #define SAVEREGS xreg=ixreg;yreg=iyreg;\ | |
159 ureg=iureg;sreg=isreg;\ | |
160 pcreg=ipcreg;\ | |
161 *areg=iareg;*breg=ibreg;\ | |
4 | 162 dpreg=idpreg;ccreg=iccreg;mmu=immu; |
0 | 163 |
164 | |
165 unsigned char haspostbyte[] = { | |
166 /*0*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
167 /*1*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
168 /*2*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
169 /*3*/ 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0, | |
170 /*4*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
171 /*5*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
172 /*6*/ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, | |
173 /*7*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
174 /*8*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
175 /*9*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
176 /*A*/ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, | |
177 /*B*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
178 /*C*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
179 /*D*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
180 /*E*/ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, | |
181 /*F*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
182 }; | |
183 | |
9 | 184 extern char *prog ; |
185 | |
0 | 186 void interpr(void) |
187 { | |
188 Word ixreg,iyreg,iureg,isreg,ipcreg; | |
189 Byte idpreg,iccreg,iareg,ibreg; | |
190 /* Make local variables for the registers. On a real processor (non-Intel) | |
191 these could be implemented as fast registers. */ | |
192 Word eaddr; /* effective address */ | |
193 Byte ireg; /* instruction register */ | |
194 Byte iflag; /* flag to indicate $10 or $11 prebyte */ | |
195 Byte tb;Word tw; | |
4 | 196 Byte *immu = 0; |
197 #ifdef USE_MMU | |
198 const int imemsize = memsize; | |
199 Byte *iphymem = (Byte *)phymem; | |
200 immu = iphymem + imemsize - 0x10000 + 0xffa0; | |
201 #endif | |
0 | 202 LOADREGS |
203 for(;;){ | |
204 if(attention) { | |
9 | 205 if(tracing && ipcreg>=tracelo && ipcreg<=tracehi) { |
206 SAVEREGS | |
207 #ifdef USE_MMU | |
208 Byte *phyadr = &mem(pcreg); | |
209 prog = (char *)(phyadr - pcreg); | |
210 #endif | |
211 do_trace(tracefile); | |
212 } | |
0 | 213 if(escape){ SAVEREGS do_escape(); LOADREGS } |
214 if(irq) { | |
215 if(irq==1&&!(iccreg&0x10)) { /* standard IRQ */ | |
216 PUSHWORD(ipcreg) | |
217 PUSHWORD(iureg) | |
218 PUSHWORD(iyreg) | |
219 PUSHWORD(ixreg) | |
220 PUSHBYTE(idpreg) | |
221 PUSHBYTE(ibreg) | |
222 PUSHBYTE(iareg) | |
223 PUSHBYTE(iccreg) | |
224 iccreg|=0x90; | |
225 ipcreg=GETWORD(0xfff8); | |
226 } | |
227 if(irq==2&&!(iccreg&0x40)) { /* Fast IRQ */ | |
228 PUSHWORD(ipcreg) | |
229 PUSHBYTE(iccreg) | |
230 iccreg&=0x7f; | |
231 iccreg|=0x50; | |
232 ipcreg=GETWORD(0xfff6); | |
233 } | |
234 if(!tracing)attention=0; | |
235 irq=0; | |
236 } | |
237 } | |
238 iflag=0; | |
239 flaginstr: /* $10 and $11 instructions return here */ | |
4 | 240 ireg=mem(ipcreg++); |
0 | 241 if(haspostbyte[ireg]) { |
4 | 242 Byte postbyte=mem(ipcreg++); |
0 | 243 switch(postbyte) { |
244 case 0x00: eaddr=ixreg;break; | |
245 case 0x01: eaddr=ixreg+1;break; | |
246 case 0x02: eaddr=ixreg+2;break; | |
247 case 0x03: eaddr=ixreg+3;break; | |
248 case 0x04: eaddr=ixreg+4;break; | |
249 case 0x05: eaddr=ixreg+5;break; | |
250 case 0x06: eaddr=ixreg+6;break; | |
251 case 0x07: eaddr=ixreg+7;break; | |
252 case 0x08: eaddr=ixreg+8;break; | |
253 case 0x09: eaddr=ixreg+9;break; | |
254 case 0x0A: eaddr=ixreg+10;break; | |
255 case 0x0B: eaddr=ixreg+11;break; | |
256 case 0x0C: eaddr=ixreg+12;break; | |
257 case 0x0D: eaddr=ixreg+13;break; | |
258 case 0x0E: eaddr=ixreg+14;break; | |
259 case 0x0F: eaddr=ixreg+15;break; | |
260 case 0x10: eaddr=ixreg-16;break; | |
261 case 0x11: eaddr=ixreg-15;break; | |
262 case 0x12: eaddr=ixreg-14;break; | |
263 case 0x13: eaddr=ixreg-13;break; | |
264 case 0x14: eaddr=ixreg-12;break; | |
265 case 0x15: eaddr=ixreg-11;break; | |
266 case 0x16: eaddr=ixreg-10;break; | |
267 case 0x17: eaddr=ixreg-9;break; | |
268 case 0x18: eaddr=ixreg-8;break; | |
269 case 0x19: eaddr=ixreg-7;break; | |
270 case 0x1A: eaddr=ixreg-6;break; | |
271 case 0x1B: eaddr=ixreg-5;break; | |
272 case 0x1C: eaddr=ixreg-4;break; | |
273 case 0x1D: eaddr=ixreg-3;break; | |
274 case 0x1E: eaddr=ixreg-2;break; | |
275 case 0x1F: eaddr=ixreg-1;break; | |
276 case 0x20: eaddr=iyreg;break; | |
277 case 0x21: eaddr=iyreg+1;break; | |
278 case 0x22: eaddr=iyreg+2;break; | |
279 case 0x23: eaddr=iyreg+3;break; | |
280 case 0x24: eaddr=iyreg+4;break; | |
281 case 0x25: eaddr=iyreg+5;break; | |
282 case 0x26: eaddr=iyreg+6;break; | |
283 case 0x27: eaddr=iyreg+7;break; | |
284 case 0x28: eaddr=iyreg+8;break; | |
285 case 0x29: eaddr=iyreg+9;break; | |
286 case 0x2A: eaddr=iyreg+10;break; | |
287 case 0x2B: eaddr=iyreg+11;break; | |
288 case 0x2C: eaddr=iyreg+12;break; | |
289 case 0x2D: eaddr=iyreg+13;break; | |
290 case 0x2E: eaddr=iyreg+14;break; | |
291 case 0x2F: eaddr=iyreg+15;break; | |
292 case 0x30: eaddr=iyreg-16;break; | |
293 case 0x31: eaddr=iyreg-15;break; | |
294 case 0x32: eaddr=iyreg-14;break; | |
295 case 0x33: eaddr=iyreg-13;break; | |
296 case 0x34: eaddr=iyreg-12;break; | |
297 case 0x35: eaddr=iyreg-11;break; | |
298 case 0x36: eaddr=iyreg-10;break; | |
299 case 0x37: eaddr=iyreg-9;break; | |
300 case 0x38: eaddr=iyreg-8;break; | |
301 case 0x39: eaddr=iyreg-7;break; | |
302 case 0x3A: eaddr=iyreg-6;break; | |
303 case 0x3B: eaddr=iyreg-5;break; | |
304 case 0x3C: eaddr=iyreg-4;break; | |
305 case 0x3D: eaddr=iyreg-3;break; | |
306 case 0x3E: eaddr=iyreg-2;break; | |
307 case 0x3F: eaddr=iyreg-1;break; | |
308 case 0x40: eaddr=iureg;break; | |
309 case 0x41: eaddr=iureg+1;break; | |
310 case 0x42: eaddr=iureg+2;break; | |
311 case 0x43: eaddr=iureg+3;break; | |
312 case 0x44: eaddr=iureg+4;break; | |
313 case 0x45: eaddr=iureg+5;break; | |
314 case 0x46: eaddr=iureg+6;break; | |
315 case 0x47: eaddr=iureg+7;break; | |
316 case 0x48: eaddr=iureg+8;break; | |
317 case 0x49: eaddr=iureg+9;break; | |
318 case 0x4A: eaddr=iureg+10;break; | |
319 case 0x4B: eaddr=iureg+11;break; | |
320 case 0x4C: eaddr=iureg+12;break; | |
321 case 0x4D: eaddr=iureg+13;break; | |
322 case 0x4E: eaddr=iureg+14;break; | |
323 case 0x4F: eaddr=iureg+15;break; | |
324 case 0x50: eaddr=iureg-16;break; | |
325 case 0x51: eaddr=iureg-15;break; | |
326 case 0x52: eaddr=iureg-14;break; | |
327 case 0x53: eaddr=iureg-13;break; | |
328 case 0x54: eaddr=iureg-12;break; | |
329 case 0x55: eaddr=iureg-11;break; | |
330 case 0x56: eaddr=iureg-10;break; | |
331 case 0x57: eaddr=iureg-9;break; | |
332 case 0x58: eaddr=iureg-8;break; | |
333 case 0x59: eaddr=iureg-7;break; | |
334 case 0x5A: eaddr=iureg-6;break; | |
335 case 0x5B: eaddr=iureg-5;break; | |
336 case 0x5C: eaddr=iureg-4;break; | |
337 case 0x5D: eaddr=iureg-3;break; | |
338 case 0x5E: eaddr=iureg-2;break; | |
339 case 0x5F: eaddr=iureg-1;break; | |
340 case 0x60: eaddr=isreg;break; | |
341 case 0x61: eaddr=isreg+1;break; | |
342 case 0x62: eaddr=isreg+2;break; | |
343 case 0x63: eaddr=isreg+3;break; | |
344 case 0x64: eaddr=isreg+4;break; | |
345 case 0x65: eaddr=isreg+5;break; | |
346 case 0x66: eaddr=isreg+6;break; | |
347 case 0x67: eaddr=isreg+7;break; | |
348 case 0x68: eaddr=isreg+8;break; | |
349 case 0x69: eaddr=isreg+9;break; | |
350 case 0x6A: eaddr=isreg+10;break; | |
351 case 0x6B: eaddr=isreg+11;break; | |
352 case 0x6C: eaddr=isreg+12;break; | |
353 case 0x6D: eaddr=isreg+13;break; | |
354 case 0x6E: eaddr=isreg+14;break; | |
355 case 0x6F: eaddr=isreg+15;break; | |
356 case 0x70: eaddr=isreg-16;break; | |
357 case 0x71: eaddr=isreg-15;break; | |
358 case 0x72: eaddr=isreg-14;break; | |
359 case 0x73: eaddr=isreg-13;break; | |
360 case 0x74: eaddr=isreg-12;break; | |
361 case 0x75: eaddr=isreg-11;break; | |
362 case 0x76: eaddr=isreg-10;break; | |
363 case 0x77: eaddr=isreg-9;break; | |
364 case 0x78: eaddr=isreg-8;break; | |
365 case 0x79: eaddr=isreg-7;break; | |
366 case 0x7A: eaddr=isreg-6;break; | |
367 case 0x7B: eaddr=isreg-5;break; | |
368 case 0x7C: eaddr=isreg-4;break; | |
369 case 0x7D: eaddr=isreg-3;break; | |
370 case 0x7E: eaddr=isreg-2;break; | |
371 case 0x7F: eaddr=isreg-1;break; | |
372 case 0x80: eaddr=ixreg;ixreg++;break; | |
373 case 0x81: eaddr=ixreg;ixreg+=2;break; | |
374 case 0x82: ixreg--;eaddr=ixreg;break; | |
375 case 0x83: ixreg-=2;eaddr=ixreg;break; | |
376 case 0x84: eaddr=ixreg;break; | |
377 case 0x85: eaddr=ixreg+SIGNED(ibreg);break; | |
378 case 0x86: eaddr=ixreg+SIGNED(iareg);break; | |
379 case 0x87: eaddr=0;break; /*ILELGAL*/ | |
380 case 0x88: IMMBYTE(eaddr);eaddr=ixreg+SIGNED(eaddr);break; | |
381 case 0x89: IMMWORD(eaddr);eaddr+=ixreg;break; | |
382 case 0x8A: eaddr=0;break; /*ILLEGAL*/ | |
383 case 0x8B: eaddr=ixreg+GETDREG;break; | |
384 case 0x8C: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break; | |
385 case 0x8D: IMMWORD(eaddr);eaddr+=ipcreg;break; | |
386 case 0x8E: eaddr=0;break; /*ILLEGAL*/ | |
387 case 0x8F: IMMWORD(eaddr);break; | |
388 case 0x90: eaddr=ixreg;ixreg++;eaddr=GETWORD(eaddr);break; | |
389 case 0x91: eaddr=ixreg;ixreg+=2;eaddr=GETWORD(eaddr);break; | |
390 case 0x92: ixreg--;eaddr=ixreg;eaddr=GETWORD(eaddr);break; | |
391 case 0x93: ixreg-=2;eaddr=ixreg;eaddr=GETWORD(eaddr);break; | |
392 case 0x94: eaddr=ixreg;eaddr=GETWORD(eaddr);break; | |
393 case 0x95: eaddr=ixreg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break; | |
394 case 0x96: eaddr=ixreg+SIGNED(iareg);eaddr=GETWORD(eaddr);break; | |
395 case 0x97: eaddr=0;break; /*ILELGAL*/ | |
396 case 0x98: IMMBYTE(eaddr);eaddr=ixreg+SIGNED(eaddr); | |
397 eaddr=GETWORD(eaddr);break; | |
398 case 0x99: IMMWORD(eaddr);eaddr+=ixreg;eaddr=GETWORD(eaddr);break; | |
399 case 0x9A: eaddr=0;break; /*ILLEGAL*/ | |
400 case 0x9B: eaddr=ixreg+GETDREG;eaddr=GETWORD(eaddr);break; | |
401 case 0x9C: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr); | |
402 eaddr=GETWORD(eaddr);break; | |
403 case 0x9D: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break; | |
404 case 0x9E: eaddr=0;break; /*ILLEGAL*/ | |
405 case 0x9F: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break; | |
406 case 0xA0: eaddr=iyreg;iyreg++;break; | |
407 case 0xA1: eaddr=iyreg;iyreg+=2;break; | |
408 case 0xA2: iyreg--;eaddr=iyreg;break; | |
409 case 0xA3: iyreg-=2;eaddr=iyreg;break; | |
410 case 0xA4: eaddr=iyreg;break; | |
411 case 0xA5: eaddr=iyreg+SIGNED(ibreg);break; | |
412 case 0xA6: eaddr=iyreg+SIGNED(iareg);break; | |
413 case 0xA7: eaddr=0;break; /*ILELGAL*/ | |
414 case 0xA8: IMMBYTE(eaddr);eaddr=iyreg+SIGNED(eaddr);break; | |
415 case 0xA9: IMMWORD(eaddr);eaddr+=iyreg;break; | |
416 case 0xAA: eaddr=0;break; /*ILLEGAL*/ | |
417 case 0xAB: eaddr=iyreg+GETDREG;break; | |
418 case 0xAC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break; | |
419 case 0xAD: IMMWORD(eaddr);eaddr+=ipcreg;break; | |
420 case 0xAE: eaddr=0;break; /*ILLEGAL*/ | |
421 case 0xAF: IMMWORD(eaddr);break; | |
422 case 0xB0: eaddr=iyreg;iyreg++;eaddr=GETWORD(eaddr);break; | |
423 case 0xB1: eaddr=iyreg;iyreg+=2;eaddr=GETWORD(eaddr);break; | |
424 case 0xB2: iyreg--;eaddr=iyreg;eaddr=GETWORD(eaddr);break; | |
425 case 0xB3: iyreg-=2;eaddr=iyreg;eaddr=GETWORD(eaddr);break; | |
426 case 0xB4: eaddr=iyreg;eaddr=GETWORD(eaddr);break; | |
427 case 0xB5: eaddr=iyreg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break; | |
428 case 0xB6: eaddr=iyreg+SIGNED(iareg);eaddr=GETWORD(eaddr);break; | |
429 case 0xB7: eaddr=0;break; /*ILELGAL*/ | |
430 case 0xB8: IMMBYTE(eaddr);eaddr=iyreg+SIGNED(eaddr); | |
431 eaddr=GETWORD(eaddr);break; | |
432 case 0xB9: IMMWORD(eaddr);eaddr+=iyreg;eaddr=GETWORD(eaddr);break; | |
433 case 0xBA: eaddr=0;break; /*ILLEGAL*/ | |
434 case 0xBB: eaddr=iyreg+GETDREG;eaddr=GETWORD(eaddr);break; | |
435 case 0xBC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr); | |
436 eaddr=GETWORD(eaddr);break; | |
437 case 0xBD: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break; | |
438 case 0xBE: eaddr=0;break; /*ILLEGAL*/ | |
439 case 0xBF: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break; | |
440 case 0xC0: eaddr=iureg;iureg++;break; | |
441 case 0xC1: eaddr=iureg;iureg+=2;break; | |
442 case 0xC2: iureg--;eaddr=iureg;break; | |
443 case 0xC3: iureg-=2;eaddr=iureg;break; | |
444 case 0xC4: eaddr=iureg;break; | |
445 case 0xC5: eaddr=iureg+SIGNED(ibreg);break; | |
446 case 0xC6: eaddr=iureg+SIGNED(iareg);break; | |
447 case 0xC7: eaddr=0;break; /*ILELGAL*/ | |
448 case 0xC8: IMMBYTE(eaddr);eaddr=iureg+SIGNED(eaddr);break; | |
449 case 0xC9: IMMWORD(eaddr);eaddr+=iureg;break; | |
450 case 0xCA: eaddr=0;break; /*ILLEGAL*/ | |
451 case 0xCB: eaddr=iureg+GETDREG;break; | |
452 case 0xCC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break; | |
453 case 0xCD: IMMWORD(eaddr);eaddr+=ipcreg;break; | |
454 case 0xCE: eaddr=0;break; /*ILLEGAL*/ | |
455 case 0xCF: IMMWORD(eaddr);break; | |
456 case 0xD0: eaddr=iureg;iureg++;eaddr=GETWORD(eaddr);break; | |
457 case 0xD1: eaddr=iureg;iureg+=2;eaddr=GETWORD(eaddr);break; | |
458 case 0xD2: iureg--;eaddr=iureg;eaddr=GETWORD(eaddr);break; | |
459 case 0xD3: iureg-=2;eaddr=iureg;eaddr=GETWORD(eaddr);break; | |
460 case 0xD4: eaddr=iureg;eaddr=GETWORD(eaddr);break; | |
461 case 0xD5: eaddr=iureg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break; | |
462 case 0xD6: eaddr=iureg+SIGNED(iareg);eaddr=GETWORD(eaddr);break; | |
463 case 0xD7: eaddr=0;break; /*ILELGAL*/ | |
464 case 0xD8: IMMBYTE(eaddr);eaddr=iureg+SIGNED(eaddr); | |
465 eaddr=GETWORD(eaddr);break; | |
466 case 0xD9: IMMWORD(eaddr);eaddr+=iureg;eaddr=GETWORD(eaddr);break; | |
467 case 0xDA: eaddr=0;break; /*ILLEGAL*/ | |
468 case 0xDB: eaddr=iureg+GETDREG;eaddr=GETWORD(eaddr);break; | |
469 case 0xDC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr); | |
470 eaddr=GETWORD(eaddr);break; | |
471 case 0xDD: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break; | |
472 case 0xDE: eaddr=0;break; /*ILLEGAL*/ | |
473 case 0xDF: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break; | |
474 case 0xE0: eaddr=isreg;isreg++;break; | |
475 case 0xE1: eaddr=isreg;isreg+=2;break; | |
476 case 0xE2: isreg--;eaddr=isreg;break; | |
477 case 0xE3: isreg-=2;eaddr=isreg;break; | |
478 case 0xE4: eaddr=isreg;break; | |
479 case 0xE5: eaddr=isreg+SIGNED(ibreg);break; | |
480 case 0xE6: eaddr=isreg+SIGNED(iareg);break; | |
481 case 0xE7: eaddr=0;break; /*ILELGAL*/ | |
482 case 0xE8: IMMBYTE(eaddr);eaddr=isreg+SIGNED(eaddr);break; | |
483 case 0xE9: IMMWORD(eaddr);eaddr+=isreg;break; | |
484 case 0xEA: eaddr=0;break; /*ILLEGAL*/ | |
485 case 0xEB: eaddr=isreg+GETDREG;break; | |
486 case 0xEC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break; | |
487 case 0xED: IMMWORD(eaddr);eaddr+=ipcreg;break; | |
488 case 0xEE: eaddr=0;break; /*ILLEGAL*/ | |
489 case 0xEF: IMMWORD(eaddr);break; | |
490 case 0xF0: eaddr=isreg;isreg++;eaddr=GETWORD(eaddr);break; | |
491 case 0xF1: eaddr=isreg;isreg+=2;eaddr=GETWORD(eaddr);break; | |
492 case 0xF2: isreg--;eaddr=isreg;eaddr=GETWORD(eaddr);break; | |
493 case 0xF3: isreg-=2;eaddr=isreg;eaddr=GETWORD(eaddr);break; | |
494 case 0xF4: eaddr=isreg;eaddr=GETWORD(eaddr);break; | |
495 case 0xF5: eaddr=isreg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break; | |
496 case 0xF6: eaddr=isreg+SIGNED(iareg);eaddr=GETWORD(eaddr);break; | |
497 case 0xF7: eaddr=0;break; /*ILELGAL*/ | |
498 case 0xF8: IMMBYTE(eaddr);eaddr=isreg+SIGNED(eaddr); | |
499 eaddr=GETWORD(eaddr);break; | |
500 case 0xF9: IMMWORD(eaddr);eaddr+=isreg;eaddr=GETWORD(eaddr);break; | |
501 case 0xFA: eaddr=0;break; /*ILLEGAL*/ | |
502 case 0xFB: eaddr=isreg+GETDREG;eaddr=GETWORD(eaddr);break; | |
503 case 0xFC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr); | |
504 eaddr=GETWORD(eaddr);break; | |
505 case 0xFD: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break; | |
506 case 0xFE: eaddr=0;break; /*ILLEGAL*/ | |
507 case 0xFF: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break; | |
508 } | |
509 } | |
510 switch(ireg) { | |
4 | 511 case 0x00: /*NEG direct*/ DIRECT tw=-mem(eaddr);SETSTATUS(0,mem(eaddr),tw) |
0 | 512 SETBYTE(eaddr,tw)break; |
513 case 0x01: break;/*ILLEGAL*/ | |
514 case 0x02: break;/*ILLEGAL*/ | |
4 | 515 case 0x03: /*COM direct*/ DIRECT tb=~mem(eaddr);SETNZ8(tb);SEC CLV |
0 | 516 SETBYTE(eaddr,tb)break; |
4 | 517 case 0x04: /*LSR direct*/ DIRECT tb=mem(eaddr);if(tb&0x01)SEC else CLC |
0 | 518 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb) |
519 SETBYTE(eaddr,tb)break; | |
520 case 0x05: break;/* ILLEGAL*/ | |
521 case 0x06: /*ROR direct*/ DIRECT tb=(iccreg&0x01)<<7; | |
4 | 522 if(mem(eaddr)&0x01)SEC else CLC |
523 tw=(mem(eaddr)>>1)+tb;SETNZ8(tw) | |
0 | 524 SETBYTE(eaddr,tw) |
525 break; | |
4 | 526 case 0x07: /*ASR direct*/ DIRECT tb=mem(eaddr);if(tb&0x01)SEC else CLC |
0 | 527 if(tb&0x10)SEH else CLH tb>>=1; |
528 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb) | |
529 break; | |
4 | 530 case 0x08: /*ASL direct*/ DIRECT tw=mem(eaddr)<<1; |
531 SETSTATUS(mem(eaddr),mem(eaddr),tw) | |
0 | 532 SETBYTE(eaddr,tw)break; |
4 | 533 case 0x09: /*ROL direct*/ DIRECT tb=mem(eaddr);tw=iccreg&0x01; |
0 | 534 if(tb&0x80)SEC else CLC |
535 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV | |
536 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break; | |
4 | 537 case 0x0A: /*DEC direct*/ DIRECT tb=mem(eaddr)-1;if(tb==0x7F)SEV else CLV |
0 | 538 SETNZ8(tb) SETBYTE(eaddr,tb)break; |
539 case 0x0B: break; /*ILLEGAL*/ | |
4 | 540 case 0x0C: /*INC direct*/ DIRECT tb=mem(eaddr)+1;if(tb==0x80)SEV else CLV |
0 | 541 SETNZ8(tb) SETBYTE(eaddr,tb)break; |
4 | 542 case 0x0D: /*TST direct*/ DIRECT tb=mem(eaddr);SETNZ8(tb) break; |
0 | 543 case 0x0E: /*JMP direct*/ DIRECT ipcreg=eaddr;break; |
544 case 0x0F: /*CLR direct*/ DIRECT SETBYTE(eaddr,0);CLN CLV SEZ CLC break; | |
545 case 0x10: /* flag10 */ iflag=1;goto flaginstr; | |
546 case 0x11: /* flag11 */ iflag=2;goto flaginstr; | |
547 case 0x12: /* NOP */ break; | |
548 case 0x13: /* SYNC */ | |
549 do usleep(USLEEP); /* Wait for IRQ */ | |
550 while(!irq && !attention); | |
551 if(iccreg&0x40)tracetrick=1; | |
552 break; | |
553 case 0x14: break; /*ILLEGAL*/ | |
554 case 0x15: break; /*ILLEGAL*/ | |
555 case 0x16: /*LBRA*/ IMMWORD(eaddr) ipcreg+=eaddr;break; | |
556 case 0x17: /*LBSR*/ IMMWORD(eaddr) PUSHWORD(ipcreg) ipcreg+=eaddr;break; | |
557 case 0x18: break; /*ILLEGAL*/ | |
558 case 0x19: /* DAA*/ tw=iareg; | |
559 if(iccreg&0x20)tw+=6; | |
560 if((tw&0x0f)>9)tw+=6; | |
561 if(iccreg&0x01)tw+=0x60; | |
562 if((tw&0xf0)>0x90)tw+=0x60; | |
563 if(tw&0x100)SEC | |
564 iareg=tw;break; | |
565 case 0x1A: /* ORCC*/ IMMBYTE(tb) iccreg|=tb;break; | |
566 case 0x1B: break; /*ILLEGAL*/ | |
567 case 0x1C: /* ANDCC*/ IMMBYTE(tb) iccreg&=tb;break; | |
568 case 0x1D: /* SEX */ tw=SIGNED(ibreg); SETNZ16(tw) SETDREG(tw) break; | |
569 case 0x1E: /* EXG */ IMMBYTE(tb) {Word t2;GETREG(tw,tb>>4) GETREG(t2,tb&15) | |
570 SETREG(t2,tb>>4) SETREG(tw,tb&15) } break; | |
571 case 0x1F: /* TFR */ IMMBYTE(tb) GETREG(tw,tb>>4) SETREG(tw,tb&15) break; | |
572 case 0x20: /* (L)BRA*/ BRANCH(1) break; | |
573 case 0x21: /* (L)BRN*/ BRANCH(0) break; | |
574 case 0x22: /* (L)BHI*/ BRANCH(!(iccreg&0x05)) break; | |
575 case 0x23: /* (L)BLS*/ BRANCH(iccreg&0x05) break; | |
576 case 0x24: /* (L)BCC*/ BRANCH(!(iccreg&0x01)) break; | |
577 case 0x25: /* (L)BCS*/ BRANCH(iccreg&0x01) break; | |
578 case 0x26: /* (L)BNE*/ BRANCH(!(iccreg&0x04)) break; | |
579 case 0x27: /* (L)BEQ*/ BRANCH(iccreg&0x04) break; | |
580 case 0x28: /* (L)BVC*/ BRANCH(!(iccreg&0x02)) break; | |
581 case 0x29: /* (L)BVS*/ BRANCH(iccreg&0x02) break; | |
582 case 0x2A: /* (L)BPL*/ BRANCH(!(iccreg&0x08)) break; | |
583 case 0x2B: /* (L)BMI*/ BRANCH(iccreg&0x08) break; | |
584 case 0x2C: /* (L)BGE*/ BRANCH(!NXORV) break; | |
585 case 0x2D: /* (L)BLT*/ BRANCH(NXORV) break; | |
586 case 0x2E: /* (L)BGT*/ BRANCH(!(NXORV||iccreg&0x04)) break; | |
587 case 0x2F: /* (L)BLE*/ BRANCH(NXORV||iccreg&0x04) break; | |
588 case 0x30: /* LEAX*/ ixreg=eaddr; if(ixreg) CLZ else SEZ break; | |
589 case 0x31: /* LEAY*/ iyreg=eaddr; if(iyreg) CLZ else SEZ break; | |
590 case 0x32: /* LEAS*/ isreg=eaddr;break; | |
591 case 0x33: /* LEAU*/ iureg=eaddr;break; | |
592 case 0x34: /* PSHS*/ IMMBYTE(tb) | |
593 if(tb&0x80)PUSHWORD(ipcreg) | |
594 if(tb&0x40)PUSHWORD(iureg) | |
595 if(tb&0x20)PUSHWORD(iyreg) | |
596 if(tb&0x10)PUSHWORD(ixreg) | |
597 if(tb&0x08)PUSHBYTE(idpreg) | |
598 if(tb&0x04)PUSHBYTE(ibreg) | |
599 if(tb&0x02)PUSHBYTE(iareg) | |
600 if(tb&0x01)PUSHBYTE(iccreg) break; | |
601 case 0x35: /* PULS*/ IMMBYTE(tb) | |
602 if(tb&0x01)PULLBYTE(iccreg) | |
603 if(tb&0x02)PULLBYTE(iareg) | |
604 if(tb&0x04)PULLBYTE(ibreg) | |
605 if(tb&0x08)PULLBYTE(idpreg) | |
606 if(tb&0x10)PULLWORD(ixreg) | |
607 if(tb&0x20)PULLWORD(iyreg) | |
608 if(tb&0x40)PULLWORD(iureg) | |
609 if(tb&0x80)PULLWORD(ipcreg) | |
610 if(tracetrick&&tb==0xff) { /* Arrange fake FIRQ after next insn | |
611 for hardware tracing */ | |
612 tracetrick=0; | |
613 irq=2; | |
614 attention=1; | |
615 goto flaginstr; | |
616 } | |
617 break; | |
618 case 0x36: /* PSHU*/ IMMBYTE(tb) | |
619 if(tb&0x80)PSHUWORD(ipcreg) | |
620 if(tb&0x40)PSHUWORD(isreg) | |
621 if(tb&0x20)PSHUWORD(iyreg) | |
622 if(tb&0x10)PSHUWORD(ixreg) | |
623 if(tb&0x08)PSHUBYTE(idpreg) | |
624 if(tb&0x04)PSHUBYTE(ibreg) | |
625 if(tb&0x02)PSHUBYTE(iareg) | |
626 if(tb&0x01)PSHUBYTE(iccreg) break; | |
627 case 0x37: /* PULU*/ IMMBYTE(tb) | |
628 if(tb&0x01)PULUBYTE(iccreg) | |
629 if(tb&0x02)PULUBYTE(iareg) | |
630 if(tb&0x04)PULUBYTE(ibreg) | |
631 if(tb&0x08)PULUBYTE(idpreg) | |
632 if(tb&0x10)PULUWORD(ixreg) | |
633 if(tb&0x20)PULUWORD(iyreg) | |
634 if(tb&0x40)PULUWORD(isreg) | |
635 if(tb&0x80)PULUWORD(ipcreg) break; | |
636 case 0x39: /* RTS*/ PULLWORD(ipcreg) break; | |
637 case 0x3A: /* ABX*/ ixreg+=ibreg; break; | |
638 case 0x3B: /* RTI*/ tb=iccreg&0x80; | |
639 PULLBYTE(iccreg) | |
640 if(tb) | |
641 { | |
642 PULLBYTE(iareg) | |
643 PULLBYTE(ibreg) | |
644 PULLBYTE(idpreg) | |
645 PULLWORD(ixreg) | |
646 PULLWORD(iyreg) | |
647 PULLWORD(iureg) | |
648 } | |
649 PULLWORD(ipcreg) break; | |
650 case 0x3C: /* CWAI*/ IMMBYTE(tb) | |
651 PUSHWORD(ipcreg) | |
652 PUSHWORD(iureg) | |
653 PUSHWORD(iyreg) | |
654 PUSHWORD(ixreg) | |
655 PUSHBYTE(idpreg) | |
656 PUSHBYTE(ibreg) | |
657 PUSHBYTE(iareg) | |
658 PUSHBYTE(iccreg) | |
659 iccreg&=tb; | |
660 iccreg|=0x80; | |
661 do usleep(USLEEP); /* Wait for IRQ */ | |
662 while(!attention && !((irq==1&&!(iccreg&0x10))||(irq==2&&!(iccreg&0x040)))); | |
663 if(irq==1)ipcreg=GETWORD(0xfff8); | |
664 else ipcreg=GETWORD(0xfff6); | |
665 irq=0; | |
666 if(!tracing)attention=0; | |
667 break; | |
668 case 0x3D: /* MUL*/ tw=iareg*ibreg; if(tw)CLZ else SEZ | |
669 if(tw&0x80) SEC else CLC SETDREG(tw) break; | |
670 case 0x3E: break; /*ILLEGAL*/ | |
671 case 0x3F: /* SWI (SWI2 SWI3)*/ { | |
672 PUSHWORD(ipcreg) | |
673 PUSHWORD(iureg) | |
674 PUSHWORD(iyreg) | |
675 PUSHWORD(ixreg) | |
676 PUSHBYTE(idpreg) | |
677 PUSHBYTE(ibreg) | |
678 PUSHBYTE(iareg) | |
679 PUSHBYTE(iccreg) | |
680 iccreg|=0x80; | |
681 if(!iflag)iccreg|=0x50; | |
682 switch(iflag) { | |
683 case 0:ipcreg=GETWORD(0xfffa);break; | |
684 case 1:ipcreg=GETWORD(0xfff4);break; | |
685 case 2:ipcreg=GETWORD(0xfff2);break; | |
686 } | |
687 }break; | |
688 case 0x40: /*NEGA*/ tw=-iareg;SETSTATUS(0,iareg,tw) | |
689 iareg=tw;break; | |
690 case 0x41: break;/*ILLEGAL*/ | |
691 case 0x42: break;/*ILLEGAL*/ | |
692 case 0x43: /*COMA*/ tb=~iareg;SETNZ8(tb);SEC CLV | |
693 iareg=tb;break; | |
694 case 0x44: /*LSRA*/ tb=iareg;if(tb&0x01)SEC else CLC | |
695 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb) | |
696 iareg=tb;break; | |
697 case 0x45: break;/* ILLEGAL*/ | |
698 case 0x46: /*RORA*/ tb=(iccreg&0x01)<<7; | |
699 if(iareg&0x01)SEC else CLC | |
700 iareg=(iareg>>1)+tb;SETNZ8(iareg) | |
701 break; | |
702 case 0x47: /*ASRA*/ tb=iareg;if(tb&0x01)SEC else CLC | |
703 if(tb&0x10)SEH else CLH tb>>=1; | |
704 if(tb&0x40)tb|=0x80;iareg=tb;SETNZ8(tb) | |
705 break; | |
706 case 0x48: /*ASLA*/ tw=iareg<<1; | |
707 SETSTATUS(iareg,iareg,tw) | |
708 iareg=tw;break; | |
709 case 0x49: /*ROLA*/ tb=iareg;tw=iccreg&0x01; | |
710 if(tb&0x80)SEC else CLC | |
711 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV | |
712 tb=(tb<<1)+tw;SETNZ8(tb) iareg=tb;break; | |
713 case 0x4A: /*DECA*/ tb=iareg-1;if(tb==0x7F)SEV else CLV | |
714 SETNZ8(tb) iareg=tb;break; | |
715 case 0x4B: break; /*ILLEGAL*/ | |
716 case 0x4C: /*INCA*/ tb=iareg+1;if(tb==0x80)SEV else CLV | |
717 SETNZ8(tb) iareg=tb;break; | |
718 case 0x4D: /*TSTA*/ SETNZ8(iareg) break; | |
719 case 0x4E: break; /*ILLEGAL*/ | |
720 case 0x4F: /*CLRA*/ iareg=0;CLN CLV SEZ CLC break; | |
721 case 0x50: /*NEGB*/ tw=-ibreg;SETSTATUS(0,ibreg,tw) | |
722 ibreg=tw;break; | |
723 case 0x51: break;/*ILLEGAL*/ | |
724 case 0x52: break;/*ILLEGAL*/ | |
725 case 0x53: /*COMB*/ tb=~ibreg;SETNZ8(tb);SEC CLV | |
726 ibreg=tb;break; | |
727 case 0x54: /*LSRB*/ tb=ibreg;if(tb&0x01)SEC else CLC | |
728 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb) | |
729 ibreg=tb;break; | |
730 case 0x55: break;/* ILLEGAL*/ | |
731 case 0x56: /*RORB*/ tb=(iccreg&0x01)<<7; | |
732 if(ibreg&0x01)SEC else CLC | |
733 ibreg=(ibreg>>1)+tb;SETNZ8(ibreg) | |
734 break; | |
735 case 0x57: /*ASRB*/ tb=ibreg;if(tb&0x01)SEC else CLC | |
736 if(tb&0x10)SEH else CLH tb>>=1; | |
737 if(tb&0x40)tb|=0x80;ibreg=tb;SETNZ8(tb) | |
738 break; | |
739 case 0x58: /*ASLB*/ tw=ibreg<<1; | |
740 SETSTATUS(ibreg,ibreg,tw) | |
741 ibreg=tw;break; | |
742 case 0x59: /*ROLB*/ tb=ibreg;tw=iccreg&0x01; | |
743 if(tb&0x80)SEC else CLC | |
744 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV | |
745 tb=(tb<<1)+tw;SETNZ8(tb) ibreg=tb;break; | |
746 case 0x5A: /*DECB*/ tb=ibreg-1;if(tb==0x7F)SEV else CLV | |
747 SETNZ8(tb) ibreg=tb;break; | |
748 case 0x5B: break; /*ILLEGAL*/ | |
749 case 0x5C: /*INCB*/ tb=ibreg+1;if(tb==0x80)SEV else CLV | |
750 SETNZ8(tb) ibreg=tb;break; | |
751 case 0x5D: /*TSTB*/ SETNZ8(ibreg) break; | |
752 case 0x5E: break; /*ILLEGAL*/ | |
753 case 0x5F: /*CLRB*/ ibreg=0;CLN CLV SEZ CLC break; | |
4 | 754 case 0x60: /*NEG indexed*/ tw=-mem(eaddr);SETSTATUS(0,mem(eaddr),tw) |
0 | 755 SETBYTE(eaddr,tw)break; |
756 case 0x61: break;/*ILLEGAL*/ | |
757 case 0x62: break;/*ILLEGAL*/ | |
4 | 758 case 0x63: /*COM indexed*/ tb=~mem(eaddr);SETNZ8(tb);SEC CLV |
0 | 759 SETBYTE(eaddr,tb)break; |
4 | 760 case 0x64: /*LSR indexed*/ tb=mem(eaddr);if(tb&0x01)SEC else CLC |
0 | 761 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb) |
762 SETBYTE(eaddr,tb)break; | |
763 case 0x65: break;/* ILLEGAL*/ | |
764 case 0x66: /*ROR indexed*/ tb=(iccreg&0x01)<<7; | |
4 | 765 if(mem(eaddr)&0x01)SEC else CLC |
766 tw=(mem(eaddr)>>1)+tb;SETNZ8(tw) | |
0 | 767 SETBYTE(eaddr,tw) |
768 break; | |
4 | 769 case 0x67: /*ASR indexed*/ tb=mem(eaddr);if(tb&0x01)SEC else CLC |
0 | 770 if(tb&0x10)SEH else CLH tb>>=1; |
771 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb) | |
772 break; | |
4 | 773 case 0x68: /*ASL indexed*/ tw=mem(eaddr)<<1; |
774 SETSTATUS(mem(eaddr),mem(eaddr),tw) | |
0 | 775 SETBYTE(eaddr,tw)break; |
4 | 776 case 0x69: /*ROL indexed*/ tb=mem(eaddr);tw=iccreg&0x01; |
0 | 777 if(tb&0x80)SEC else CLC |
778 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV | |
779 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break; | |
4 | 780 case 0x6A: /*DEC indexed*/ tb=mem(eaddr)-1;if(tb==0x7F)SEV else CLV |
0 | 781 SETNZ8(tb) SETBYTE(eaddr,tb)break; |
782 case 0x6B: break; /*ILLEGAL*/ | |
4 | 783 case 0x6C: /*INC indexed*/ tb=mem(eaddr)+1;if(tb==0x80)SEV else CLV |
0 | 784 SETNZ8(tb) SETBYTE(eaddr,tb)break; |
4 | 785 case 0x6D: /*TST indexed*/ tb=mem(eaddr);SETNZ8(tb) break; |
0 | 786 case 0x6E: /*JMP indexed*/ ipcreg=eaddr;break; |
787 case 0x6F: /*CLR indexed*/ SETBYTE(eaddr,0)CLN CLV SEZ CLC break; | |
4 | 788 case 0x70: /*NEG ext*/ EXTENDED tw=-mem(eaddr);SETSTATUS(0,mem(eaddr),tw) |
0 | 789 SETBYTE(eaddr,tw)break; |
790 case 0x71: break;/*ILLEGAL*/ | |
791 case 0x72: break;/*ILLEGAL*/ | |
4 | 792 case 0x73: /*COM ext*/ EXTENDED tb=~mem(eaddr);SETNZ8(tb);SEC CLV |
0 | 793 SETBYTE(eaddr,tb)break; |
4 | 794 case 0x74: /*LSR ext*/ EXTENDED tb=mem(eaddr);if(tb&0x01)SEC else CLC |
0 | 795 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb) |
796 SETBYTE(eaddr,tb)break; | |
797 case 0x75: break;/* ILLEGAL*/ | |
798 case 0x76: /*ROR ext*/ EXTENDED tb=(iccreg&0x01)<<7; | |
4 | 799 if(mem(eaddr)&0x01)SEC else CLC |
800 tw=(mem(eaddr)>>1)+tb;SETNZ8(tw) | |
0 | 801 SETBYTE(eaddr,tw) |
802 break; | |
4 | 803 case 0x77: /*ASR ext*/ EXTENDED tb=mem(eaddr);if(tb&0x01)SEC else CLC |
0 | 804 if(tb&0x10)SEH else CLH tb>>=1; |
805 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb) | |
806 break; | |
4 | 807 case 0x78: /*ASL ext*/ EXTENDED tw=mem(eaddr)<<1; |
808 SETSTATUS(mem(eaddr),mem(eaddr),tw) | |
0 | 809 SETBYTE(eaddr,tw)break; |
4 | 810 case 0x79: /*ROL ext*/ EXTENDED tb=mem(eaddr);tw=iccreg&0x01; |
0 | 811 if(tb&0x80)SEC else CLC |
812 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV | |
813 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break; | |
4 | 814 case 0x7A: /*DEC ext*/ EXTENDED tb=mem(eaddr)-1;if(tb==0x7F)SEV else CLV |
0 | 815 SETNZ8(tb) SETBYTE(eaddr,tb)break; |
816 case 0x7B: break; /*ILLEGAL*/ | |
4 | 817 case 0x7C: /*INC ext*/ EXTENDED tb=mem(eaddr)+1;if(tb==0x80)SEV else CLV |
0 | 818 SETNZ8(tb) SETBYTE(eaddr,tb)break; |
4 | 819 case 0x7D: /*TST ext*/ EXTENDED tb=mem(eaddr);SETNZ8(tb) break; |
0 | 820 case 0x7E: /*JMP ext*/ EXTENDED ipcreg=eaddr;break; |
821 case 0x7F: /*CLR ext*/ EXTENDED SETBYTE(eaddr,0)CLN CLV SEZ CLC break; | |
4 | 822 case 0x80: /*SUBA immediate*/ IMM8 tw=iareg-mem(eaddr); |
823 SETSTATUS(iareg,mem(eaddr),tw) | |
0 | 824 iareg=tw;break; |
4 | 825 case 0x81: /*CMPA immediate*/ IMM8 tw=iareg-mem(eaddr); |
826 SETSTATUS(iareg,mem(eaddr),tw) break; | |
827 case 0x82: /*SBCA immediate*/ IMM8 tw=iareg-mem(eaddr)-(iccreg&0x01); | |
828 SETSTATUS(iareg,mem(eaddr),tw) | |
0 | 829 iareg=tw;break; |
830 case 0x83: /*SUBD (CMPD CMPU) immediate*/ IMM16 | |
831 {unsigned long res,dreg,breg; | |
832 if(iflag==2)dreg=iureg;else dreg=GETDREG; | |
833 breg=GETWORD(eaddr); | |
834 res=dreg-breg; | |
835 SETSTATUSD(dreg,breg,res) | |
836 if(iflag==0) SETDREG(res) | |
837 }break; | |
4 | 838 case 0x84: /*ANDA immediate*/ IMM8 iareg=iareg&mem(eaddr);SETNZ8(iareg) |
0 | 839 CLV break; |
4 | 840 case 0x85: /*BITA immediate*/ IMM8 tb=iareg&mem(eaddr);SETNZ8(tb) |
0 | 841 CLV break; |
842 case 0x86: /*LDA immediate*/ IMM8 LOADAC(iareg) CLV SETNZ8(iareg) | |
843 break; | |
844 case 0x87: /*STA immediate (for the sake of orthogonality) */ IMM8 | |
845 SETNZ8(iareg) CLV STOREAC(iareg) break; | |
4 | 846 case 0x88: /*EORA immediate*/ IMM8 iareg=iareg^mem(eaddr);SETNZ8(iareg) |
0 | 847 CLV break; |
4 | 848 case 0x89: /*ADCA immediate*/ IMM8 tw=iareg+mem(eaddr)+(iccreg&0x01); |
849 SETSTATUS(iareg,mem(eaddr),tw) | |
0 | 850 iareg=tw;break; |
4 | 851 case 0x8A: /*ORA immediate*/ IMM8 iareg=iareg|mem(eaddr);SETNZ8(iareg) |
0 | 852 CLV break; |
4 | 853 case 0x8B: /*ADDA immediate*/ IMM8 tw=iareg+mem(eaddr); |
854 SETSTATUS(iareg,mem(eaddr),tw) | |
0 | 855 iareg=tw;break; |
856 case 0x8C: /*CMPX (CMPY CMPS) immediate */ IMM16 | |
857 {unsigned long dreg,breg,res; | |
858 if(iflag==0)dreg=ixreg;else if(iflag==1) | |
859 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr); | |
860 res=dreg-breg; | |
861 SETSTATUSD(dreg,breg,res) | |
862 }break; | |
863 case 0x8D: /*BSR */ IMMBYTE(tb) PUSHWORD(ipcreg) ipcreg+=SIGNED(tb); | |
864 break; | |
865 case 0x8E: /* LDX (LDY) immediate */ IMM16 tw=GETWORD(eaddr); | |
866 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else | |
867 iyreg=tw;break; | |
868 case 0x8F: /* STX (STY) immediate (orthogonality) */ IMM16 | |
869 if(!iflag) tw=ixreg; else tw=iyreg; | |
870 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
4 | 871 case 0x90: /*SUBA direct*/ DIRECT tw=iareg-mem(eaddr); |
872 SETSTATUS(iareg,mem(eaddr),tw) | |
0 | 873 iareg=tw;break; |
4 | 874 case 0x91: /*CMPA direct*/ DIRECT tw=iareg-mem(eaddr); |
875 SETSTATUS(iareg,mem(eaddr),tw) break; | |
876 case 0x92: /*SBCA direct*/ DIRECT tw=iareg-mem(eaddr)-(iccreg&0x01); | |
877 SETSTATUS(iareg,mem(eaddr),tw) | |
0 | 878 iareg=tw;break; |
879 case 0x93: /*SUBD (CMPD CMPU) direct*/ DIRECT | |
880 {unsigned long res,dreg,breg; | |
881 if(iflag==2)dreg=iureg;else dreg=GETDREG; | |
882 breg=GETWORD(eaddr); | |
883 res=dreg-breg; | |
884 SETSTATUSD(dreg,breg,res) | |
885 if(iflag==0) SETDREG(res) | |
886 }break; | |
4 | 887 case 0x94: /*ANDA direct*/ DIRECT iareg=iareg&mem(eaddr);SETNZ8(iareg) |
0 | 888 CLV break; |
4 | 889 case 0x95: /*BITA direct*/ DIRECT tb=iareg&mem(eaddr);SETNZ8(tb) |
0 | 890 CLV break; |
891 case 0x96: /*LDA direct*/ DIRECT LOADAC(iareg) CLV SETNZ8(iareg) | |
892 break; | |
893 case 0x97: /*STA direct */ DIRECT | |
894 SETNZ8(iareg) CLV STOREAC(iareg) break; | |
4 | 895 case 0x98: /*EORA direct*/ DIRECT iareg=iareg^mem(eaddr);SETNZ8(iareg) |
0 | 896 CLV break; |
4 | 897 case 0x99: /*ADCA direct*/ DIRECT tw=iareg+mem(eaddr)+(iccreg&0x01); |
898 SETSTATUS(iareg,mem(eaddr),tw) | |
0 | 899 iareg=tw;break; |
4 | 900 case 0x9A: /*ORA direct*/ DIRECT iareg=iareg|mem(eaddr);SETNZ8(iareg) |
0 | 901 CLV break; |
4 | 902 case 0x9B: /*ADDA direct*/ DIRECT tw=iareg+mem(eaddr); |
903 SETSTATUS(iareg,mem(eaddr),tw) | |
0 | 904 iareg=tw;break; |
905 case 0x9C: /*CMPX (CMPY CMPS) direct */ DIRECT | |
906 {unsigned long dreg,breg,res; | |
907 if(iflag==0)dreg=ixreg;else if(iflag==1) | |
908 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr); | |
909 res=dreg-breg; | |
910 SETSTATUSD(dreg,breg,res) | |
911 }break; | |
912 case 0x9D: /*JSR direct */ DIRECT PUSHWORD(ipcreg) ipcreg=eaddr; | |
913 break; | |
914 case 0x9E: /* LDX (LDY) direct */ DIRECT tw=GETWORD(eaddr); | |
915 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else | |
916 iyreg=tw;break; | |
917 case 0x9F: /* STX (STY) direct */ DIRECT | |
918 if(!iflag) tw=ixreg; else tw=iyreg; | |
919 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
4 | 920 case 0xA0: /*SUBA indexed*/ tw=iareg-mem(eaddr); |
921 SETSTATUS(iareg,mem(eaddr),tw) | |
0 | 922 iareg=tw;break; |
4 | 923 case 0xA1: /*CMPA indexed*/ tw=iareg-mem(eaddr); |
924 SETSTATUS(iareg,mem(eaddr),tw) break; | |
925 case 0xA2: /*SBCA indexed*/ tw=iareg-mem(eaddr)-(iccreg&0x01); | |
926 SETSTATUS(iareg,mem(eaddr),tw) | |
0 | 927 iareg=tw;break; |
928 case 0xA3: /*SUBD (CMPD CMPU) indexed*/ | |
929 {unsigned long res,dreg,breg; | |
930 if(iflag==2)dreg=iureg;else dreg=GETDREG; | |
931 breg=GETWORD(eaddr); | |
932 res=dreg-breg; | |
933 SETSTATUSD(dreg,breg,res) | |
934 if(iflag==0) SETDREG(res) | |
935 }break; | |
4 | 936 case 0xA4: /*ANDA indexed*/ iareg=iareg&mem(eaddr);SETNZ8(iareg) |
0 | 937 CLV break; |
4 | 938 case 0xA5: /*BITA indexed*/ tb=iareg&mem(eaddr);SETNZ8(tb) |
0 | 939 CLV break; |
940 case 0xA6: /*LDA indexed*/ LOADAC(iareg) CLV SETNZ8(iareg) | |
941 break; | |
942 case 0xA7: /*STA indexed */ | |
943 SETNZ8(iareg) CLV STOREAC(iareg) break; | |
4 | 944 case 0xA8: /*EORA indexed*/ iareg=iareg^mem(eaddr);SETNZ8(iareg) |
0 | 945 CLV break; |
4 | 946 case 0xA9: /*ADCA indexed*/ tw=iareg+mem(eaddr)+(iccreg&0x01); |
947 SETSTATUS(iareg,mem(eaddr),tw) | |
0 | 948 iareg=tw;break; |
4 | 949 case 0xAA: /*ORA indexed*/ iareg=iareg|mem(eaddr);SETNZ8(iareg) |
0 | 950 CLV break; |
4 | 951 case 0xAB: /*ADDA indexed*/ tw=iareg+mem(eaddr); |
952 SETSTATUS(iareg,mem(eaddr),tw) | |
0 | 953 iareg=tw;break; |
954 case 0xAC: /*CMPX (CMPY CMPS) indexed */ | |
955 {unsigned long dreg,breg,res; | |
956 if(iflag==0)dreg=ixreg;else if(iflag==1) | |
957 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr); | |
958 res=dreg-breg; | |
959 SETSTATUSD(dreg,breg,res) | |
960 }break; | |
961 case 0xAD: /*JSR indexed */ PUSHWORD(ipcreg) ipcreg=eaddr; | |
962 break; | |
963 case 0xAE: /* LDX (LDY) indexed */ tw=GETWORD(eaddr); | |
964 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else | |
965 iyreg=tw;break; | |
966 case 0xAF: /* STX (STY) indexed */ | |
967 if(!iflag) tw=ixreg; else tw=iyreg; | |
968 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
4 | 969 case 0xB0: /*SUBA ext*/ EXTENDED tw=iareg-mem(eaddr); |
970 SETSTATUS(iareg,mem(eaddr),tw) | |
0 | 971 iareg=tw;break; |
4 | 972 case 0xB1: /*CMPA ext*/ EXTENDED tw=iareg-mem(eaddr); |
973 SETSTATUS(iareg,mem(eaddr),tw) break; | |
974 case 0xB2: /*SBCA ext*/ EXTENDED tw=iareg-mem(eaddr)-(iccreg&0x01); | |
975 SETSTATUS(iareg,mem(eaddr),tw) | |
0 | 976 iareg=tw;break; |
977 case 0xB3: /*SUBD (CMPD CMPU) ext*/ EXTENDED | |
978 {unsigned long res,dreg,breg; | |
979 if(iflag==2)dreg=iureg;else dreg=GETDREG; | |
980 breg=GETWORD(eaddr); | |
981 res=dreg-breg; | |
982 SETSTATUSD(dreg,breg,res) | |
983 if(iflag==0) SETDREG(res) | |
984 }break; | |
4 | 985 case 0xB4: /*ANDA ext*/ EXTENDED iareg=iareg&mem(eaddr);SETNZ8(iareg) |
0 | 986 CLV break; |
4 | 987 case 0xB5: /*BITA ext*/ EXTENDED tb=iareg&mem(eaddr);SETNZ8(tb) |
0 | 988 CLV break; |
989 case 0xB6: /*LDA ext*/ EXTENDED LOADAC(iareg) CLV SETNZ8(iareg) | |
990 break; | |
991 case 0xB7: /*STA ext */ EXTENDED | |
992 SETNZ8(iareg) CLV STOREAC(iareg) break; | |
4 | 993 case 0xB8: /*EORA ext*/ EXTENDED iareg=iareg^mem(eaddr);SETNZ8(iareg) |
0 | 994 CLV break; |
4 | 995 case 0xB9: /*ADCA ext*/ EXTENDED tw=iareg+mem(eaddr)+(iccreg&0x01); |
996 SETSTATUS(iareg,mem(eaddr),tw) | |
0 | 997 iareg=tw;break; |
4 | 998 case 0xBA: /*ORA ext*/ EXTENDED iareg=iareg|mem(eaddr);SETNZ8(iareg) |
0 | 999 CLV break; |
4 | 1000 case 0xBB: /*ADDA ext*/ EXTENDED tw=iareg+mem(eaddr); |
1001 SETSTATUS(iareg,mem(eaddr),tw) | |
0 | 1002 iareg=tw;break; |
1003 case 0xBC: /*CMPX (CMPY CMPS) ext */ EXTENDED | |
1004 {unsigned long dreg,breg,res; | |
1005 if(iflag==0)dreg=ixreg;else if(iflag==1) | |
1006 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr); | |
1007 res=dreg-breg; | |
1008 SETSTATUSD(dreg,breg,res) | |
1009 }break; | |
1010 case 0xBD: /*JSR ext */ EXTENDED PUSHWORD(ipcreg) ipcreg=eaddr; | |
1011 break; | |
1012 case 0xBE: /* LDX (LDY) ext */ EXTENDED tw=GETWORD(eaddr); | |
1013 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else | |
1014 iyreg=tw;break; | |
1015 case 0xBF: /* STX (STY) ext */ EXTENDED | |
1016 if(!iflag) tw=ixreg; else tw=iyreg; | |
1017 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
4 | 1018 case 0xC0: /*SUBB immediate*/ IMM8 tw=ibreg-mem(eaddr); |
1019 SETSTATUS(ibreg,mem(eaddr),tw) | |
0 | 1020 ibreg=tw;break; |
4 | 1021 case 0xC1: /*CMPB immediate*/ IMM8 tw=ibreg-mem(eaddr); |
1022 SETSTATUS(ibreg,mem(eaddr),tw) break; | |
1023 case 0xC2: /*SBCB immediate*/ IMM8 tw=ibreg-mem(eaddr)-(iccreg&0x01); | |
1024 SETSTATUS(ibreg,mem(eaddr),tw) | |
0 | 1025 ibreg=tw;break; |
1026 case 0xC3: /*ADDD immediate*/ IMM16 | |
1027 {unsigned long res,dreg,breg; | |
1028 dreg=GETDREG; | |
1029 breg=GETWORD(eaddr); | |
1030 res=dreg+breg; | |
1031 SETSTATUSD(dreg,breg,res) | |
1032 SETDREG(res) | |
1033 }break; | |
4 | 1034 case 0xC4: /*ANDB immediate*/ IMM8 ibreg=ibreg&mem(eaddr);SETNZ8(ibreg) |
0 | 1035 CLV break; |
4 | 1036 case 0xC5: /*BITB immediate*/ IMM8 tb=ibreg&mem(eaddr);SETNZ8(tb) |
0 | 1037 CLV break; |
1038 case 0xC6: /*LDB immediate*/ IMM8 LOADAC(ibreg) CLV SETNZ8(ibreg) | |
1039 break; | |
1040 case 0xC7: /*STB immediate (for the sake of orthogonality) */ IMM8 | |
1041 SETNZ8(ibreg) CLV STOREAC(ibreg) break; | |
4 | 1042 case 0xC8: /*EORB immediate*/ IMM8 ibreg=ibreg^mem(eaddr);SETNZ8(ibreg) |
0 | 1043 CLV break; |
4 | 1044 case 0xC9: /*ADCB immediate*/ IMM8 tw=ibreg+mem(eaddr)+(iccreg&0x01); |
1045 SETSTATUS(ibreg,mem(eaddr),tw) | |
0 | 1046 ibreg=tw;break; |
4 | 1047 case 0xCA: /*ORB immediate*/ IMM8 ibreg=ibreg|mem(eaddr);SETNZ8(ibreg) |
0 | 1048 CLV break; |
4 | 1049 case 0xCB: /*ADDB immediate*/ IMM8 tw=ibreg+mem(eaddr); |
1050 SETSTATUS(ibreg,mem(eaddr),tw) | |
0 | 1051 ibreg=tw;break; |
1052 case 0xCC: /*LDD immediate */ IMM16 tw=GETWORD(eaddr);SETNZ16(tw) | |
1053 CLV SETDREG(tw) break; | |
1054 case 0xCD: /*STD immediate (orthogonality) */ IMM16 | |
1055 tw=GETDREG; SETNZ16(tw) CLV | |
1056 SETWORD(eaddr,tw) break; | |
1057 case 0xCE: /* LDU (LDS) immediate */ IMM16 tw=GETWORD(eaddr); | |
1058 CLV SETNZ16(tw) if(!iflag)iureg=tw; else | |
1059 isreg=tw;break; | |
1060 case 0xCF: /* STU (STS) immediate (orthogonality) */ IMM16 | |
1061 if(!iflag) tw=iureg; else tw=isreg; | |
1062 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
4 | 1063 case 0xD0: /*SUBB direct*/ DIRECT tw=ibreg-mem(eaddr); |
1064 SETSTATUS(ibreg,mem(eaddr),tw) | |
0 | 1065 ibreg=tw;break; |
4 | 1066 case 0xD1: /*CMPB direct*/ DIRECT tw=ibreg-mem(eaddr); |
1067 SETSTATUS(ibreg,mem(eaddr),tw) break; | |
1068 case 0xD2: /*SBCB direct*/ DIRECT tw=ibreg-mem(eaddr)-(iccreg&0x01); | |
1069 SETSTATUS(ibreg,mem(eaddr),tw) | |
0 | 1070 ibreg=tw;break; |
1071 case 0xD3: /*ADDD direct*/ DIRECT | |
1072 {unsigned long res,dreg,breg; | |
1073 dreg=GETDREG; | |
1074 breg=GETWORD(eaddr); | |
1075 res=dreg+breg; | |
1076 SETSTATUSD(dreg,breg,res) | |
1077 SETDREG(res) | |
1078 }break; | |
4 | 1079 case 0xD4: /*ANDB direct*/ DIRECT ibreg=ibreg&mem(eaddr);SETNZ8(ibreg) |
0 | 1080 CLV break; |
4 | 1081 case 0xD5: /*BITB direct*/ DIRECT tb=ibreg&mem(eaddr);SETNZ8(tb) |
0 | 1082 CLV break; |
1083 case 0xD6: /*LDB direct*/ DIRECT LOADAC(ibreg) CLV SETNZ8(ibreg) | |
1084 break; | |
1085 case 0xD7: /*STB direct */ DIRECT | |
1086 SETNZ8(ibreg) CLV STOREAC(ibreg) break; | |
4 | 1087 case 0xD8: /*EORB direct*/ DIRECT ibreg=ibreg^mem(eaddr);SETNZ8(ibreg) |
0 | 1088 CLV break; |
4 | 1089 case 0xD9: /*ADCB direct*/ DIRECT tw=ibreg+mem(eaddr)+(iccreg&0x01); |
1090 SETSTATUS(ibreg,mem(eaddr),tw) | |
0 | 1091 ibreg=tw;break; |
4 | 1092 case 0xDA: /*ORB direct*/ DIRECT ibreg=ibreg|mem(eaddr);SETNZ8(ibreg) |
0 | 1093 CLV break; |
4 | 1094 case 0xDB: /*ADDB direct*/ DIRECT tw=ibreg+mem(eaddr); |
1095 SETSTATUS(ibreg,mem(eaddr),tw) | |
0 | 1096 ibreg=tw;break; |
1097 case 0xDC: /*LDD direct */ DIRECT tw=GETWORD(eaddr);SETNZ16(tw) | |
1098 CLV SETDREG(tw) break; | |
1099 case 0xDD: /*STD direct */ DIRECT | |
1100 tw=GETDREG; SETNZ16(tw) CLV | |
1101 SETWORD(eaddr,tw) break; | |
1102 case 0xDE: /* LDU (LDS) direct */ DIRECT tw=GETWORD(eaddr); | |
1103 CLV SETNZ16(tw) if(!iflag)iureg=tw; else | |
1104 isreg=tw;break; | |
1105 case 0xDF: /* STU (STS) direct */ DIRECT | |
1106 if(!iflag) tw=iureg; else tw=isreg; | |
1107 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
4 | 1108 case 0xE0: /*SUBB indexed*/ tw=ibreg-mem(eaddr); |
1109 SETSTATUS(ibreg,mem(eaddr),tw) | |
0 | 1110 ibreg=tw;break; |
4 | 1111 case 0xE1: /*CMPB indexed*/ tw=ibreg-mem(eaddr); |
1112 SETSTATUS(ibreg,mem(eaddr),tw) break; | |
1113 case 0xE2: /*SBCB indexed*/ tw=ibreg-mem(eaddr)-(iccreg&0x01); | |
1114 SETSTATUS(ibreg,mem(eaddr),tw) | |
0 | 1115 ibreg=tw;break; |
1116 case 0xE3: /*ADDD indexed*/ | |
1117 {unsigned long res,dreg,breg; | |
1118 dreg=GETDREG; | |
1119 breg=GETWORD(eaddr); | |
1120 res=dreg+breg; | |
1121 SETSTATUSD(dreg,breg,res) | |
1122 SETDREG(res) | |
1123 }break; | |
4 | 1124 case 0xE4: /*ANDB indexed*/ ibreg=ibreg&mem(eaddr);SETNZ8(ibreg) |
0 | 1125 CLV break; |
4 | 1126 case 0xE5: /*BITB indexed*/ tb=ibreg&mem(eaddr);SETNZ8(tb) |
0 | 1127 CLV break; |
1128 case 0xE6: /*LDB indexed*/ LOADAC(ibreg) CLV SETNZ8(ibreg) | |
1129 break; | |
1130 case 0xE7: /*STB indexed */ | |
1131 SETNZ8(ibreg) CLV STOREAC(ibreg) break; | |
4 | 1132 case 0xE8: /*EORB indexed*/ ibreg=ibreg^mem(eaddr);SETNZ8(ibreg) |
0 | 1133 CLV break; |
4 | 1134 case 0xE9: /*ADCB indexed*/ tw=ibreg+mem(eaddr)+(iccreg&0x01); |
1135 SETSTATUS(ibreg,mem(eaddr),tw) | |
0 | 1136 ibreg=tw;break; |
4 | 1137 case 0xEA: /*ORB indexed*/ ibreg=ibreg|mem(eaddr);SETNZ8(ibreg) |
0 | 1138 CLV break; |
4 | 1139 case 0xEB: /*ADDB indexed*/ tw=ibreg+mem(eaddr); |
1140 SETSTATUS(ibreg,mem(eaddr),tw) | |
0 | 1141 ibreg=tw;break; |
1142 case 0xEC: /*LDD indexed */ tw=GETWORD(eaddr);SETNZ16(tw) | |
1143 CLV SETDREG(tw) break; | |
1144 case 0xED: /*STD indexed */ | |
1145 tw=GETDREG; SETNZ16(tw) CLV | |
1146 SETWORD(eaddr,tw) break; | |
1147 case 0xEE: /* LDU (LDS) indexed */ tw=GETWORD(eaddr); | |
1148 CLV SETNZ16(tw) if(!iflag)iureg=tw; else | |
1149 isreg=tw;break; | |
1150 case 0xEF: /* STU (STS) indexed */ | |
1151 if(!iflag) tw=iureg; else tw=isreg; | |
1152 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
4 | 1153 case 0xF0: /*SUBB ext*/ EXTENDED tw=ibreg-mem(eaddr); |
1154 SETSTATUS(ibreg,mem(eaddr),tw) | |
0 | 1155 ibreg=tw;break; |
4 | 1156 case 0xF1: /*CMPB ext*/ EXTENDED tw=ibreg-mem(eaddr); |
1157 SETSTATUS(ibreg,mem(eaddr),tw) break; | |
1158 case 0xF2: /*SBCB ext*/ EXTENDED tw=ibreg-mem(eaddr)-(iccreg&0x01); | |
1159 SETSTATUS(ibreg,mem(eaddr),tw) | |
0 | 1160 ibreg=tw;break; |
1161 case 0xF3: /*ADDD ext*/ EXTENDED | |
1162 {unsigned long res,dreg,breg; | |
1163 dreg=GETDREG; | |
1164 breg=GETWORD(eaddr); | |
1165 res=dreg+breg; | |
1166 SETSTATUSD(dreg,breg,res) | |
1167 SETDREG(res) | |
1168 }break; | |
4 | 1169 case 0xF4: /*ANDB ext*/ EXTENDED ibreg=ibreg&mem(eaddr);SETNZ8(ibreg) |
0 | 1170 CLV break; |
4 | 1171 case 0xF5: /*BITB ext*/ EXTENDED tb=ibreg&mem(eaddr);SETNZ8(tb) |
0 | 1172 CLV break; |
1173 case 0xF6: /*LDB ext*/ EXTENDED LOADAC(ibreg) CLV SETNZ8(ibreg) | |
1174 break; | |
1175 case 0xF7: /*STB ext */ EXTENDED | |
1176 SETNZ8(ibreg) CLV STOREAC(ibreg) break; | |
4 | 1177 case 0xF8: /*EORB ext*/ EXTENDED ibreg=ibreg^mem(eaddr);SETNZ8(ibreg) |
0 | 1178 CLV break; |
4 | 1179 case 0xF9: /*ADCB ext*/ EXTENDED tw=ibreg+mem(eaddr)+(iccreg&0x01); |
1180 SETSTATUS(ibreg,mem(eaddr),tw) | |
0 | 1181 ibreg=tw;break; |
4 | 1182 case 0xFA: /*ORB ext*/ EXTENDED ibreg=ibreg|mem(eaddr);SETNZ8(ibreg) |
0 | 1183 CLV break; |
4 | 1184 case 0xFB: /*ADDB ext*/ EXTENDED tw=ibreg+mem(eaddr); |
1185 SETSTATUS(ibreg,mem(eaddr),tw) | |
0 | 1186 ibreg=tw;break; |
1187 case 0xFC: /*LDD ext */ EXTENDED tw=GETWORD(eaddr);SETNZ16(tw) | |
1188 CLV SETDREG(tw) break; | |
1189 case 0xFD: /*STD ext */ EXTENDED | |
1190 tw=GETDREG; SETNZ16(tw) CLV | |
1191 SETWORD(eaddr,tw) break; | |
1192 case 0xFE: /* LDU (LDS) ext */ EXTENDED tw=GETWORD(eaddr); | |
1193 CLV SETNZ16(tw) if(!iflag)iureg=tw; else | |
1194 isreg=tw;break; | |
1195 case 0xFF: /* STU (STS) ext */ EXTENDED | |
1196 if(!iflag) tw=iureg; else tw=isreg; | |
1197 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
1198 | |
1199 | |
1200 } | |
1201 } | |
1202 } | |
1203 |