Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/pa/pa64-regs.h @ 111:04ced10e8804
gcc 7
| author | kono |
|---|---|
| date | Fri, 27 Oct 2017 22:46:09 +0900 |
| parents | f6334be47118 |
| children | 84e7813d76e9 |
| rev | line source |
|---|---|
| 0 | 1 /* Configuration for GCC-compiler for PA-RISC. |
| 111 | 2 Copyright (C) 1999-2017 Free Software Foundation, Inc. |
| 0 | 3 |
| 4 This file is part of GCC. | |
| 5 | |
| 6 GCC is free software; you can redistribute it and/or modify | |
| 7 it under the terms of the GNU General Public License as published by | |
| 8 the Free Software Foundation; either version 3, or (at your option) | |
| 9 any later version. | |
| 10 | |
| 11 GCC is distributed in the hope that it will be useful, | |
| 12 but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 GNU General Public License for more details. | |
| 15 | |
| 16 You should have received a copy of the GNU General Public License | |
| 17 along with GCC; see the file COPYING3. If not see | |
| 18 <http://www.gnu.org/licenses/>. */ | |
| 19 | |
| 20 /* Standard register usage. | |
| 21 | |
| 22 It is safe to refer to actual register numbers in this file. */ | |
| 23 | |
| 24 /* Number of actual hardware registers. | |
| 25 The hardware registers are assigned numbers for the compiler | |
| 26 from 0 to just below FIRST_PSEUDO_REGISTER. | |
| 27 All registers that the compiler knows about must be given numbers, | |
| 28 even those that are not normally considered general registers. | |
| 29 | |
| 30 HP-PA 2.0w has 32 fullword registers and 32 floating point | |
| 31 registers. However, the floating point registers behave | |
| 32 differently: the left and right halves of registers are addressable | |
| 33 as 32-bit registers. | |
| 34 | |
| 35 Due to limitations within GCC itself, we do not expose the left/right | |
| 36 half addressability when in wide mode. This is not a major performance | |
| 37 issue as using the halves independently triggers false dependency stalls | |
| 38 anyway. */ | |
| 39 | |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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40 #define FIRST_PSEUDO_REGISTER 62 /* 32 general regs + 28 fp regs + |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
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41 + 1 shift reg + frame pointer */ |
| 0 | 42 |
| 43 /* 1 for registers that have pervasive standard uses | |
| 44 and are not available for the register allocator. | |
| 45 | |
| 46 On the HP-PA, these are: | |
| 47 Reg 0 = 0 (hardware). However, 0 is used for condition code, | |
| 48 so is not fixed. | |
| 49 Reg 1 = ADDIL target/Temporary (hardware). | |
| 50 Reg 2 = Return Pointer | |
| 51 Reg 3 = Frame Pointer | |
| 52 Reg 4 = Frame Pointer (>8k varying frame with HP compilers only) | |
| 53 Reg 4-18 = Preserved Registers | |
| 54 Reg 19 = Linkage Table Register in HPUX 8.0 shared library scheme. | |
| 55 Reg 20-22 = Temporary Registers | |
| 56 Reg 23-26 = Temporary/Parameter Registers | |
| 57 Reg 27 = Global Data Pointer (hp) | |
| 58 Reg 28 = Temporary/Return Value register | |
| 59 Reg 29 = Temporary/Static Chain/Return Value register #2 | |
| 60 Reg 30 = stack pointer | |
| 61 Reg 31 = Temporary/Millicode Return Pointer (hp) | |
| 62 | |
| 63 Freg 0-3 = Status Registers -- Not known to the compiler. | |
| 64 Freg 4-7 = Arguments/Return Value | |
| 65 Freg 8-11 = Temporary Registers | |
| 66 Freg 12-21 = Preserved Registers | |
| 67 Freg 22-31 = Temporary Registers | |
| 68 | |
| 69 */ | |
| 70 | |
| 71 #define FIXED_REGISTERS \ | |
| 72 {0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 73 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 74 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 75 0, 0, 0, 1, 0, 0, 1, 0, \ | |
| 76 /* fp registers */ \ | |
| 77 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 78 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 79 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 80 0, 0, 0, 0, \ | |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
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81 /* shift register and soft frame pointer */ \ |
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82 0, 1} |
| 0 | 83 |
| 84 /* 1 for registers not available across function calls. | |
| 85 These must include the FIXED_REGISTERS and also any | |
| 86 registers that can be used without being saved. | |
| 87 The latter must include the registers where values are returned | |
| 88 and the register where structure-value addresses are passed. | |
| 89 Aside from that, you can include as many other registers as you like. */ | |
| 90 #define CALL_USED_REGISTERS \ | |
| 91 {1, 1, 1, 0, 0, 0, 0, 0, \ | |
| 92 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 93 0, 0, 0, 1, 1, 1, 1, 1, \ | |
| 94 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 95 /* fp registers */ \ | |
| 96 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 97 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 98 0, 0, 1, 1, 1, 1, 1, 1, \ | |
| 99 1, 1, 1, 1, \ | |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
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100 /* shift register and soft frame pointer */ \ |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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101 1, 1} |
| 0 | 102 |
| 103 /* Allocate the call used registers first. This should minimize | |
| 104 the number of registers that need to be saved (as call used | |
| 105 registers will generally not be allocated across a call). | |
| 106 | |
| 107 Experimentation has shown slightly better results by allocating | |
| 108 FP registers first. We allocate the caller-saved registers more | |
| 109 or less in reverse order to their allocation as arguments. */ | |
| 110 | |
| 111 #define REG_ALLOC_ORDER \ | |
| 112 { \ | |
| 113 /* caller-saved fp regs. */ \ | |
| 114 50, 51, 52, 53, 54, 55, 56, 57, \ | |
| 115 58, 59, 39, 38, 37, 36, 35, 34, \ | |
| 116 33, 32, \ | |
| 117 /* caller-saved general regs. */ \ | |
| 118 28, 31, 19, 20, 21, 22, 23, 24, \ | |
| 119 25, 26, 29, 2, \ | |
| 120 /* callee-saved fp regs. */ \ | |
| 121 40, 41, 42, 43, 44, 45, 46, 47, \ | |
| 122 48, 49, \ | |
| 123 /* callee-saved general regs. */ \ | |
| 124 3, 4, 5, 6, 7, 8, 9, 10, \ | |
| 125 11, 12, 13, 14, 15, 16, 17, 18, \ | |
| 126 /* special registers. */ \ | |
|
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parents:
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changeset
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127 1, 27, 30, 0, 60, 61} |
| 0 | 128 |
| 129 | |
| 130 /* Return number of consecutive hard regs needed starting at reg REGNO | |
| 131 to hold something of mode MODE. | |
| 132 This is ordinarily the length in words of a value of mode MODE | |
| 133 but can be less for certain modes in special long registers. | |
| 134 | |
| 135 For PA64, GPRs and FPRs hold 64 bits worth. We ignore the 32-bit | |
| 136 addressability of the FPRs and pretend each register holds precisely | |
| 137 WORD_SIZE bits. Note that SCmode values are placed in a single FPR. | |
| 138 Thus, any patterns defined to operate on these values would have to | |
| 139 use the 32-bit addressability of the FPR registers. */ | |
| 111 | 140 #define PA_HARD_REGNO_NREGS(REGNO, MODE) \ |
| 0 | 141 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
| 142 | |
| 143 /* These are the valid FP modes. */ | |
| 144 #define VALID_FP_MODE_P(MODE) \ | |
| 145 ((MODE) == SFmode || (MODE) == DFmode \ | |
| 146 || (MODE) == SCmode || (MODE) == DCmode \ | |
| 147 || (MODE) == SImode || (MODE) == DImode) | |
| 148 | |
| 149 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
| 150 On the HP-PA, the cpu registers can hold any mode. We | |
| 111 | 151 force this to be an even register if it cannot hold the full mode. */ |
| 152 #define PA_HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
| 0 | 153 ((REGNO) == 0 \ |
| 154 ? (MODE) == CCmode || (MODE) == CCFPmode \ | |
| 111 | 155 : (REGNO) == 60 ? SCALAR_INT_MODE_P (MODE) \ |
| 0 | 156 /* Make wide modes be in aligned registers. */ \ |
| 157 : FP_REGNO_P (REGNO) \ | |
| 158 ? (VALID_FP_MODE_P (MODE) \ | |
| 159 && (GET_MODE_SIZE (MODE) <= 8 \ | |
| 160 || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 1) == 0) \ | |
| 161 || (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 3) == 0))) \ | |
| 162 : (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \ | |
| 163 || (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD \ | |
| 164 && ((((REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28)) \ | |
| 165 || (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD \ | |
| 166 && ((REGNO) & 3) == 3 && (REGNO) <= 23))) | |
| 167 | |
| 168 /* How to renumber registers for dbx and gdb. | |
| 169 | |
| 170 Registers 0 - 31 remain unchanged. | |
| 171 | |
| 172 Registers 32 - 59 are mapped to 72, 74, 76 ... | |
| 173 | |
| 174 Register 60 is mapped to 32. */ | |
| 175 #define DBX_REGISTER_NUMBER(REGNO) \ | |
| 176 ((REGNO) <= 31 ? (REGNO) : ((REGNO) < 60 ? (REGNO - 32) * 2 + 72 : 32)) | |
| 177 | |
| 178 /* We must not use the DBX register numbers for the DWARF 2 CFA column | |
| 179 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER. | |
| 180 Instead use the identity mapping. */ | |
| 181 #define DWARF_FRAME_REGNUM(REG) REG | |
| 182 | |
| 183 /* Define the classes of registers for register constraints in the | |
| 184 machine description. Also define ranges of constants. | |
| 185 | |
| 186 One of the classes must always be named ALL_REGS and include all hard regs. | |
| 187 If there is more than one class, another class must be named NO_REGS | |
| 188 and contain no registers. | |
| 189 | |
| 190 The name GENERAL_REGS must be the name of a class (or an alias for | |
| 191 another name such as ALL_REGS). This is the class of registers | |
| 192 that is allowed by "g" or "r" in a register constraint. | |
| 193 Also, registers outside this class are allocated only when | |
| 194 instructions express preferences for them. | |
| 195 | |
| 196 The classes must be numbered in nondecreasing order; that is, | |
| 197 a larger-numbered class must never be contained completely | |
| 198 in a smaller-numbered class. | |
| 199 | |
| 200 For any two classes, it is very desirable that there be another | |
| 201 class that represents their union. */ | |
| 202 | |
| 203 /* The HP-PA has four kinds of registers: general regs, 1.0 fp regs, | |
| 204 1.1 fp regs, and the high 1.1 fp regs, to which the operands of | |
| 205 fmpyadd and fmpysub are restricted. */ | |
| 206 | |
| 207 enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS, | |
| 208 GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES}; | |
| 209 | |
| 210 #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
| 211 | |
| 212 /* Give names of register classes as strings for dump file. */ | |
| 213 | |
| 214 #define REG_CLASS_NAMES \ | |
| 215 {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \ | |
| 216 "GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"} | |
| 217 | |
| 218 /* Define which registers fit in which classes. | |
| 219 This is an initializer for a vector of HARD_REG_SET | |
| 220 of length N_REG_CLASSES. Register 0, the "condition code" register, | |
| 221 is in no class. */ | |
| 222 | |
| 223 #define REG_CLASS_CONTENTS \ | |
| 224 {{0x00000000, 0x00000000}, /* NO_REGS */ \ | |
| 225 {0x00000002, 0x00000000}, /* R1_REGS */ \ | |
|
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f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
226 {0xfffffffe, 0x20000000}, /* GENERAL_REGS */ \ |
| 0 | 227 {0x00000000, 0x00000000}, /* FPUPPER_REGS */ \ |
| 228 {0x00000000, 0x0fffffff}, /* FP_REGS */ \ | |
|
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f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
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229 {0xfffffffe, 0x2fffffff}, /* GENERAL_OR_FP_REGS */ \ |
| 0 | 230 {0x00000000, 0x10000000}, /* SHIFT_REGS */ \ |
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f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
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231 {0xfffffffe, 0x3fffffff}} /* ALL_REGS */ |
| 0 | 232 |
| 233 /* Return the class number of the smallest class containing | |
| 234 reg number REGNO. This could be a conditional expression | |
| 235 or could index an array. */ | |
| 236 | |
| 237 #define REGNO_REG_CLASS(REGNO) \ | |
| 238 ((REGNO) == 0 ? NO_REGS \ | |
| 239 : (REGNO) == 1 ? R1_REGS \ | |
|
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f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
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240 : (REGNO) < 32 || (REGNO) == 61 ? GENERAL_REGS \ |
| 0 | 241 : (REGNO) < 60 ? FP_REGS \ |
| 242 : SHIFT_REGS) | |
| 243 | |
| 244 /* Return the maximum number of consecutive registers | |
| 245 needed to represent mode MODE in a register of class CLASS. */ | |
| 246 #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
| 247 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
| 248 | |
| 249 /* 1 if N is a possible register number for function argument passing. */ | |
| 250 | |
| 251 #define FUNCTION_ARG_REGNO_P(N) \ | |
| 252 ((((N) >= 19) && (N) <= 26) \ | |
| 253 || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39)) | |
| 254 | |
| 255 /* How to refer to registers in assembler output. | |
| 256 This sequence is indexed by compiler's hard-register-number (see above). */ | |
| 257 | |
| 258 #define REGISTER_NAMES \ | |
| 259 {"%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ | |
| 260 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ | |
| 261 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", \ | |
| 262 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", \ | |
| 263 "%fr4", "%fr5", "%fr6", "%fr7", "%fr8", "%fr9", "%fr10", "%fr11", \ | |
| 264 "%fr12", "%fr13", "%fr14", "%fr15", "%fr16", "%fr17", "%fr18", "%fr19", \ | |
| 265 "%fr20", "%fr21", "%fr22", "%fr23", "%fr24", "%fr25", "%fr26", "%fr27", \ | |
|
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f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
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266 "%fr28", "%fr29", "%fr30", "%fr31", "SAR", "sfp"} |
| 0 | 267 |
| 268 #define ADDITIONAL_REGISTER_NAMES \ | |
| 269 {{"%cr11",60}} | |
| 270 | |
| 271 #define FP_SAVED_REG_LAST 49 | |
| 272 #define FP_SAVED_REG_FIRST 40 | |
| 273 #define FP_REG_STEP 1 | |
| 274 #define FP_REG_FIRST 32 | |
| 275 #define FP_REG_LAST 59 |