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1 ;; Pipeline description for Motorola PowerPC 8540 processor.
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2 ;; Copyright (C) 2003-2017 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5
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6 ;; GCC is free software; you can redistribute it and/or modify it
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7 ;; under the terms of the GNU General Public License as published
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8 ;; by the Free Software Foundation; either version 3, or (at your
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9 ;; option) any later version.
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10
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11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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14 ;; License for more details.
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15
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_automaton "ppc8540_most,ppc8540_long,ppc8540_retire")
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21 (define_cpu_unit "ppc8540_decode_0,ppc8540_decode_1" "ppc8540_most")
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22
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23 ;; We don't simulate general issue queue (GIC). If we have SU insn
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24 ;; and then SU1 insn, they cannot be issued on the same cycle
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25 ;; (although SU1 insn and then SU insn can be issued) because the SU
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26 ;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle
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27 ;; multipass insn scheduling will find the situation and issue the SU1
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28 ;; insn and then the SU insn.
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29 (define_cpu_unit "ppc8540_issue_0,ppc8540_issue_1" "ppc8540_most")
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30
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31 ;; We could describe completion buffers slots in combination with the
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32 ;; retirement units and the order of completion but the result
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33 ;; automaton would behave in the same way because we cannot describe
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34 ;; real latency time with taking in order completion into account.
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35 ;; Actually we could define the real latency time by querying reserved
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36 ;; automaton units but the current scheduler uses latency time before
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37 ;; issuing insns and making any reservations.
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38 ;;
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39 ;; So our description is aimed to achieve a insn schedule in which the
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40 ;; insns would not wait in the completion buffer.
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41 (define_cpu_unit "ppc8540_retire_0,ppc8540_retire_1" "ppc8540_retire")
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42
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43 ;; Branch unit:
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44 (define_cpu_unit "ppc8540_bu" "ppc8540_most")
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45
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46 ;; SU:
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47 (define_cpu_unit "ppc8540_su0_stage0,ppc8540_su1_stage0" "ppc8540_most")
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48
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49 ;; We could describe here MU subunits for float multiply, float add
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50 ;; etc. But the result automaton would behave the same way as the
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51 ;; described one pipeline below because MU can start only one insn
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52 ;; per cycle. Actually we could simplify the automaton more not
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53 ;; describing stages 1-3, the result automata would be the same.
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54 (define_cpu_unit "ppc8540_mu_stage0,ppc8540_mu_stage1" "ppc8540_most")
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55 (define_cpu_unit "ppc8540_mu_stage2,ppc8540_mu_stage3" "ppc8540_most")
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56
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57 ;; The following unit is used to describe non-pipelined division.
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58 (define_cpu_unit "ppc8540_mu_div" "ppc8540_long")
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59
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60 ;; Here we simplified LSU unit description not describing the stages.
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61 (define_cpu_unit "ppc8540_lsu" "ppc8540_most")
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62
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63 ;; The following units are used to make automata deterministic
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64 (define_cpu_unit "present_ppc8540_decode_0" "ppc8540_most")
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65 (define_cpu_unit "present_ppc8540_issue_0" "ppc8540_most")
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66 (define_cpu_unit "present_ppc8540_retire_0" "ppc8540_retire")
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67 (define_cpu_unit "present_ppc8540_su0_stage0" "ppc8540_most")
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68
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69 ;; The following sets to make automata deterministic when option ndfa is used.
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70 (presence_set "present_ppc8540_decode_0" "ppc8540_decode_0")
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71 (presence_set "present_ppc8540_issue_0" "ppc8540_issue_0")
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72 (presence_set "present_ppc8540_retire_0" "ppc8540_retire_0")
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73 (presence_set "present_ppc8540_su0_stage0" "ppc8540_su0_stage0")
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74
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75 ;; Some useful abbreviations.
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76 (define_reservation "ppc8540_decode"
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77 "ppc8540_decode_0|ppc8540_decode_1+present_ppc8540_decode_0")
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78 (define_reservation "ppc8540_issue"
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79 "ppc8540_issue_0|ppc8540_issue_1+present_ppc8540_issue_0")
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80 (define_reservation "ppc8540_retire"
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81 "ppc8540_retire_0|ppc8540_retire_1+present_ppc8540_retire_0")
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82 (define_reservation "ppc8540_su_stage0"
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83 "ppc8540_su0_stage0|ppc8540_su1_stage0+present_ppc8540_su0_stage0")
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84
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85 ;; Simple SU insns
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86 (define_insn_reservation "ppc8540_su" 1
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87 (and (eq_attr "type" "integer,add,logical,insert,cmp,\
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88 shift,trap,cntlz,exts,isel")
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89 (eq_attr "cpu" "ppc8540,ppc8548"))
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90 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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91
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92 (define_insn_reservation "ppc8540_two" 1
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93 (and (eq_attr "type" "two")
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94 (eq_attr "cpu" "ppc8540,ppc8548"))
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95 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
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96 ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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97
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98 (define_insn_reservation "ppc8540_three" 1
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99 (and (eq_attr "type" "three")
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100 (eq_attr "cpu" "ppc8540,ppc8548"))
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101 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
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102 ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
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103 ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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104
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105 ;; Branch. Actually this latency time is not used by the scheduler.
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106 (define_insn_reservation "ppc8540_branch" 1
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107 (and (eq_attr "type" "jmpreg,branch,isync")
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108 (eq_attr "cpu" "ppc8540,ppc8548"))
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109 "ppc8540_decode,ppc8540_bu,ppc8540_retire")
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110
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111 ;; Multiply
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112 (define_insn_reservation "ppc8540_multiply" 4
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113 (and (eq_attr "type" "mul")
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114 (eq_attr "cpu" "ppc8540,ppc8548"))
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115 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
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116 ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
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117
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118 ;; Divide. We use the average latency time here. We omit reserving a
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119 ;; retire unit because of the result automata will be huge. We ignore
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120 ;; reservation of miu_stage3 here because we use the average latency
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121 ;; time.
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122 (define_insn_reservation "ppc8540_divide" 14
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123 (and (eq_attr "type" "div")
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124 (eq_attr "cpu" "ppc8540,ppc8548"))
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125 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
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126 ppc8540_mu_div*13")
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127
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128 ;; CR logical
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129 (define_insn_reservation "ppc8540_cr_logical" 1
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130 (and (eq_attr "type" "cr_logical,delayed_cr")
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131 (eq_attr "cpu" "ppc8540,ppc8548"))
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132 "ppc8540_decode,ppc8540_bu,ppc8540_retire")
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133
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134 ;; Mfcr
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135 (define_insn_reservation "ppc8540_mfcr" 1
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136 (and (eq_attr "type" "mfcr")
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137 (eq_attr "cpu" "ppc8540,ppc8548"))
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138 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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139
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140 ;; Mtcrf
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141 (define_insn_reservation "ppc8540_mtcrf" 1
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142 (and (eq_attr "type" "mtcr")
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143 (eq_attr "cpu" "ppc8540,ppc8548"))
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144 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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145
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146 ;; Mtjmpr
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147 (define_insn_reservation "ppc8540_mtjmpr" 1
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148 (and (eq_attr "type" "mtjmpr,mfjmpr")
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149 (eq_attr "cpu" "ppc8540,ppc8548"))
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150 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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151
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152 ;; Loads
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153 (define_insn_reservation "ppc8540_load" 3
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154 (and (eq_attr "type" "load,load_l,sync")
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155 (eq_attr "cpu" "ppc8540,ppc8548"))
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156 "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
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157
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158 ;; Stores.
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159 (define_insn_reservation "ppc8540_store" 3
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160 (and (eq_attr "type" "store,store_c")
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161 (eq_attr "cpu" "ppc8540,ppc8548"))
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162 "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
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163
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164 ;; Simple FP
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165 (define_insn_reservation "ppc8540_simple_float" 1
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166 (and (eq_attr "type" "fpsimple")
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167 (eq_attr "cpu" "ppc8540,ppc8548"))
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168 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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169
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170 ;; FP
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171 (define_insn_reservation "ppc8540_float" 4
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172 (and (eq_attr "type" "fp")
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173 (eq_attr "cpu" "ppc8540,ppc8548"))
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174 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
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175 ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
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176
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177 ;; float divides. We omit reserving a retire unit and miu_stage3
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178 ;; because of the result automata will be huge.
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179 (define_insn_reservation "ppc8540_float_vector_divide" 29
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180 (and (eq_attr "type" "vecfdiv")
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181 (eq_attr "cpu" "ppc8540,ppc8548"))
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182 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
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183 ppc8540_mu_div*28")
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184
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185 ;; Simple vector
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186 (define_insn_reservation "ppc8540_simple_vector" 1
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187 (and (eq_attr "type" "vecsimple,veclogical,vecmove")
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188 (eq_attr "cpu" "ppc8540,ppc8548"))
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189 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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190
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191 ;; Simple vector compare
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192 (define_insn_reservation "ppc8540_simple_vector_compare" 1
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193 (and (eq_attr "type" "veccmpsimple")
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194 (eq_attr "cpu" "ppc8540,ppc8548"))
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195 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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196
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197 ;; Vector compare
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198 (define_insn_reservation "ppc8540_vector_compare" 1
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199 (and (eq_attr "type" "veccmp,veccmpfx")
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200 (eq_attr "cpu" "ppc8540,ppc8548"))
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201 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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202
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203 ;; evsplatfi evsplati
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204 (define_insn_reservation "ppc8540_vector_perm" 1
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205 (and (eq_attr "type" "vecperm")
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206 (eq_attr "cpu" "ppc8540,ppc8548"))
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207 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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208
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209 ;; Vector float
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210 (define_insn_reservation "ppc8540_float_vector" 4
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211 (and (eq_attr "type" "vecfloat")
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212 (eq_attr "cpu" "ppc8540,ppc8548"))
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213 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
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214 ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
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215
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216 ;; Vector divides: Use the average. We omit reserving a retire unit
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217 ;; because of the result automata will be huge. We ignore reservation
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218 ;; of miu_stage3 here because we use the average latency time.
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219 (define_insn_reservation "ppc8540_vector_divide" 14
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220 (and (eq_attr "type" "vecdiv")
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221 (eq_attr "cpu" "ppc8540,ppc8548"))
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222 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
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223 ppc8540_mu_div*13")
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224
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225 ;; Complex vector.
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226 (define_insn_reservation "ppc8540_complex_vector" 4
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227 (and (eq_attr "type" "veccomplex")
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228 (eq_attr "cpu" "ppc8540,ppc8548"))
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229 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
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230 ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
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231
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232 ;; Vector load
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233 (define_insn_reservation "ppc8540_vector_load" 3
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234 (and (eq_attr "type" "vecload")
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235 (eq_attr "cpu" "ppc8540,ppc8548"))
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236 "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
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237
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238 ;; Vector store
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239 (define_insn_reservation "ppc8540_vector_store" 3
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240 (and (eq_attr "type" "vecstore")
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241 (eq_attr "cpu" "ppc8540,ppc8548"))
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242 "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
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