Mercurial > hg > Members > kono > os9 > sbc09
annotate engine.c @ 10:2a1338b218bf
on going
| author | Shinji KONO <kono@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Thu, 05 Jul 2018 18:37:11 +0900 |
| parents | cb7aa75418b8 |
| children | ce7323f9b937 |
| rev | line source |
|---|---|
| 0 | 1 /* 6809 Simulator V09. |
| 2 | |
| 3 created 1994,1995 by L.C. Benschop. | |
| 4 copyleft (c) 1994-2014 by the sbc09 team, see AUTHORS for more details. | |
| 5 license: GNU General Public License version 2, see LICENSE for more details. | |
| 6 | |
| 7 This program simulates a 6809 processor. | |
| 8 | |
| 9 System dependencies: short must be 16 bits. | |
| 10 char must be 8 bits. | |
| 11 long must be more than 16 bits. | |
| 12 arrays up to 65536 bytes must be supported. | |
| 13 machine must be twos complement. | |
| 14 Most Unix machines will work. For MSODS you need long pointers | |
| 15 and you may have to malloc() the mem array of 65536 bytes. | |
| 16 | |
| 17 Special instructions: | |
| 18 SWI2 writes char to stdout from register B. | |
| 19 SWI3 reads char from stdout to register B, sets carry at EOF. | |
| 20 (or when no key available when using term control). | |
| 21 SWI retains its normal function. | |
| 22 CWAI and SYNC stop simulator. | |
| 23 Note: special instructions are gone for now. | |
| 24 | |
| 25 ACIA emulation at port $E000 | |
| 26 | |
| 27 Note: BIG_ENDIAN option is no longer needed. | |
| 28 */ | |
| 29 | |
| 30 #include <stdio.h> | |
| 31 #include <unistd.h> | |
| 32 | |
| 33 #define engine | |
| 34 #include "v09.h" | |
| 35 | |
| 36 #define USLEEP 1000 | |
| 37 Byte aca,acb; | |
| 38 Byte *breg=&aca,*areg=&acb; | |
| 39 static int tracetrick=0; | |
| 9 | 40 extern long romstart; |
| 0 | 41 |
| 4 | 42 #ifdef USE_MMU |
| 10 | 43 |
| 44 Byte dummy; | |
| 45 static Byte * mem0(Byte *iphymem, Word adr, Byte *immu) { | |
| 9 | 46 if (adr>=0xff00) return iphymem + memsize - 0x10000 + adr; // fixed area |
| 10 | 47 int addr = (immu[ (adr) >> 13 ] <<13 ) + ((adr) & 0x1fff ); |
| 48 if ( addr >= memsize ) { | |
| 49 dummy = 0; | |
| 50 return &dummy; | |
| 51 } | |
| 52 return & iphymem[ addr ]; | |
| 9 | 53 }; |
| 5 | 54 #define mem(adr) (*mem0(iphymem, adr,immu)) |
| 9 | 55 #define GETWORD(a) ({Byte *phy = mem0(iphymem, a,immu); phy[0]<<8|phy[1];}) |
| 56 #define SETBYTE(a,n) {Byte *phy = mem0(iphymem, a,immu); if(!(phy-iphymem>=romstart)) phy[0]=n;} | |
| 57 #define SETWORD(a,n) {Byte *phy = mem0(iphymem, a,immu); if(!(phy-iphymem>=romstart)){phy[0]=(n)>>8;phy[1]=n;}} | |
| 58 | |
| 59 Byte * mem1(Byte *iphymem, Word adr, Byte *immu) { return mem0(iphymem,adr,immu); } | |
| 60 | |
| 4 | 61 #else |
| 9 | 62 |
| 4 | 63 #define mem(adr) mem[adr] |
| 64 | |
| 65 #define GETWORD(a) (mem(a)<<8|mem((a)+1)) | |
| 66 #define SETBYTE(a,n) {if(!(a>=romstart))mem(a)=n;} | |
| 67 #define SETWORD(a,n) if(!(a>=romstart)){mem(a)=(n)>>8;mem((a)+1)=n;} | |
| 9 | 68 |
| 69 #endif | |
| 70 | |
| 0 | 71 /* Two bytes of a word are fetched separately because of |
| 72 the possible wrap-around at address $ffff and alignment | |
| 73 */ | |
| 74 | |
| 4 | 75 #define IMMBYTE(b) b=mem(ipcreg++); |
| 0 | 76 #define IMMWORD(w) {w=GETWORD(ipcreg);ipcreg+=2;} |
| 77 | |
| 78 #define PUSHBYTE(b) {--isreg;SETBYTE(isreg,b)} | |
| 79 #define PUSHWORD(w) {isreg-=2;SETWORD(isreg,w)} | |
| 4 | 80 #define PULLBYTE(b) b=mem(isreg++); |
| 0 | 81 #define PULLWORD(w) {w=GETWORD(isreg);isreg+=2;} |
| 82 #define PSHUBYTE(b) {--iureg;SETBYTE(iureg,b)} | |
| 83 #define PSHUWORD(w) {iureg-=2;SETWORD(iureg,w)} | |
| 4 | 84 #define PULUBYTE(b) b=mem(iureg++); |
| 0 | 85 #define PULUWORD(w) {w=GETWORD(iureg);iureg+=2;} |
| 86 | |
| 87 #define SIGNED(b) ((Word)(b&0x80?b|0xff00:b)) | |
| 88 | |
| 89 #define GETDREG ((iareg<<8)|ibreg) | |
| 90 #define SETDREG(n) {iareg=(n)>>8;ibreg=(n);} | |
| 91 | |
| 92 /* Macros for addressing modes (postbytes have their own code) */ | |
| 93 #define DIRECT {IMMBYTE(eaddr) eaddr|=(idpreg<<8);} | |
| 94 #define IMM8 {eaddr=ipcreg++;} | |
| 95 #define IMM16 {eaddr=ipcreg;ipcreg+=2;} | |
| 96 #define EXTENDED {IMMWORD(eaddr)} | |
| 97 | |
| 98 /* macros to set status flags */ | |
| 99 #define SEC iccreg|=0x01; | |
| 100 #define CLC iccreg&=0xfe; | |
| 101 #define SEZ iccreg|=0x04; | |
| 102 #define CLZ iccreg&=0xfb; | |
| 103 #define SEN iccreg|=0x08; | |
| 104 #define CLN iccreg&=0xf7; | |
| 105 #define SEV iccreg|=0x02; | |
| 106 #define CLV iccreg&=0xfd; | |
| 107 #define SEH iccreg|=0x20; | |
| 108 #define CLH iccreg&=0xdf; | |
| 109 | |
| 110 /* set N and Z flags depending on 8 or 16 bit result */ | |
| 111 #define SETNZ8(b) {if(b)CLZ else SEZ if(b&0x80)SEN else CLN} | |
| 112 #define SETNZ16(b) {if(b)CLZ else SEZ if(b&0x8000)SEN else CLN} | |
| 113 | |
| 114 #define SETSTATUS(a,b,res) if((a^b^res)&0x10) SEH else CLH \ | |
| 115 if((a^b^res^(res>>1))&0x80)SEV else CLV \ | |
| 116 if(res&0x100)SEC else CLC SETNZ8((Byte)res) | |
| 117 | |
| 118 #define SETSTATUSD(a,b,res) {if(res&0x10000) SEC else CLC \ | |
| 119 if(((res>>1)^a^b^res)&0x8000) SEV else CLV \ | |
| 120 SETNZ16((Word)res)} | |
| 121 | |
| 122 /* Macros for branch instructions */ | |
| 123 #define BRANCH(f) if(!iflag){IMMBYTE(tb) if(f)ipcreg+=SIGNED(tb);}\ | |
| 124 else{IMMWORD(tw) if(f)ipcreg+=tw;} | |
| 125 #define NXORV ((iccreg&0x08)^((iccreg&0x02)<<2)) | |
| 126 | |
| 127 /* MAcros for setting/getting registers in TFR/EXG instructions */ | |
| 128 #define GETREG(val,reg) switch(reg) {\ | |
| 129 case 0: val=GETDREG;break;\ | |
| 130 case 1: val=ixreg;break;\ | |
| 131 case 2: val=iyreg;break;\ | |
| 132 case 3: val=iureg;break;\ | |
| 133 case 4: val=isreg;break;\ | |
| 134 case 5: val=ipcreg;break;\ | |
| 135 case 8: val=iareg;break;\ | |
| 136 case 9: val=ibreg;break;\ | |
| 137 case 10: val=iccreg;break;\ | |
| 138 case 11: val=idpreg;break;} | |
| 139 | |
| 140 #define SETREG(val,reg) switch(reg) {\ | |
| 141 case 0: SETDREG(val) break;\ | |
| 142 case 1: ixreg=val;break;\ | |
| 143 case 2: iyreg=val;break;\ | |
| 144 case 3: iureg=val;break;\ | |
| 145 case 4: isreg=val;break;\ | |
| 146 case 5: ipcreg=val;break;\ | |
| 147 case 8: iareg=val;break;\ | |
| 148 case 9: ibreg=val;break;\ | |
| 149 case 10: iccreg=val;break;\ | |
| 150 case 11: idpreg=val;break;} | |
| 151 | |
| 152 /* Macros for load and store of accumulators. Can be modified to check | |
| 153 for port addresses */ | |
|
7
a6db579d8c11
level 2 rom preparing...
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents:
5
diff
changeset
|
154 #define LOADAC(reg) if((eaddr&0xff00)!=(IOPAGE&0xff00))reg=mem(eaddr);else\ |
| 0 | 155 reg=do_input(eaddr&0xff); |
|
7
a6db579d8c11
level 2 rom preparing...
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents:
5
diff
changeset
|
156 #define STOREAC(reg) if((eaddr&0xff00)!=(IOPAGE&0xff00))SETBYTE(eaddr,reg)else\ |
| 0 | 157 do_output(eaddr&0xff,reg); |
| 158 | |
| 159 #define LOADREGS ixreg=xreg;iyreg=yreg;\ | |
| 160 iureg=ureg;isreg=sreg;\ | |
| 161 ipcreg=pcreg;\ | |
| 162 iareg=*areg;ibreg=*breg;\ | |
| 4 | 163 idpreg=dpreg;iccreg=ccreg;immu=mmu; |
| 0 | 164 |
| 165 #define SAVEREGS xreg=ixreg;yreg=iyreg;\ | |
| 166 ureg=iureg;sreg=isreg;\ | |
| 167 pcreg=ipcreg;\ | |
| 168 *areg=iareg;*breg=ibreg;\ | |
| 4 | 169 dpreg=idpreg;ccreg=iccreg;mmu=immu; |
| 0 | 170 |
| 171 | |
| 172 unsigned char haspostbyte[] = { | |
| 173 /*0*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 174 /*1*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 175 /*2*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 176 /*3*/ 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 177 /*4*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 178 /*5*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 179 /*6*/ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, | |
| 180 /*7*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 181 /*8*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 182 /*9*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 183 /*A*/ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, | |
| 184 /*B*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 185 /*C*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 186 /*D*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 187 /*E*/ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, | |
| 188 /*F*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 189 }; | |
| 190 | |
| 9 | 191 extern char *prog ; |
| 192 | |
| 0 | 193 void interpr(void) |
| 194 { | |
| 195 Word ixreg,iyreg,iureg,isreg,ipcreg; | |
| 196 Byte idpreg,iccreg,iareg,ibreg; | |
| 197 /* Make local variables for the registers. On a real processor (non-Intel) | |
| 198 these could be implemented as fast registers. */ | |
| 199 Word eaddr; /* effective address */ | |
| 200 Byte ireg; /* instruction register */ | |
| 201 Byte iflag; /* flag to indicate $10 or $11 prebyte */ | |
| 202 Byte tb;Word tw; | |
| 4 | 203 Byte *immu = 0; |
| 204 #ifdef USE_MMU | |
| 205 const int imemsize = memsize; | |
| 206 Byte *iphymem = (Byte *)phymem; | |
| 207 immu = iphymem + imemsize - 0x10000 + 0xffa0; | |
| 208 #endif | |
| 0 | 209 LOADREGS |
| 210 for(;;){ | |
| 211 if(attention) { | |
| 9 | 212 if(tracing && ipcreg>=tracelo && ipcreg<=tracehi) { |
| 213 SAVEREGS | |
| 214 #ifdef USE_MMU | |
| 215 Byte *phyadr = &mem(pcreg); | |
| 216 prog = (char *)(phyadr - pcreg); | |
| 217 #endif | |
| 218 do_trace(tracefile); | |
| 219 } | |
| 0 | 220 if(escape){ SAVEREGS do_escape(); LOADREGS } |
| 221 if(irq) { | |
| 222 if(irq==1&&!(iccreg&0x10)) { /* standard IRQ */ | |
| 223 PUSHWORD(ipcreg) | |
| 224 PUSHWORD(iureg) | |
| 225 PUSHWORD(iyreg) | |
| 226 PUSHWORD(ixreg) | |
| 227 PUSHBYTE(idpreg) | |
| 228 PUSHBYTE(ibreg) | |
| 229 PUSHBYTE(iareg) | |
| 230 PUSHBYTE(iccreg) | |
| 231 iccreg|=0x90; | |
| 232 ipcreg=GETWORD(0xfff8); | |
| 233 } | |
| 234 if(irq==2&&!(iccreg&0x40)) { /* Fast IRQ */ | |
| 235 PUSHWORD(ipcreg) | |
| 236 PUSHBYTE(iccreg) | |
| 237 iccreg&=0x7f; | |
| 238 iccreg|=0x50; | |
| 239 ipcreg=GETWORD(0xfff6); | |
| 240 } | |
| 241 if(!tracing)attention=0; | |
| 242 irq=0; | |
| 243 } | |
| 244 } | |
| 245 iflag=0; | |
| 246 flaginstr: /* $10 and $11 instructions return here */ | |
| 4 | 247 ireg=mem(ipcreg++); |
| 0 | 248 if(haspostbyte[ireg]) { |
| 4 | 249 Byte postbyte=mem(ipcreg++); |
| 0 | 250 switch(postbyte) { |
| 251 case 0x00: eaddr=ixreg;break; | |
| 252 case 0x01: eaddr=ixreg+1;break; | |
| 253 case 0x02: eaddr=ixreg+2;break; | |
| 254 case 0x03: eaddr=ixreg+3;break; | |
| 255 case 0x04: eaddr=ixreg+4;break; | |
| 256 case 0x05: eaddr=ixreg+5;break; | |
| 257 case 0x06: eaddr=ixreg+6;break; | |
| 258 case 0x07: eaddr=ixreg+7;break; | |
| 259 case 0x08: eaddr=ixreg+8;break; | |
| 260 case 0x09: eaddr=ixreg+9;break; | |
| 261 case 0x0A: eaddr=ixreg+10;break; | |
| 262 case 0x0B: eaddr=ixreg+11;break; | |
| 263 case 0x0C: eaddr=ixreg+12;break; | |
| 264 case 0x0D: eaddr=ixreg+13;break; | |
| 265 case 0x0E: eaddr=ixreg+14;break; | |
| 266 case 0x0F: eaddr=ixreg+15;break; | |
| 267 case 0x10: eaddr=ixreg-16;break; | |
| 268 case 0x11: eaddr=ixreg-15;break; | |
| 269 case 0x12: eaddr=ixreg-14;break; | |
| 270 case 0x13: eaddr=ixreg-13;break; | |
| 271 case 0x14: eaddr=ixreg-12;break; | |
| 272 case 0x15: eaddr=ixreg-11;break; | |
| 273 case 0x16: eaddr=ixreg-10;break; | |
| 274 case 0x17: eaddr=ixreg-9;break; | |
| 275 case 0x18: eaddr=ixreg-8;break; | |
| 276 case 0x19: eaddr=ixreg-7;break; | |
| 277 case 0x1A: eaddr=ixreg-6;break; | |
| 278 case 0x1B: eaddr=ixreg-5;break; | |
| 279 case 0x1C: eaddr=ixreg-4;break; | |
| 280 case 0x1D: eaddr=ixreg-3;break; | |
| 281 case 0x1E: eaddr=ixreg-2;break; | |
| 282 case 0x1F: eaddr=ixreg-1;break; | |
| 283 case 0x20: eaddr=iyreg;break; | |
| 284 case 0x21: eaddr=iyreg+1;break; | |
| 285 case 0x22: eaddr=iyreg+2;break; | |
| 286 case 0x23: eaddr=iyreg+3;break; | |
| 287 case 0x24: eaddr=iyreg+4;break; | |
| 288 case 0x25: eaddr=iyreg+5;break; | |
| 289 case 0x26: eaddr=iyreg+6;break; | |
| 290 case 0x27: eaddr=iyreg+7;break; | |
| 291 case 0x28: eaddr=iyreg+8;break; | |
| 292 case 0x29: eaddr=iyreg+9;break; | |
| 293 case 0x2A: eaddr=iyreg+10;break; | |
| 294 case 0x2B: eaddr=iyreg+11;break; | |
| 295 case 0x2C: eaddr=iyreg+12;break; | |
| 296 case 0x2D: eaddr=iyreg+13;break; | |
| 297 case 0x2E: eaddr=iyreg+14;break; | |
| 298 case 0x2F: eaddr=iyreg+15;break; | |
| 299 case 0x30: eaddr=iyreg-16;break; | |
| 300 case 0x31: eaddr=iyreg-15;break; | |
| 301 case 0x32: eaddr=iyreg-14;break; | |
| 302 case 0x33: eaddr=iyreg-13;break; | |
| 303 case 0x34: eaddr=iyreg-12;break; | |
| 304 case 0x35: eaddr=iyreg-11;break; | |
| 305 case 0x36: eaddr=iyreg-10;break; | |
| 306 case 0x37: eaddr=iyreg-9;break; | |
| 307 case 0x38: eaddr=iyreg-8;break; | |
| 308 case 0x39: eaddr=iyreg-7;break; | |
| 309 case 0x3A: eaddr=iyreg-6;break; | |
| 310 case 0x3B: eaddr=iyreg-5;break; | |
| 311 case 0x3C: eaddr=iyreg-4;break; | |
| 312 case 0x3D: eaddr=iyreg-3;break; | |
| 313 case 0x3E: eaddr=iyreg-2;break; | |
| 314 case 0x3F: eaddr=iyreg-1;break; | |
| 315 case 0x40: eaddr=iureg;break; | |
| 316 case 0x41: eaddr=iureg+1;break; | |
| 317 case 0x42: eaddr=iureg+2;break; | |
| 318 case 0x43: eaddr=iureg+3;break; | |
| 319 case 0x44: eaddr=iureg+4;break; | |
| 320 case 0x45: eaddr=iureg+5;break; | |
| 321 case 0x46: eaddr=iureg+6;break; | |
| 322 case 0x47: eaddr=iureg+7;break; | |
| 323 case 0x48: eaddr=iureg+8;break; | |
| 324 case 0x49: eaddr=iureg+9;break; | |
| 325 case 0x4A: eaddr=iureg+10;break; | |
| 326 case 0x4B: eaddr=iureg+11;break; | |
| 327 case 0x4C: eaddr=iureg+12;break; | |
| 328 case 0x4D: eaddr=iureg+13;break; | |
| 329 case 0x4E: eaddr=iureg+14;break; | |
| 330 case 0x4F: eaddr=iureg+15;break; | |
| 331 case 0x50: eaddr=iureg-16;break; | |
| 332 case 0x51: eaddr=iureg-15;break; | |
| 333 case 0x52: eaddr=iureg-14;break; | |
| 334 case 0x53: eaddr=iureg-13;break; | |
| 335 case 0x54: eaddr=iureg-12;break; | |
| 336 case 0x55: eaddr=iureg-11;break; | |
| 337 case 0x56: eaddr=iureg-10;break; | |
| 338 case 0x57: eaddr=iureg-9;break; | |
| 339 case 0x58: eaddr=iureg-8;break; | |
| 340 case 0x59: eaddr=iureg-7;break; | |
| 341 case 0x5A: eaddr=iureg-6;break; | |
| 342 case 0x5B: eaddr=iureg-5;break; | |
| 343 case 0x5C: eaddr=iureg-4;break; | |
| 344 case 0x5D: eaddr=iureg-3;break; | |
| 345 case 0x5E: eaddr=iureg-2;break; | |
| 346 case 0x5F: eaddr=iureg-1;break; | |
| 347 case 0x60: eaddr=isreg;break; | |
| 348 case 0x61: eaddr=isreg+1;break; | |
| 349 case 0x62: eaddr=isreg+2;break; | |
| 350 case 0x63: eaddr=isreg+3;break; | |
| 351 case 0x64: eaddr=isreg+4;break; | |
| 352 case 0x65: eaddr=isreg+5;break; | |
| 353 case 0x66: eaddr=isreg+6;break; | |
| 354 case 0x67: eaddr=isreg+7;break; | |
| 355 case 0x68: eaddr=isreg+8;break; | |
| 356 case 0x69: eaddr=isreg+9;break; | |
| 357 case 0x6A: eaddr=isreg+10;break; | |
| 358 case 0x6B: eaddr=isreg+11;break; | |
| 359 case 0x6C: eaddr=isreg+12;break; | |
| 360 case 0x6D: eaddr=isreg+13;break; | |
| 361 case 0x6E: eaddr=isreg+14;break; | |
| 362 case 0x6F: eaddr=isreg+15;break; | |
| 363 case 0x70: eaddr=isreg-16;break; | |
| 364 case 0x71: eaddr=isreg-15;break; | |
| 365 case 0x72: eaddr=isreg-14;break; | |
| 366 case 0x73: eaddr=isreg-13;break; | |
| 367 case 0x74: eaddr=isreg-12;break; | |
| 368 case 0x75: eaddr=isreg-11;break; | |
| 369 case 0x76: eaddr=isreg-10;break; | |
| 370 case 0x77: eaddr=isreg-9;break; | |
| 371 case 0x78: eaddr=isreg-8;break; | |
| 372 case 0x79: eaddr=isreg-7;break; | |
| 373 case 0x7A: eaddr=isreg-6;break; | |
| 374 case 0x7B: eaddr=isreg-5;break; | |
| 375 case 0x7C: eaddr=isreg-4;break; | |
| 376 case 0x7D: eaddr=isreg-3;break; | |
| 377 case 0x7E: eaddr=isreg-2;break; | |
| 378 case 0x7F: eaddr=isreg-1;break; | |
| 379 case 0x80: eaddr=ixreg;ixreg++;break; | |
| 380 case 0x81: eaddr=ixreg;ixreg+=2;break; | |
| 381 case 0x82: ixreg--;eaddr=ixreg;break; | |
| 382 case 0x83: ixreg-=2;eaddr=ixreg;break; | |
| 383 case 0x84: eaddr=ixreg;break; | |
| 384 case 0x85: eaddr=ixreg+SIGNED(ibreg);break; | |
| 385 case 0x86: eaddr=ixreg+SIGNED(iareg);break; | |
| 386 case 0x87: eaddr=0;break; /*ILELGAL*/ | |
| 387 case 0x88: IMMBYTE(eaddr);eaddr=ixreg+SIGNED(eaddr);break; | |
| 388 case 0x89: IMMWORD(eaddr);eaddr+=ixreg;break; | |
| 389 case 0x8A: eaddr=0;break; /*ILLEGAL*/ | |
| 390 case 0x8B: eaddr=ixreg+GETDREG;break; | |
| 391 case 0x8C: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break; | |
| 392 case 0x8D: IMMWORD(eaddr);eaddr+=ipcreg;break; | |
| 393 case 0x8E: eaddr=0;break; /*ILLEGAL*/ | |
| 394 case 0x8F: IMMWORD(eaddr);break; | |
| 395 case 0x90: eaddr=ixreg;ixreg++;eaddr=GETWORD(eaddr);break; | |
| 396 case 0x91: eaddr=ixreg;ixreg+=2;eaddr=GETWORD(eaddr);break; | |
| 397 case 0x92: ixreg--;eaddr=ixreg;eaddr=GETWORD(eaddr);break; | |
| 398 case 0x93: ixreg-=2;eaddr=ixreg;eaddr=GETWORD(eaddr);break; | |
| 399 case 0x94: eaddr=ixreg;eaddr=GETWORD(eaddr);break; | |
| 400 case 0x95: eaddr=ixreg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break; | |
| 401 case 0x96: eaddr=ixreg+SIGNED(iareg);eaddr=GETWORD(eaddr);break; | |
| 402 case 0x97: eaddr=0;break; /*ILELGAL*/ | |
| 403 case 0x98: IMMBYTE(eaddr);eaddr=ixreg+SIGNED(eaddr); | |
| 404 eaddr=GETWORD(eaddr);break; | |
| 405 case 0x99: IMMWORD(eaddr);eaddr+=ixreg;eaddr=GETWORD(eaddr);break; | |
| 406 case 0x9A: eaddr=0;break; /*ILLEGAL*/ | |
| 407 case 0x9B: eaddr=ixreg+GETDREG;eaddr=GETWORD(eaddr);break; | |
| 408 case 0x9C: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr); | |
| 409 eaddr=GETWORD(eaddr);break; | |
| 410 case 0x9D: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break; | |
| 411 case 0x9E: eaddr=0;break; /*ILLEGAL*/ | |
| 412 case 0x9F: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break; | |
| 413 case 0xA0: eaddr=iyreg;iyreg++;break; | |
| 414 case 0xA1: eaddr=iyreg;iyreg+=2;break; | |
| 415 case 0xA2: iyreg--;eaddr=iyreg;break; | |
| 416 case 0xA3: iyreg-=2;eaddr=iyreg;break; | |
| 417 case 0xA4: eaddr=iyreg;break; | |
| 418 case 0xA5: eaddr=iyreg+SIGNED(ibreg);break; | |
| 419 case 0xA6: eaddr=iyreg+SIGNED(iareg);break; | |
| 420 case 0xA7: eaddr=0;break; /*ILELGAL*/ | |
| 421 case 0xA8: IMMBYTE(eaddr);eaddr=iyreg+SIGNED(eaddr);break; | |
| 422 case 0xA9: IMMWORD(eaddr);eaddr+=iyreg;break; | |
| 423 case 0xAA: eaddr=0;break; /*ILLEGAL*/ | |
| 424 case 0xAB: eaddr=iyreg+GETDREG;break; | |
| 425 case 0xAC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break; | |
| 426 case 0xAD: IMMWORD(eaddr);eaddr+=ipcreg;break; | |
| 427 case 0xAE: eaddr=0;break; /*ILLEGAL*/ | |
| 428 case 0xAF: IMMWORD(eaddr);break; | |
| 429 case 0xB0: eaddr=iyreg;iyreg++;eaddr=GETWORD(eaddr);break; | |
| 430 case 0xB1: eaddr=iyreg;iyreg+=2;eaddr=GETWORD(eaddr);break; | |
| 431 case 0xB2: iyreg--;eaddr=iyreg;eaddr=GETWORD(eaddr);break; | |
| 432 case 0xB3: iyreg-=2;eaddr=iyreg;eaddr=GETWORD(eaddr);break; | |
| 433 case 0xB4: eaddr=iyreg;eaddr=GETWORD(eaddr);break; | |
| 434 case 0xB5: eaddr=iyreg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break; | |
| 435 case 0xB6: eaddr=iyreg+SIGNED(iareg);eaddr=GETWORD(eaddr);break; | |
| 436 case 0xB7: eaddr=0;break; /*ILELGAL*/ | |
| 437 case 0xB8: IMMBYTE(eaddr);eaddr=iyreg+SIGNED(eaddr); | |
| 438 eaddr=GETWORD(eaddr);break; | |
| 439 case 0xB9: IMMWORD(eaddr);eaddr+=iyreg;eaddr=GETWORD(eaddr);break; | |
| 440 case 0xBA: eaddr=0;break; /*ILLEGAL*/ | |
| 441 case 0xBB: eaddr=iyreg+GETDREG;eaddr=GETWORD(eaddr);break; | |
| 442 case 0xBC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr); | |
| 443 eaddr=GETWORD(eaddr);break; | |
| 444 case 0xBD: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break; | |
| 445 case 0xBE: eaddr=0;break; /*ILLEGAL*/ | |
| 446 case 0xBF: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break; | |
| 447 case 0xC0: eaddr=iureg;iureg++;break; | |
| 448 case 0xC1: eaddr=iureg;iureg+=2;break; | |
| 449 case 0xC2: iureg--;eaddr=iureg;break; | |
| 450 case 0xC3: iureg-=2;eaddr=iureg;break; | |
| 451 case 0xC4: eaddr=iureg;break; | |
| 452 case 0xC5: eaddr=iureg+SIGNED(ibreg);break; | |
| 453 case 0xC6: eaddr=iureg+SIGNED(iareg);break; | |
| 454 case 0xC7: eaddr=0;break; /*ILELGAL*/ | |
| 455 case 0xC8: IMMBYTE(eaddr);eaddr=iureg+SIGNED(eaddr);break; | |
| 456 case 0xC9: IMMWORD(eaddr);eaddr+=iureg;break; | |
| 457 case 0xCA: eaddr=0;break; /*ILLEGAL*/ | |
| 458 case 0xCB: eaddr=iureg+GETDREG;break; | |
| 459 case 0xCC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break; | |
| 460 case 0xCD: IMMWORD(eaddr);eaddr+=ipcreg;break; | |
| 461 case 0xCE: eaddr=0;break; /*ILLEGAL*/ | |
| 462 case 0xCF: IMMWORD(eaddr);break; | |
| 463 case 0xD0: eaddr=iureg;iureg++;eaddr=GETWORD(eaddr);break; | |
| 464 case 0xD1: eaddr=iureg;iureg+=2;eaddr=GETWORD(eaddr);break; | |
| 465 case 0xD2: iureg--;eaddr=iureg;eaddr=GETWORD(eaddr);break; | |
| 466 case 0xD3: iureg-=2;eaddr=iureg;eaddr=GETWORD(eaddr);break; | |
| 467 case 0xD4: eaddr=iureg;eaddr=GETWORD(eaddr);break; | |
| 468 case 0xD5: eaddr=iureg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break; | |
| 469 case 0xD6: eaddr=iureg+SIGNED(iareg);eaddr=GETWORD(eaddr);break; | |
| 470 case 0xD7: eaddr=0;break; /*ILELGAL*/ | |
| 471 case 0xD8: IMMBYTE(eaddr);eaddr=iureg+SIGNED(eaddr); | |
| 472 eaddr=GETWORD(eaddr);break; | |
| 473 case 0xD9: IMMWORD(eaddr);eaddr+=iureg;eaddr=GETWORD(eaddr);break; | |
| 474 case 0xDA: eaddr=0;break; /*ILLEGAL*/ | |
| 475 case 0xDB: eaddr=iureg+GETDREG;eaddr=GETWORD(eaddr);break; | |
| 476 case 0xDC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr); | |
| 477 eaddr=GETWORD(eaddr);break; | |
| 478 case 0xDD: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break; | |
| 479 case 0xDE: eaddr=0;break; /*ILLEGAL*/ | |
| 480 case 0xDF: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break; | |
| 481 case 0xE0: eaddr=isreg;isreg++;break; | |
| 482 case 0xE1: eaddr=isreg;isreg+=2;break; | |
| 483 case 0xE2: isreg--;eaddr=isreg;break; | |
| 484 case 0xE3: isreg-=2;eaddr=isreg;break; | |
| 485 case 0xE4: eaddr=isreg;break; | |
| 486 case 0xE5: eaddr=isreg+SIGNED(ibreg);break; | |
| 487 case 0xE6: eaddr=isreg+SIGNED(iareg);break; | |
| 488 case 0xE7: eaddr=0;break; /*ILELGAL*/ | |
| 489 case 0xE8: IMMBYTE(eaddr);eaddr=isreg+SIGNED(eaddr);break; | |
| 490 case 0xE9: IMMWORD(eaddr);eaddr+=isreg;break; | |
| 491 case 0xEA: eaddr=0;break; /*ILLEGAL*/ | |
| 492 case 0xEB: eaddr=isreg+GETDREG;break; | |
| 493 case 0xEC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break; | |
| 494 case 0xED: IMMWORD(eaddr);eaddr+=ipcreg;break; | |
| 495 case 0xEE: eaddr=0;break; /*ILLEGAL*/ | |
| 496 case 0xEF: IMMWORD(eaddr);break; | |
| 497 case 0xF0: eaddr=isreg;isreg++;eaddr=GETWORD(eaddr);break; | |
| 498 case 0xF1: eaddr=isreg;isreg+=2;eaddr=GETWORD(eaddr);break; | |
| 499 case 0xF2: isreg--;eaddr=isreg;eaddr=GETWORD(eaddr);break; | |
| 500 case 0xF3: isreg-=2;eaddr=isreg;eaddr=GETWORD(eaddr);break; | |
| 501 case 0xF4: eaddr=isreg;eaddr=GETWORD(eaddr);break; | |
| 502 case 0xF5: eaddr=isreg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break; | |
| 503 case 0xF6: eaddr=isreg+SIGNED(iareg);eaddr=GETWORD(eaddr);break; | |
| 504 case 0xF7: eaddr=0;break; /*ILELGAL*/ | |
| 505 case 0xF8: IMMBYTE(eaddr);eaddr=isreg+SIGNED(eaddr); | |
| 506 eaddr=GETWORD(eaddr);break; | |
| 507 case 0xF9: IMMWORD(eaddr);eaddr+=isreg;eaddr=GETWORD(eaddr);break; | |
| 508 case 0xFA: eaddr=0;break; /*ILLEGAL*/ | |
| 509 case 0xFB: eaddr=isreg+GETDREG;eaddr=GETWORD(eaddr);break; | |
| 510 case 0xFC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr); | |
| 511 eaddr=GETWORD(eaddr);break; | |
| 512 case 0xFD: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break; | |
| 513 case 0xFE: eaddr=0;break; /*ILLEGAL*/ | |
| 514 case 0xFF: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break; | |
| 515 } | |
| 516 } | |
| 517 switch(ireg) { | |
| 4 | 518 case 0x00: /*NEG direct*/ DIRECT tw=-mem(eaddr);SETSTATUS(0,mem(eaddr),tw) |
| 0 | 519 SETBYTE(eaddr,tw)break; |
| 520 case 0x01: break;/*ILLEGAL*/ | |
| 521 case 0x02: break;/*ILLEGAL*/ | |
| 4 | 522 case 0x03: /*COM direct*/ DIRECT tb=~mem(eaddr);SETNZ8(tb);SEC CLV |
| 0 | 523 SETBYTE(eaddr,tb)break; |
| 4 | 524 case 0x04: /*LSR direct*/ DIRECT tb=mem(eaddr);if(tb&0x01)SEC else CLC |
| 0 | 525 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb) |
| 526 SETBYTE(eaddr,tb)break; | |
| 527 case 0x05: break;/* ILLEGAL*/ | |
| 528 case 0x06: /*ROR direct*/ DIRECT tb=(iccreg&0x01)<<7; | |
| 4 | 529 if(mem(eaddr)&0x01)SEC else CLC |
| 530 tw=(mem(eaddr)>>1)+tb;SETNZ8(tw) | |
| 0 | 531 SETBYTE(eaddr,tw) |
| 532 break; | |
| 4 | 533 case 0x07: /*ASR direct*/ DIRECT tb=mem(eaddr);if(tb&0x01)SEC else CLC |
| 0 | 534 if(tb&0x10)SEH else CLH tb>>=1; |
| 535 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb) | |
| 536 break; | |
| 4 | 537 case 0x08: /*ASL direct*/ DIRECT tw=mem(eaddr)<<1; |
| 538 SETSTATUS(mem(eaddr),mem(eaddr),tw) | |
| 0 | 539 SETBYTE(eaddr,tw)break; |
| 4 | 540 case 0x09: /*ROL direct*/ DIRECT tb=mem(eaddr);tw=iccreg&0x01; |
| 0 | 541 if(tb&0x80)SEC else CLC |
| 542 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV | |
| 543 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break; | |
| 4 | 544 case 0x0A: /*DEC direct*/ DIRECT tb=mem(eaddr)-1;if(tb==0x7F)SEV else CLV |
| 0 | 545 SETNZ8(tb) SETBYTE(eaddr,tb)break; |
| 546 case 0x0B: break; /*ILLEGAL*/ | |
| 4 | 547 case 0x0C: /*INC direct*/ DIRECT tb=mem(eaddr)+1;if(tb==0x80)SEV else CLV |
| 0 | 548 SETNZ8(tb) SETBYTE(eaddr,tb)break; |
| 4 | 549 case 0x0D: /*TST direct*/ DIRECT tb=mem(eaddr);SETNZ8(tb) break; |
| 0 | 550 case 0x0E: /*JMP direct*/ DIRECT ipcreg=eaddr;break; |
| 551 case 0x0F: /*CLR direct*/ DIRECT SETBYTE(eaddr,0);CLN CLV SEZ CLC break; | |
| 552 case 0x10: /* flag10 */ iflag=1;goto flaginstr; | |
| 553 case 0x11: /* flag11 */ iflag=2;goto flaginstr; | |
| 554 case 0x12: /* NOP */ break; | |
| 555 case 0x13: /* SYNC */ | |
| 556 do usleep(USLEEP); /* Wait for IRQ */ | |
| 557 while(!irq && !attention); | |
| 558 if(iccreg&0x40)tracetrick=1; | |
| 559 break; | |
| 560 case 0x14: break; /*ILLEGAL*/ | |
| 561 case 0x15: break; /*ILLEGAL*/ | |
| 562 case 0x16: /*LBRA*/ IMMWORD(eaddr) ipcreg+=eaddr;break; | |
| 563 case 0x17: /*LBSR*/ IMMWORD(eaddr) PUSHWORD(ipcreg) ipcreg+=eaddr;break; | |
| 564 case 0x18: break; /*ILLEGAL*/ | |
| 565 case 0x19: /* DAA*/ tw=iareg; | |
| 566 if(iccreg&0x20)tw+=6; | |
| 567 if((tw&0x0f)>9)tw+=6; | |
| 568 if(iccreg&0x01)tw+=0x60; | |
| 569 if((tw&0xf0)>0x90)tw+=0x60; | |
| 570 if(tw&0x100)SEC | |
| 571 iareg=tw;break; | |
| 572 case 0x1A: /* ORCC*/ IMMBYTE(tb) iccreg|=tb;break; | |
| 573 case 0x1B: break; /*ILLEGAL*/ | |
| 574 case 0x1C: /* ANDCC*/ IMMBYTE(tb) iccreg&=tb;break; | |
| 575 case 0x1D: /* SEX */ tw=SIGNED(ibreg); SETNZ16(tw) SETDREG(tw) break; | |
| 576 case 0x1E: /* EXG */ IMMBYTE(tb) {Word t2;GETREG(tw,tb>>4) GETREG(t2,tb&15) | |
| 577 SETREG(t2,tb>>4) SETREG(tw,tb&15) } break; | |
| 578 case 0x1F: /* TFR */ IMMBYTE(tb) GETREG(tw,tb>>4) SETREG(tw,tb&15) break; | |
| 579 case 0x20: /* (L)BRA*/ BRANCH(1) break; | |
| 580 case 0x21: /* (L)BRN*/ BRANCH(0) break; | |
| 581 case 0x22: /* (L)BHI*/ BRANCH(!(iccreg&0x05)) break; | |
| 582 case 0x23: /* (L)BLS*/ BRANCH(iccreg&0x05) break; | |
| 583 case 0x24: /* (L)BCC*/ BRANCH(!(iccreg&0x01)) break; | |
| 584 case 0x25: /* (L)BCS*/ BRANCH(iccreg&0x01) break; | |
| 585 case 0x26: /* (L)BNE*/ BRANCH(!(iccreg&0x04)) break; | |
| 586 case 0x27: /* (L)BEQ*/ BRANCH(iccreg&0x04) break; | |
| 587 case 0x28: /* (L)BVC*/ BRANCH(!(iccreg&0x02)) break; | |
| 588 case 0x29: /* (L)BVS*/ BRANCH(iccreg&0x02) break; | |
| 589 case 0x2A: /* (L)BPL*/ BRANCH(!(iccreg&0x08)) break; | |
| 590 case 0x2B: /* (L)BMI*/ BRANCH(iccreg&0x08) break; | |
| 591 case 0x2C: /* (L)BGE*/ BRANCH(!NXORV) break; | |
| 592 case 0x2D: /* (L)BLT*/ BRANCH(NXORV) break; | |
| 593 case 0x2E: /* (L)BGT*/ BRANCH(!(NXORV||iccreg&0x04)) break; | |
| 594 case 0x2F: /* (L)BLE*/ BRANCH(NXORV||iccreg&0x04) break; | |
| 595 case 0x30: /* LEAX*/ ixreg=eaddr; if(ixreg) CLZ else SEZ break; | |
| 596 case 0x31: /* LEAY*/ iyreg=eaddr; if(iyreg) CLZ else SEZ break; | |
| 597 case 0x32: /* LEAS*/ isreg=eaddr;break; | |
| 598 case 0x33: /* LEAU*/ iureg=eaddr;break; | |
| 599 case 0x34: /* PSHS*/ IMMBYTE(tb) | |
| 600 if(tb&0x80)PUSHWORD(ipcreg) | |
| 601 if(tb&0x40)PUSHWORD(iureg) | |
| 602 if(tb&0x20)PUSHWORD(iyreg) | |
| 603 if(tb&0x10)PUSHWORD(ixreg) | |
| 604 if(tb&0x08)PUSHBYTE(idpreg) | |
| 605 if(tb&0x04)PUSHBYTE(ibreg) | |
| 606 if(tb&0x02)PUSHBYTE(iareg) | |
| 607 if(tb&0x01)PUSHBYTE(iccreg) break; | |
| 608 case 0x35: /* PULS*/ IMMBYTE(tb) | |
| 609 if(tb&0x01)PULLBYTE(iccreg) | |
| 610 if(tb&0x02)PULLBYTE(iareg) | |
| 611 if(tb&0x04)PULLBYTE(ibreg) | |
| 612 if(tb&0x08)PULLBYTE(idpreg) | |
| 613 if(tb&0x10)PULLWORD(ixreg) | |
| 614 if(tb&0x20)PULLWORD(iyreg) | |
| 615 if(tb&0x40)PULLWORD(iureg) | |
| 616 if(tb&0x80)PULLWORD(ipcreg) | |
| 617 if(tracetrick&&tb==0xff) { /* Arrange fake FIRQ after next insn | |
| 618 for hardware tracing */ | |
| 619 tracetrick=0; | |
| 620 irq=2; | |
| 621 attention=1; | |
| 622 goto flaginstr; | |
| 623 } | |
| 624 break; | |
| 625 case 0x36: /* PSHU*/ IMMBYTE(tb) | |
| 626 if(tb&0x80)PSHUWORD(ipcreg) | |
| 627 if(tb&0x40)PSHUWORD(isreg) | |
| 628 if(tb&0x20)PSHUWORD(iyreg) | |
| 629 if(tb&0x10)PSHUWORD(ixreg) | |
| 630 if(tb&0x08)PSHUBYTE(idpreg) | |
| 631 if(tb&0x04)PSHUBYTE(ibreg) | |
| 632 if(tb&0x02)PSHUBYTE(iareg) | |
| 633 if(tb&0x01)PSHUBYTE(iccreg) break; | |
| 634 case 0x37: /* PULU*/ IMMBYTE(tb) | |
| 635 if(tb&0x01)PULUBYTE(iccreg) | |
| 636 if(tb&0x02)PULUBYTE(iareg) | |
| 637 if(tb&0x04)PULUBYTE(ibreg) | |
| 638 if(tb&0x08)PULUBYTE(idpreg) | |
| 639 if(tb&0x10)PULUWORD(ixreg) | |
| 640 if(tb&0x20)PULUWORD(iyreg) | |
| 641 if(tb&0x40)PULUWORD(isreg) | |
| 642 if(tb&0x80)PULUWORD(ipcreg) break; | |
| 643 case 0x39: /* RTS*/ PULLWORD(ipcreg) break; | |
| 644 case 0x3A: /* ABX*/ ixreg+=ibreg; break; | |
| 645 case 0x3B: /* RTI*/ tb=iccreg&0x80; | |
| 646 PULLBYTE(iccreg) | |
| 647 if(tb) | |
| 648 { | |
| 649 PULLBYTE(iareg) | |
| 650 PULLBYTE(ibreg) | |
| 651 PULLBYTE(idpreg) | |
| 652 PULLWORD(ixreg) | |
| 653 PULLWORD(iyreg) | |
| 654 PULLWORD(iureg) | |
| 655 } | |
| 656 PULLWORD(ipcreg) break; | |
| 657 case 0x3C: /* CWAI*/ IMMBYTE(tb) | |
| 658 PUSHWORD(ipcreg) | |
| 659 PUSHWORD(iureg) | |
| 660 PUSHWORD(iyreg) | |
| 661 PUSHWORD(ixreg) | |
| 662 PUSHBYTE(idpreg) | |
| 663 PUSHBYTE(ibreg) | |
| 664 PUSHBYTE(iareg) | |
| 665 PUSHBYTE(iccreg) | |
| 666 iccreg&=tb; | |
| 667 iccreg|=0x80; | |
| 668 do usleep(USLEEP); /* Wait for IRQ */ | |
| 669 while(!attention && !((irq==1&&!(iccreg&0x10))||(irq==2&&!(iccreg&0x040)))); | |
| 670 if(irq==1)ipcreg=GETWORD(0xfff8); | |
| 671 else ipcreg=GETWORD(0xfff6); | |
| 672 irq=0; | |
| 673 if(!tracing)attention=0; | |
| 674 break; | |
| 675 case 0x3D: /* MUL*/ tw=iareg*ibreg; if(tw)CLZ else SEZ | |
| 676 if(tw&0x80) SEC else CLC SETDREG(tw) break; | |
| 677 case 0x3E: break; /*ILLEGAL*/ | |
| 678 case 0x3F: /* SWI (SWI2 SWI3)*/ { | |
| 679 PUSHWORD(ipcreg) | |
| 680 PUSHWORD(iureg) | |
| 681 PUSHWORD(iyreg) | |
| 682 PUSHWORD(ixreg) | |
| 683 PUSHBYTE(idpreg) | |
| 684 PUSHBYTE(ibreg) | |
| 685 PUSHBYTE(iareg) | |
| 686 PUSHBYTE(iccreg) | |
| 687 iccreg|=0x80; | |
| 688 if(!iflag)iccreg|=0x50; | |
| 689 switch(iflag) { | |
| 690 case 0:ipcreg=GETWORD(0xfffa);break; | |
| 691 case 1:ipcreg=GETWORD(0xfff4);break; | |
| 692 case 2:ipcreg=GETWORD(0xfff2);break; | |
| 693 } | |
| 694 }break; | |
| 695 case 0x40: /*NEGA*/ tw=-iareg;SETSTATUS(0,iareg,tw) | |
| 696 iareg=tw;break; | |
| 697 case 0x41: break;/*ILLEGAL*/ | |
| 698 case 0x42: break;/*ILLEGAL*/ | |
| 699 case 0x43: /*COMA*/ tb=~iareg;SETNZ8(tb);SEC CLV | |
| 700 iareg=tb;break; | |
| 701 case 0x44: /*LSRA*/ tb=iareg;if(tb&0x01)SEC else CLC | |
| 702 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb) | |
| 703 iareg=tb;break; | |
| 704 case 0x45: break;/* ILLEGAL*/ | |
| 705 case 0x46: /*RORA*/ tb=(iccreg&0x01)<<7; | |
| 706 if(iareg&0x01)SEC else CLC | |
| 707 iareg=(iareg>>1)+tb;SETNZ8(iareg) | |
| 708 break; | |
| 709 case 0x47: /*ASRA*/ tb=iareg;if(tb&0x01)SEC else CLC | |
| 710 if(tb&0x10)SEH else CLH tb>>=1; | |
| 711 if(tb&0x40)tb|=0x80;iareg=tb;SETNZ8(tb) | |
| 712 break; | |
| 713 case 0x48: /*ASLA*/ tw=iareg<<1; | |
| 714 SETSTATUS(iareg,iareg,tw) | |
| 715 iareg=tw;break; | |
| 716 case 0x49: /*ROLA*/ tb=iareg;tw=iccreg&0x01; | |
| 717 if(tb&0x80)SEC else CLC | |
| 718 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV | |
| 719 tb=(tb<<1)+tw;SETNZ8(tb) iareg=tb;break; | |
| 720 case 0x4A: /*DECA*/ tb=iareg-1;if(tb==0x7F)SEV else CLV | |
| 721 SETNZ8(tb) iareg=tb;break; | |
| 722 case 0x4B: break; /*ILLEGAL*/ | |
| 723 case 0x4C: /*INCA*/ tb=iareg+1;if(tb==0x80)SEV else CLV | |
| 724 SETNZ8(tb) iareg=tb;break; | |
| 725 case 0x4D: /*TSTA*/ SETNZ8(iareg) break; | |
| 726 case 0x4E: break; /*ILLEGAL*/ | |
| 727 case 0x4F: /*CLRA*/ iareg=0;CLN CLV SEZ CLC break; | |
| 728 case 0x50: /*NEGB*/ tw=-ibreg;SETSTATUS(0,ibreg,tw) | |
| 729 ibreg=tw;break; | |
| 730 case 0x51: break;/*ILLEGAL*/ | |
| 731 case 0x52: break;/*ILLEGAL*/ | |
| 732 case 0x53: /*COMB*/ tb=~ibreg;SETNZ8(tb);SEC CLV | |
| 733 ibreg=tb;break; | |
| 734 case 0x54: /*LSRB*/ tb=ibreg;if(tb&0x01)SEC else CLC | |
| 735 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb) | |
| 736 ibreg=tb;break; | |
| 737 case 0x55: break;/* ILLEGAL*/ | |
| 738 case 0x56: /*RORB*/ tb=(iccreg&0x01)<<7; | |
| 739 if(ibreg&0x01)SEC else CLC | |
| 740 ibreg=(ibreg>>1)+tb;SETNZ8(ibreg) | |
| 741 break; | |
| 742 case 0x57: /*ASRB*/ tb=ibreg;if(tb&0x01)SEC else CLC | |
| 743 if(tb&0x10)SEH else CLH tb>>=1; | |
| 744 if(tb&0x40)tb|=0x80;ibreg=tb;SETNZ8(tb) | |
| 745 break; | |
| 746 case 0x58: /*ASLB*/ tw=ibreg<<1; | |
| 747 SETSTATUS(ibreg,ibreg,tw) | |
| 748 ibreg=tw;break; | |
| 749 case 0x59: /*ROLB*/ tb=ibreg;tw=iccreg&0x01; | |
| 750 if(tb&0x80)SEC else CLC | |
| 751 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV | |
| 752 tb=(tb<<1)+tw;SETNZ8(tb) ibreg=tb;break; | |
| 753 case 0x5A: /*DECB*/ tb=ibreg-1;if(tb==0x7F)SEV else CLV | |
| 754 SETNZ8(tb) ibreg=tb;break; | |
| 755 case 0x5B: break; /*ILLEGAL*/ | |
| 756 case 0x5C: /*INCB*/ tb=ibreg+1;if(tb==0x80)SEV else CLV | |
| 757 SETNZ8(tb) ibreg=tb;break; | |
| 758 case 0x5D: /*TSTB*/ SETNZ8(ibreg) break; | |
| 759 case 0x5E: break; /*ILLEGAL*/ | |
| 760 case 0x5F: /*CLRB*/ ibreg=0;CLN CLV SEZ CLC break; | |
| 4 | 761 case 0x60: /*NEG indexed*/ tw=-mem(eaddr);SETSTATUS(0,mem(eaddr),tw) |
| 0 | 762 SETBYTE(eaddr,tw)break; |
| 763 case 0x61: break;/*ILLEGAL*/ | |
| 764 case 0x62: break;/*ILLEGAL*/ | |
| 4 | 765 case 0x63: /*COM indexed*/ tb=~mem(eaddr);SETNZ8(tb);SEC CLV |
| 0 | 766 SETBYTE(eaddr,tb)break; |
| 4 | 767 case 0x64: /*LSR indexed*/ tb=mem(eaddr);if(tb&0x01)SEC else CLC |
| 0 | 768 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb) |
| 769 SETBYTE(eaddr,tb)break; | |
| 770 case 0x65: break;/* ILLEGAL*/ | |
| 771 case 0x66: /*ROR indexed*/ tb=(iccreg&0x01)<<7; | |
| 4 | 772 if(mem(eaddr)&0x01)SEC else CLC |
| 773 tw=(mem(eaddr)>>1)+tb;SETNZ8(tw) | |
| 0 | 774 SETBYTE(eaddr,tw) |
| 775 break; | |
| 4 | 776 case 0x67: /*ASR indexed*/ tb=mem(eaddr);if(tb&0x01)SEC else CLC |
| 0 | 777 if(tb&0x10)SEH else CLH tb>>=1; |
| 778 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb) | |
| 779 break; | |
| 4 | 780 case 0x68: /*ASL indexed*/ tw=mem(eaddr)<<1; |
| 781 SETSTATUS(mem(eaddr),mem(eaddr),tw) | |
| 0 | 782 SETBYTE(eaddr,tw)break; |
| 4 | 783 case 0x69: /*ROL indexed*/ tb=mem(eaddr);tw=iccreg&0x01; |
| 0 | 784 if(tb&0x80)SEC else CLC |
| 785 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV | |
| 786 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break; | |
| 4 | 787 case 0x6A: /*DEC indexed*/ tb=mem(eaddr)-1;if(tb==0x7F)SEV else CLV |
| 0 | 788 SETNZ8(tb) SETBYTE(eaddr,tb)break; |
| 789 case 0x6B: break; /*ILLEGAL*/ | |
| 4 | 790 case 0x6C: /*INC indexed*/ tb=mem(eaddr)+1;if(tb==0x80)SEV else CLV |
| 0 | 791 SETNZ8(tb) SETBYTE(eaddr,tb)break; |
| 4 | 792 case 0x6D: /*TST indexed*/ tb=mem(eaddr);SETNZ8(tb) break; |
| 0 | 793 case 0x6E: /*JMP indexed*/ ipcreg=eaddr;break; |
| 794 case 0x6F: /*CLR indexed*/ SETBYTE(eaddr,0)CLN CLV SEZ CLC break; | |
| 4 | 795 case 0x70: /*NEG ext*/ EXTENDED tw=-mem(eaddr);SETSTATUS(0,mem(eaddr),tw) |
| 0 | 796 SETBYTE(eaddr,tw)break; |
| 797 case 0x71: break;/*ILLEGAL*/ | |
| 798 case 0x72: break;/*ILLEGAL*/ | |
| 4 | 799 case 0x73: /*COM ext*/ EXTENDED tb=~mem(eaddr);SETNZ8(tb);SEC CLV |
| 0 | 800 SETBYTE(eaddr,tb)break; |
| 4 | 801 case 0x74: /*LSR ext*/ EXTENDED tb=mem(eaddr);if(tb&0x01)SEC else CLC |
| 0 | 802 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb) |
| 803 SETBYTE(eaddr,tb)break; | |
| 804 case 0x75: break;/* ILLEGAL*/ | |
| 805 case 0x76: /*ROR ext*/ EXTENDED tb=(iccreg&0x01)<<7; | |
| 4 | 806 if(mem(eaddr)&0x01)SEC else CLC |
| 807 tw=(mem(eaddr)>>1)+tb;SETNZ8(tw) | |
| 0 | 808 SETBYTE(eaddr,tw) |
| 809 break; | |
| 4 | 810 case 0x77: /*ASR ext*/ EXTENDED tb=mem(eaddr);if(tb&0x01)SEC else CLC |
| 0 | 811 if(tb&0x10)SEH else CLH tb>>=1; |
| 812 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb) | |
| 813 break; | |
| 4 | 814 case 0x78: /*ASL ext*/ EXTENDED tw=mem(eaddr)<<1; |
| 815 SETSTATUS(mem(eaddr),mem(eaddr),tw) | |
| 0 | 816 SETBYTE(eaddr,tw)break; |
| 4 | 817 case 0x79: /*ROL ext*/ EXTENDED tb=mem(eaddr);tw=iccreg&0x01; |
| 0 | 818 if(tb&0x80)SEC else CLC |
| 819 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV | |
| 820 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break; | |
| 4 | 821 case 0x7A: /*DEC ext*/ EXTENDED tb=mem(eaddr)-1;if(tb==0x7F)SEV else CLV |
| 0 | 822 SETNZ8(tb) SETBYTE(eaddr,tb)break; |
| 823 case 0x7B: break; /*ILLEGAL*/ | |
| 4 | 824 case 0x7C: /*INC ext*/ EXTENDED tb=mem(eaddr)+1;if(tb==0x80)SEV else CLV |
| 0 | 825 SETNZ8(tb) SETBYTE(eaddr,tb)break; |
| 4 | 826 case 0x7D: /*TST ext*/ EXTENDED tb=mem(eaddr);SETNZ8(tb) break; |
| 0 | 827 case 0x7E: /*JMP ext*/ EXTENDED ipcreg=eaddr;break; |
| 828 case 0x7F: /*CLR ext*/ EXTENDED SETBYTE(eaddr,0)CLN CLV SEZ CLC break; | |
| 4 | 829 case 0x80: /*SUBA immediate*/ IMM8 tw=iareg-mem(eaddr); |
| 830 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 831 iareg=tw;break; |
| 4 | 832 case 0x81: /*CMPA immediate*/ IMM8 tw=iareg-mem(eaddr); |
| 833 SETSTATUS(iareg,mem(eaddr),tw) break; | |
| 834 case 0x82: /*SBCA immediate*/ IMM8 tw=iareg-mem(eaddr)-(iccreg&0x01); | |
| 835 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 836 iareg=tw;break; |
| 837 case 0x83: /*SUBD (CMPD CMPU) immediate*/ IMM16 | |
| 838 {unsigned long res,dreg,breg; | |
| 839 if(iflag==2)dreg=iureg;else dreg=GETDREG; | |
| 840 breg=GETWORD(eaddr); | |
| 841 res=dreg-breg; | |
| 842 SETSTATUSD(dreg,breg,res) | |
| 843 if(iflag==0) SETDREG(res) | |
| 844 }break; | |
| 4 | 845 case 0x84: /*ANDA immediate*/ IMM8 iareg=iareg&mem(eaddr);SETNZ8(iareg) |
| 0 | 846 CLV break; |
| 4 | 847 case 0x85: /*BITA immediate*/ IMM8 tb=iareg&mem(eaddr);SETNZ8(tb) |
| 0 | 848 CLV break; |
| 849 case 0x86: /*LDA immediate*/ IMM8 LOADAC(iareg) CLV SETNZ8(iareg) | |
| 850 break; | |
| 851 case 0x87: /*STA immediate (for the sake of orthogonality) */ IMM8 | |
| 852 SETNZ8(iareg) CLV STOREAC(iareg) break; | |
| 4 | 853 case 0x88: /*EORA immediate*/ IMM8 iareg=iareg^mem(eaddr);SETNZ8(iareg) |
| 0 | 854 CLV break; |
| 4 | 855 case 0x89: /*ADCA immediate*/ IMM8 tw=iareg+mem(eaddr)+(iccreg&0x01); |
| 856 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 857 iareg=tw;break; |
| 4 | 858 case 0x8A: /*ORA immediate*/ IMM8 iareg=iareg|mem(eaddr);SETNZ8(iareg) |
| 0 | 859 CLV break; |
| 4 | 860 case 0x8B: /*ADDA immediate*/ IMM8 tw=iareg+mem(eaddr); |
| 861 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 862 iareg=tw;break; |
| 863 case 0x8C: /*CMPX (CMPY CMPS) immediate */ IMM16 | |
| 864 {unsigned long dreg,breg,res; | |
| 865 if(iflag==0)dreg=ixreg;else if(iflag==1) | |
| 866 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr); | |
| 867 res=dreg-breg; | |
| 868 SETSTATUSD(dreg,breg,res) | |
| 869 }break; | |
| 870 case 0x8D: /*BSR */ IMMBYTE(tb) PUSHWORD(ipcreg) ipcreg+=SIGNED(tb); | |
| 871 break; | |
| 872 case 0x8E: /* LDX (LDY) immediate */ IMM16 tw=GETWORD(eaddr); | |
| 873 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else | |
| 874 iyreg=tw;break; | |
| 875 case 0x8F: /* STX (STY) immediate (orthogonality) */ IMM16 | |
| 876 if(!iflag) tw=ixreg; else tw=iyreg; | |
| 877 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
| 4 | 878 case 0x90: /*SUBA direct*/ DIRECT tw=iareg-mem(eaddr); |
| 879 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 880 iareg=tw;break; |
| 4 | 881 case 0x91: /*CMPA direct*/ DIRECT tw=iareg-mem(eaddr); |
| 882 SETSTATUS(iareg,mem(eaddr),tw) break; | |
| 883 case 0x92: /*SBCA direct*/ DIRECT tw=iareg-mem(eaddr)-(iccreg&0x01); | |
| 884 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 885 iareg=tw;break; |
| 886 case 0x93: /*SUBD (CMPD CMPU) direct*/ DIRECT | |
| 887 {unsigned long res,dreg,breg; | |
| 888 if(iflag==2)dreg=iureg;else dreg=GETDREG; | |
| 889 breg=GETWORD(eaddr); | |
| 890 res=dreg-breg; | |
| 891 SETSTATUSD(dreg,breg,res) | |
| 892 if(iflag==0) SETDREG(res) | |
| 893 }break; | |
| 4 | 894 case 0x94: /*ANDA direct*/ DIRECT iareg=iareg&mem(eaddr);SETNZ8(iareg) |
| 0 | 895 CLV break; |
| 4 | 896 case 0x95: /*BITA direct*/ DIRECT tb=iareg&mem(eaddr);SETNZ8(tb) |
| 0 | 897 CLV break; |
| 898 case 0x96: /*LDA direct*/ DIRECT LOADAC(iareg) CLV SETNZ8(iareg) | |
| 899 break; | |
| 900 case 0x97: /*STA direct */ DIRECT | |
| 901 SETNZ8(iareg) CLV STOREAC(iareg) break; | |
| 4 | 902 case 0x98: /*EORA direct*/ DIRECT iareg=iareg^mem(eaddr);SETNZ8(iareg) |
| 0 | 903 CLV break; |
| 4 | 904 case 0x99: /*ADCA direct*/ DIRECT tw=iareg+mem(eaddr)+(iccreg&0x01); |
| 905 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 906 iareg=tw;break; |
| 4 | 907 case 0x9A: /*ORA direct*/ DIRECT iareg=iareg|mem(eaddr);SETNZ8(iareg) |
| 0 | 908 CLV break; |
| 4 | 909 case 0x9B: /*ADDA direct*/ DIRECT tw=iareg+mem(eaddr); |
| 910 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 911 iareg=tw;break; |
| 912 case 0x9C: /*CMPX (CMPY CMPS) direct */ DIRECT | |
| 913 {unsigned long dreg,breg,res; | |
| 914 if(iflag==0)dreg=ixreg;else if(iflag==1) | |
| 915 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr); | |
| 916 res=dreg-breg; | |
| 917 SETSTATUSD(dreg,breg,res) | |
| 918 }break; | |
| 919 case 0x9D: /*JSR direct */ DIRECT PUSHWORD(ipcreg) ipcreg=eaddr; | |
| 920 break; | |
| 921 case 0x9E: /* LDX (LDY) direct */ DIRECT tw=GETWORD(eaddr); | |
| 922 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else | |
| 923 iyreg=tw;break; | |
| 924 case 0x9F: /* STX (STY) direct */ DIRECT | |
| 925 if(!iflag) tw=ixreg; else tw=iyreg; | |
| 926 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
| 4 | 927 case 0xA0: /*SUBA indexed*/ tw=iareg-mem(eaddr); |
| 928 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 929 iareg=tw;break; |
| 4 | 930 case 0xA1: /*CMPA indexed*/ tw=iareg-mem(eaddr); |
| 931 SETSTATUS(iareg,mem(eaddr),tw) break; | |
| 932 case 0xA2: /*SBCA indexed*/ tw=iareg-mem(eaddr)-(iccreg&0x01); | |
| 933 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 934 iareg=tw;break; |
| 935 case 0xA3: /*SUBD (CMPD CMPU) indexed*/ | |
| 936 {unsigned long res,dreg,breg; | |
| 937 if(iflag==2)dreg=iureg;else dreg=GETDREG; | |
| 938 breg=GETWORD(eaddr); | |
| 939 res=dreg-breg; | |
| 940 SETSTATUSD(dreg,breg,res) | |
| 941 if(iflag==0) SETDREG(res) | |
| 942 }break; | |
| 4 | 943 case 0xA4: /*ANDA indexed*/ iareg=iareg&mem(eaddr);SETNZ8(iareg) |
| 0 | 944 CLV break; |
| 4 | 945 case 0xA5: /*BITA indexed*/ tb=iareg&mem(eaddr);SETNZ8(tb) |
| 0 | 946 CLV break; |
| 947 case 0xA6: /*LDA indexed*/ LOADAC(iareg) CLV SETNZ8(iareg) | |
| 948 break; | |
| 949 case 0xA7: /*STA indexed */ | |
| 950 SETNZ8(iareg) CLV STOREAC(iareg) break; | |
| 4 | 951 case 0xA8: /*EORA indexed*/ iareg=iareg^mem(eaddr);SETNZ8(iareg) |
| 0 | 952 CLV break; |
| 4 | 953 case 0xA9: /*ADCA indexed*/ tw=iareg+mem(eaddr)+(iccreg&0x01); |
| 954 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 955 iareg=tw;break; |
| 4 | 956 case 0xAA: /*ORA indexed*/ iareg=iareg|mem(eaddr);SETNZ8(iareg) |
| 0 | 957 CLV break; |
| 4 | 958 case 0xAB: /*ADDA indexed*/ tw=iareg+mem(eaddr); |
| 959 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 960 iareg=tw;break; |
| 961 case 0xAC: /*CMPX (CMPY CMPS) indexed */ | |
| 962 {unsigned long dreg,breg,res; | |
| 963 if(iflag==0)dreg=ixreg;else if(iflag==1) | |
| 964 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr); | |
| 965 res=dreg-breg; | |
| 966 SETSTATUSD(dreg,breg,res) | |
| 967 }break; | |
| 968 case 0xAD: /*JSR indexed */ PUSHWORD(ipcreg) ipcreg=eaddr; | |
| 969 break; | |
| 970 case 0xAE: /* LDX (LDY) indexed */ tw=GETWORD(eaddr); | |
| 971 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else | |
| 972 iyreg=tw;break; | |
| 973 case 0xAF: /* STX (STY) indexed */ | |
| 974 if(!iflag) tw=ixreg; else tw=iyreg; | |
| 975 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
| 4 | 976 case 0xB0: /*SUBA ext*/ EXTENDED tw=iareg-mem(eaddr); |
| 977 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 978 iareg=tw;break; |
| 4 | 979 case 0xB1: /*CMPA ext*/ EXTENDED tw=iareg-mem(eaddr); |
| 980 SETSTATUS(iareg,mem(eaddr),tw) break; | |
| 981 case 0xB2: /*SBCA ext*/ EXTENDED tw=iareg-mem(eaddr)-(iccreg&0x01); | |
| 982 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 983 iareg=tw;break; |
| 984 case 0xB3: /*SUBD (CMPD CMPU) ext*/ EXTENDED | |
| 985 {unsigned long res,dreg,breg; | |
| 986 if(iflag==2)dreg=iureg;else dreg=GETDREG; | |
| 987 breg=GETWORD(eaddr); | |
| 988 res=dreg-breg; | |
| 989 SETSTATUSD(dreg,breg,res) | |
| 990 if(iflag==0) SETDREG(res) | |
| 991 }break; | |
| 4 | 992 case 0xB4: /*ANDA ext*/ EXTENDED iareg=iareg&mem(eaddr);SETNZ8(iareg) |
| 0 | 993 CLV break; |
| 4 | 994 case 0xB5: /*BITA ext*/ EXTENDED tb=iareg&mem(eaddr);SETNZ8(tb) |
| 0 | 995 CLV break; |
| 996 case 0xB6: /*LDA ext*/ EXTENDED LOADAC(iareg) CLV SETNZ8(iareg) | |
| 997 break; | |
| 998 case 0xB7: /*STA ext */ EXTENDED | |
| 999 SETNZ8(iareg) CLV STOREAC(iareg) break; | |
| 4 | 1000 case 0xB8: /*EORA ext*/ EXTENDED iareg=iareg^mem(eaddr);SETNZ8(iareg) |
| 0 | 1001 CLV break; |
| 4 | 1002 case 0xB9: /*ADCA ext*/ EXTENDED tw=iareg+mem(eaddr)+(iccreg&0x01); |
| 1003 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 1004 iareg=tw;break; |
| 4 | 1005 case 0xBA: /*ORA ext*/ EXTENDED iareg=iareg|mem(eaddr);SETNZ8(iareg) |
| 0 | 1006 CLV break; |
| 4 | 1007 case 0xBB: /*ADDA ext*/ EXTENDED tw=iareg+mem(eaddr); |
| 1008 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 1009 iareg=tw;break; |
| 1010 case 0xBC: /*CMPX (CMPY CMPS) ext */ EXTENDED | |
| 1011 {unsigned long dreg,breg,res; | |
| 1012 if(iflag==0)dreg=ixreg;else if(iflag==1) | |
| 1013 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr); | |
| 1014 res=dreg-breg; | |
| 1015 SETSTATUSD(dreg,breg,res) | |
| 1016 }break; | |
| 1017 case 0xBD: /*JSR ext */ EXTENDED PUSHWORD(ipcreg) ipcreg=eaddr; | |
| 1018 break; | |
| 1019 case 0xBE: /* LDX (LDY) ext */ EXTENDED tw=GETWORD(eaddr); | |
| 1020 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else | |
| 1021 iyreg=tw;break; | |
| 1022 case 0xBF: /* STX (STY) ext */ EXTENDED | |
| 1023 if(!iflag) tw=ixreg; else tw=iyreg; | |
| 1024 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
| 4 | 1025 case 0xC0: /*SUBB immediate*/ IMM8 tw=ibreg-mem(eaddr); |
| 1026 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1027 ibreg=tw;break; |
| 4 | 1028 case 0xC1: /*CMPB immediate*/ IMM8 tw=ibreg-mem(eaddr); |
| 1029 SETSTATUS(ibreg,mem(eaddr),tw) break; | |
| 1030 case 0xC2: /*SBCB immediate*/ IMM8 tw=ibreg-mem(eaddr)-(iccreg&0x01); | |
| 1031 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1032 ibreg=tw;break; |
| 1033 case 0xC3: /*ADDD immediate*/ IMM16 | |
| 1034 {unsigned long res,dreg,breg; | |
| 1035 dreg=GETDREG; | |
| 1036 breg=GETWORD(eaddr); | |
| 1037 res=dreg+breg; | |
| 1038 SETSTATUSD(dreg,breg,res) | |
| 1039 SETDREG(res) | |
| 1040 }break; | |
| 4 | 1041 case 0xC4: /*ANDB immediate*/ IMM8 ibreg=ibreg&mem(eaddr);SETNZ8(ibreg) |
| 0 | 1042 CLV break; |
| 4 | 1043 case 0xC5: /*BITB immediate*/ IMM8 tb=ibreg&mem(eaddr);SETNZ8(tb) |
| 0 | 1044 CLV break; |
| 1045 case 0xC6: /*LDB immediate*/ IMM8 LOADAC(ibreg) CLV SETNZ8(ibreg) | |
| 1046 break; | |
| 1047 case 0xC7: /*STB immediate (for the sake of orthogonality) */ IMM8 | |
| 1048 SETNZ8(ibreg) CLV STOREAC(ibreg) break; | |
| 4 | 1049 case 0xC8: /*EORB immediate*/ IMM8 ibreg=ibreg^mem(eaddr);SETNZ8(ibreg) |
| 0 | 1050 CLV break; |
| 4 | 1051 case 0xC9: /*ADCB immediate*/ IMM8 tw=ibreg+mem(eaddr)+(iccreg&0x01); |
| 1052 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1053 ibreg=tw;break; |
| 4 | 1054 case 0xCA: /*ORB immediate*/ IMM8 ibreg=ibreg|mem(eaddr);SETNZ8(ibreg) |
| 0 | 1055 CLV break; |
| 4 | 1056 case 0xCB: /*ADDB immediate*/ IMM8 tw=ibreg+mem(eaddr); |
| 1057 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1058 ibreg=tw;break; |
| 1059 case 0xCC: /*LDD immediate */ IMM16 tw=GETWORD(eaddr);SETNZ16(tw) | |
| 1060 CLV SETDREG(tw) break; | |
| 1061 case 0xCD: /*STD immediate (orthogonality) */ IMM16 | |
| 1062 tw=GETDREG; SETNZ16(tw) CLV | |
| 1063 SETWORD(eaddr,tw) break; | |
| 1064 case 0xCE: /* LDU (LDS) immediate */ IMM16 tw=GETWORD(eaddr); | |
| 1065 CLV SETNZ16(tw) if(!iflag)iureg=tw; else | |
| 1066 isreg=tw;break; | |
| 1067 case 0xCF: /* STU (STS) immediate (orthogonality) */ IMM16 | |
| 1068 if(!iflag) tw=iureg; else tw=isreg; | |
| 1069 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
| 4 | 1070 case 0xD0: /*SUBB direct*/ DIRECT tw=ibreg-mem(eaddr); |
| 1071 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1072 ibreg=tw;break; |
| 4 | 1073 case 0xD1: /*CMPB direct*/ DIRECT tw=ibreg-mem(eaddr); |
| 1074 SETSTATUS(ibreg,mem(eaddr),tw) break; | |
| 1075 case 0xD2: /*SBCB direct*/ DIRECT tw=ibreg-mem(eaddr)-(iccreg&0x01); | |
| 1076 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1077 ibreg=tw;break; |
| 1078 case 0xD3: /*ADDD direct*/ DIRECT | |
| 1079 {unsigned long res,dreg,breg; | |
| 1080 dreg=GETDREG; | |
| 1081 breg=GETWORD(eaddr); | |
| 1082 res=dreg+breg; | |
| 1083 SETSTATUSD(dreg,breg,res) | |
| 1084 SETDREG(res) | |
| 1085 }break; | |
| 4 | 1086 case 0xD4: /*ANDB direct*/ DIRECT ibreg=ibreg&mem(eaddr);SETNZ8(ibreg) |
| 0 | 1087 CLV break; |
| 4 | 1088 case 0xD5: /*BITB direct*/ DIRECT tb=ibreg&mem(eaddr);SETNZ8(tb) |
| 0 | 1089 CLV break; |
| 1090 case 0xD6: /*LDB direct*/ DIRECT LOADAC(ibreg) CLV SETNZ8(ibreg) | |
| 1091 break; | |
| 1092 case 0xD7: /*STB direct */ DIRECT | |
| 1093 SETNZ8(ibreg) CLV STOREAC(ibreg) break; | |
| 4 | 1094 case 0xD8: /*EORB direct*/ DIRECT ibreg=ibreg^mem(eaddr);SETNZ8(ibreg) |
| 0 | 1095 CLV break; |
| 4 | 1096 case 0xD9: /*ADCB direct*/ DIRECT tw=ibreg+mem(eaddr)+(iccreg&0x01); |
| 1097 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1098 ibreg=tw;break; |
| 4 | 1099 case 0xDA: /*ORB direct*/ DIRECT ibreg=ibreg|mem(eaddr);SETNZ8(ibreg) |
| 0 | 1100 CLV break; |
| 4 | 1101 case 0xDB: /*ADDB direct*/ DIRECT tw=ibreg+mem(eaddr); |
| 1102 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1103 ibreg=tw;break; |
| 1104 case 0xDC: /*LDD direct */ DIRECT tw=GETWORD(eaddr);SETNZ16(tw) | |
| 1105 CLV SETDREG(tw) break; | |
| 1106 case 0xDD: /*STD direct */ DIRECT | |
| 1107 tw=GETDREG; SETNZ16(tw) CLV | |
| 1108 SETWORD(eaddr,tw) break; | |
| 1109 case 0xDE: /* LDU (LDS) direct */ DIRECT tw=GETWORD(eaddr); | |
| 1110 CLV SETNZ16(tw) if(!iflag)iureg=tw; else | |
| 1111 isreg=tw;break; | |
| 1112 case 0xDF: /* STU (STS) direct */ DIRECT | |
| 1113 if(!iflag) tw=iureg; else tw=isreg; | |
| 1114 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
| 4 | 1115 case 0xE0: /*SUBB indexed*/ tw=ibreg-mem(eaddr); |
| 1116 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1117 ibreg=tw;break; |
| 4 | 1118 case 0xE1: /*CMPB indexed*/ tw=ibreg-mem(eaddr); |
| 1119 SETSTATUS(ibreg,mem(eaddr),tw) break; | |
| 1120 case 0xE2: /*SBCB indexed*/ tw=ibreg-mem(eaddr)-(iccreg&0x01); | |
| 1121 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1122 ibreg=tw;break; |
| 1123 case 0xE3: /*ADDD indexed*/ | |
| 1124 {unsigned long res,dreg,breg; | |
| 1125 dreg=GETDREG; | |
| 1126 breg=GETWORD(eaddr); | |
| 1127 res=dreg+breg; | |
| 1128 SETSTATUSD(dreg,breg,res) | |
| 1129 SETDREG(res) | |
| 1130 }break; | |
| 4 | 1131 case 0xE4: /*ANDB indexed*/ ibreg=ibreg&mem(eaddr);SETNZ8(ibreg) |
| 0 | 1132 CLV break; |
| 4 | 1133 case 0xE5: /*BITB indexed*/ tb=ibreg&mem(eaddr);SETNZ8(tb) |
| 0 | 1134 CLV break; |
| 1135 case 0xE6: /*LDB indexed*/ LOADAC(ibreg) CLV SETNZ8(ibreg) | |
| 1136 break; | |
| 1137 case 0xE7: /*STB indexed */ | |
| 1138 SETNZ8(ibreg) CLV STOREAC(ibreg) break; | |
| 4 | 1139 case 0xE8: /*EORB indexed*/ ibreg=ibreg^mem(eaddr);SETNZ8(ibreg) |
| 0 | 1140 CLV break; |
| 4 | 1141 case 0xE9: /*ADCB indexed*/ tw=ibreg+mem(eaddr)+(iccreg&0x01); |
| 1142 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1143 ibreg=tw;break; |
| 4 | 1144 case 0xEA: /*ORB indexed*/ ibreg=ibreg|mem(eaddr);SETNZ8(ibreg) |
| 0 | 1145 CLV break; |
| 4 | 1146 case 0xEB: /*ADDB indexed*/ tw=ibreg+mem(eaddr); |
| 1147 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1148 ibreg=tw;break; |
| 1149 case 0xEC: /*LDD indexed */ tw=GETWORD(eaddr);SETNZ16(tw) | |
| 1150 CLV SETDREG(tw) break; | |
| 1151 case 0xED: /*STD indexed */ | |
| 1152 tw=GETDREG; SETNZ16(tw) CLV | |
| 10 | 1153 #ifdef USE_MMU |
| 1154 STOREAC((tw<<8)&0x0ff); eaddr++; | |
| 1155 STOREAC(tw&0x0ff); | |
| 1156 break; | |
| 1157 #else | |
| 0 | 1158 SETWORD(eaddr,tw) break; |
| 10 | 1159 #endif |
| 0 | 1160 case 0xEE: /* LDU (LDS) indexed */ tw=GETWORD(eaddr); |
| 1161 CLV SETNZ16(tw) if(!iflag)iureg=tw; else | |
| 1162 isreg=tw;break; | |
| 1163 case 0xEF: /* STU (STS) indexed */ | |
| 1164 if(!iflag) tw=iureg; else tw=isreg; | |
| 1165 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
| 4 | 1166 case 0xF0: /*SUBB ext*/ EXTENDED tw=ibreg-mem(eaddr); |
| 1167 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1168 ibreg=tw;break; |
| 4 | 1169 case 0xF1: /*CMPB ext*/ EXTENDED tw=ibreg-mem(eaddr); |
| 1170 SETSTATUS(ibreg,mem(eaddr),tw) break; | |
| 1171 case 0xF2: /*SBCB ext*/ EXTENDED tw=ibreg-mem(eaddr)-(iccreg&0x01); | |
| 1172 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1173 ibreg=tw;break; |
| 1174 case 0xF3: /*ADDD ext*/ EXTENDED | |
| 1175 {unsigned long res,dreg,breg; | |
| 1176 dreg=GETDREG; | |
| 1177 breg=GETWORD(eaddr); | |
| 1178 res=dreg+breg; | |
| 1179 SETSTATUSD(dreg,breg,res) | |
| 1180 SETDREG(res) | |
| 1181 }break; | |
| 4 | 1182 case 0xF4: /*ANDB ext*/ EXTENDED ibreg=ibreg&mem(eaddr);SETNZ8(ibreg) |
| 0 | 1183 CLV break; |
| 4 | 1184 case 0xF5: /*BITB ext*/ EXTENDED tb=ibreg&mem(eaddr);SETNZ8(tb) |
| 0 | 1185 CLV break; |
| 1186 case 0xF6: /*LDB ext*/ EXTENDED LOADAC(ibreg) CLV SETNZ8(ibreg) | |
| 1187 break; | |
| 1188 case 0xF7: /*STB ext */ EXTENDED | |
| 1189 SETNZ8(ibreg) CLV STOREAC(ibreg) break; | |
| 4 | 1190 case 0xF8: /*EORB ext*/ EXTENDED ibreg=ibreg^mem(eaddr);SETNZ8(ibreg) |
| 0 | 1191 CLV break; |
| 4 | 1192 case 0xF9: /*ADCB ext*/ EXTENDED tw=ibreg+mem(eaddr)+(iccreg&0x01); |
| 1193 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1194 ibreg=tw;break; |
| 4 | 1195 case 0xFA: /*ORB ext*/ EXTENDED ibreg=ibreg|mem(eaddr);SETNZ8(ibreg) |
| 0 | 1196 CLV break; |
| 4 | 1197 case 0xFB: /*ADDB ext*/ EXTENDED tw=ibreg+mem(eaddr); |
| 1198 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1199 ibreg=tw;break; |
| 1200 case 0xFC: /*LDD ext */ EXTENDED tw=GETWORD(eaddr);SETNZ16(tw) | |
| 1201 CLV SETDREG(tw) break; | |
| 1202 case 0xFD: /*STD ext */ EXTENDED | |
| 1203 tw=GETDREG; SETNZ16(tw) CLV | |
| 10 | 1204 #ifdef USE_MMU |
| 1205 STOREAC((tw<<8)&0x0ff); eaddr++; | |
| 1206 STOREAC(tw&0x0ff); | |
| 1207 break; | |
| 1208 #else | |
| 0 | 1209 SETWORD(eaddr,tw) break; |
| 10 | 1210 #endif |
| 0 | 1211 case 0xFE: /* LDU (LDS) ext */ EXTENDED tw=GETWORD(eaddr); |
| 1212 CLV SETNZ16(tw) if(!iflag)iureg=tw; else | |
| 1213 isreg=tw;break; | |
| 1214 case 0xFF: /* STU (STS) ext */ EXTENDED | |
| 1215 if(!iflag) tw=iureg; else tw=isreg; | |
| 1216 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
| 1217 | |
| 1218 | |
| 1219 } | |
| 1220 } | |
| 1221 } | |
| 1222 |