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annotate src/engine.c @ 191:d0f5894e9b3a default tip
some how load: confilicts in gmake
| author | kono |
|---|---|
| date | Thu, 07 Dec 2023 09:37:15 +0900 |
| parents | f524c0c95559 |
| children |
| rev | line source |
|---|---|
| 0 | 1 /* 6809 Simulator V09. |
| 2 | |
| 3 created 1994,1995 by L.C. Benschop. | |
| 4 copyleft (c) 1994-2014 by the sbc09 team, see AUTHORS for more details. | |
| 5 license: GNU General Public License version 2, see LICENSE for more details. | |
| 6 | |
| 7 This program simulates a 6809 processor. | |
| 8 | |
| 9 System dependencies: short must be 16 bits. | |
| 10 char must be 8 bits. | |
| 11 long must be more than 16 bits. | |
| 12 arrays up to 65536 bytes must be supported. | |
| 13 machine must be twos complement. | |
| 14 Most Unix machines will work. For MSODS you need long pointers | |
| 15 and you may have to malloc() the mem array of 65536 bytes. | |
| 16 | |
| 17 Special instructions: | |
| 18 SWI2 writes char to stdout from register B. | |
| 19 SWI3 reads char from stdout to register B, sets carry at EOF. | |
| 20 (or when no key available when using term control). | |
| 21 SWI retains its normal function. | |
| 22 CWAI and SYNC stop simulator. | |
| 23 Note: special instructions are gone for now. | |
| 24 | |
| 25 ACIA emulation at port $E000 | |
| 26 | |
| 27 Note: BIG_ENDIAN option is no longer needed. | |
| 184 | 28 |
| 29 Implementation notes: | |
| 30 half-carry: | |
| 31 According to Motorola 6809 and Hitachi 6309 Programmer's Reference | |
| 32 half-carry is not defined for ASL, but as an arithmetic operation the | |
| 33 flag behaves like an add operation where the operator is added to itself. | |
| 34 | |
| 35 According to Motorola 6809 and Hitachi 6309 Programmer's Reference | |
| 36 LSR does not influence half-carry. | |
| 37 | |
| 0 | 38 */ |
| 39 | |
| 40 #include <stdio.h> | |
| 41 #include <unistd.h> | |
| 42 | |
| 43 #define engine | |
| 44 #include "v09.h" | |
| 45 | |
| 46 #define USLEEP 1000 | |
| 47 Byte aca,acb; | |
| 48 Byte *breg=&aca,*areg=&acb; | |
| 49 static int tracetrick=0; | |
| 9 | 50 extern long romstart; |
| 0 | 51 |
| 21 | 52 #ifndef USE_MMU |
| 53 | |
| 54 static Byte mem1(Word adr) { | |
| 55 if ((adr&0xfe00)==(IOPAGE&0xfe00)) return do_input(adr&0x1ff); | |
| 56 return mem[adr]; | |
| 57 } | |
| 58 | |
| 59 static void SETBYTE1(Word a,Byte n) { | |
| 60 if ((a&0xfe00)==(IOPAGE&0xfe00)) do_output(a&0x1ff,n); | |
| 61 if(!(a>=romstart))mem[a]=n; | |
| 62 } | |
| 63 #define mem(a) mem1(a) | |
| 64 #define SETBYTE(a,n) SETBYTE1(a,n); | |
| 65 | |
| 66 #else | |
| 67 | |
| 68 int paddr(Word adr, Byte *immu) { | |
| 85 | 69 if ((adr&0xfe00)==(IOPAGE&0xfe00)) return 0x38*0x2000+adr; |
| 21 | 70 return (immu[ (adr) >> 13 ] <<13 ) + ((adr) & 0x1fff ); |
| 71 } | |
| 10 | 72 |
| 11 | 73 Byte * mem0(Byte *iphymem, Word adr, Byte *immu) { |
| 21 | 74 return & iphymem[ paddr(adr,immu) ]; |
| 18 | 75 } |
| 11 | 76 |
| 23 | 77 Byte mem1(Byte *iphymem, Word adr, Byte *immu) { |
| 18 | 78 if ((adr&0xfe00)==(IOPAGE&0xfe00)) return do_input(adr&0x1ff); |
| 11 | 79 Byte *p = mem0(iphymem, adr, immu); |
| 16 | 80 if(!(p-phymem>=rommemsize)) { |
| 11 | 81 return *p; |
| 82 } else { | |
| 83 return 0xff; | |
| 84 } | |
| 85 } | |
| 9 | 86 |
| 11 | 87 #define mem(a) mem1(iphymem,a,immu) |
| 88 | |
| 23 | 89 Byte * SETBYTE1(Word a,Byte n, Byte *iphymem, Byte *immu) { |
| 90 Word adr = a; | |
| 91 if ((adr&0xfe00)==(IOPAGE&0xfe00)) { | |
| 92 do_output(adr&0x1ff,n); | |
| 93 return mmu; | |
| 94 } else { | |
| 95 Byte *p = mem0(iphymem, adr,immu); | |
| 96 if(!(p-phymem>=romstart)) { | |
| 97 *p=n; | |
| 98 } | |
| 99 } | |
| 100 return immu; | |
| 18 | 101 } |
| 11 | 102 |
| 23 | 103 #define SETBYTE(a,n) immu=SETBYTE1(a,n,iphymem,immu); |
| 104 | |
| 11 | 105 #endif |
| 4 | 106 |
| 107 #define GETWORD(a) (mem(a)<<8|mem((a)+1)) | |
| 11 | 108 #define SETWORD(a,n) {Word a1=a;SETBYTE(a1,n>>8);SETBYTE(a1+1,n);} |
| 9 | 109 |
| 11 | 110 /* Macros for load and store of accumulators. Can be modified to check |
| 111 for port addresses */ | |
| 112 // #define LOADAC(reg) if((eaddr&0xff00)!=(IOPAGE&0xff00))reg=mem(eaddr);else\ | |
| 113 // reg=do_input(eaddr&0xff); | |
| 114 // #define STOREAC(reg) if((eaddr&0xff00)!=(IOPAGE&0xff00))SETBYTE(eaddr,reg)else\ | |
| 115 // do_output(eaddr&0xff,reg); | |
| 9 | 116 |
| 0 | 117 /* Two bytes of a word are fetched separately because of |
| 118 the possible wrap-around at address $ffff and alignment | |
| 119 */ | |
| 120 | |
| 4 | 121 #define IMMBYTE(b) b=mem(ipcreg++); |
| 0 | 122 #define IMMWORD(w) {w=GETWORD(ipcreg);ipcreg+=2;} |
| 123 | |
| 124 #define PUSHBYTE(b) {--isreg;SETBYTE(isreg,b)} | |
| 125 #define PUSHWORD(w) {isreg-=2;SETWORD(isreg,w)} | |
| 4 | 126 #define PULLBYTE(b) b=mem(isreg++); |
| 0 | 127 #define PULLWORD(w) {w=GETWORD(isreg);isreg+=2;} |
| 128 #define PSHUBYTE(b) {--iureg;SETBYTE(iureg,b)} | |
| 129 #define PSHUWORD(w) {iureg-=2;SETWORD(iureg,w)} | |
| 4 | 130 #define PULUBYTE(b) b=mem(iureg++); |
| 0 | 131 #define PULUWORD(w) {w=GETWORD(iureg);iureg+=2;} |
| 132 | |
| 133 #define SIGNED(b) ((Word)(b&0x80?b|0xff00:b)) | |
| 134 | |
| 135 #define GETDREG ((iareg<<8)|ibreg) | |
| 136 #define SETDREG(n) {iareg=(n)>>8;ibreg=(n);} | |
| 137 | |
| 138 /* Macros for addressing modes (postbytes have their own code) */ | |
| 139 #define DIRECT {IMMBYTE(eaddr) eaddr|=(idpreg<<8);} | |
| 140 #define IMM8 {eaddr=ipcreg++;} | |
| 141 #define IMM16 {eaddr=ipcreg;ipcreg+=2;} | |
| 142 #define EXTENDED {IMMWORD(eaddr)} | |
| 143 | |
| 144 /* macros to set status flags */ | |
| 145 #define SEC iccreg|=0x01; | |
| 146 #define CLC iccreg&=0xfe; | |
| 147 #define SEZ iccreg|=0x04; | |
| 148 #define CLZ iccreg&=0xfb; | |
| 149 #define SEN iccreg|=0x08; | |
| 150 #define CLN iccreg&=0xf7; | |
| 151 #define SEV iccreg|=0x02; | |
| 152 #define CLV iccreg&=0xfd; | |
| 153 #define SEH iccreg|=0x20; | |
| 154 #define CLH iccreg&=0xdf; | |
| 155 | |
| 156 /* set N and Z flags depending on 8 or 16 bit result */ | |
| 157 #define SETNZ8(b) {if(b)CLZ else SEZ if(b&0x80)SEN else CLN} | |
| 158 #define SETNZ16(b) {if(b)CLZ else SEZ if(b&0x8000)SEN else CLN} | |
| 159 | |
| 184 | 160 #define SETSTATUS(a,b,res) if((a^b^res^(res>>1))&0x80)SEV else CLV \ |
| 161 if(res&0x100)SEC else CLC SETNZ8((Byte)res) | |
| 162 | |
| 163 #define SETSTATUSH(a,b,res) if((a^b^res)&0x10) SEH else CLH \ | |
| 0 | 164 if((a^b^res^(res>>1))&0x80)SEV else CLV \ |
| 165 if(res&0x100)SEC else CLC SETNZ8((Byte)res) | |
| 166 | |
| 167 #define SETSTATUSD(a,b,res) {if(res&0x10000) SEC else CLC \ | |
| 168 if(((res>>1)^a^b^res)&0x8000) SEV else CLV \ | |
| 169 SETNZ16((Word)res)} | |
| 170 | |
| 171 /* Macros for branch instructions */ | |
| 172 #define BRANCH(f) if(!iflag){IMMBYTE(tb) if(f)ipcreg+=SIGNED(tb);}\ | |
| 173 else{IMMWORD(tw) if(f)ipcreg+=tw;} | |
| 174 #define NXORV ((iccreg&0x08)^((iccreg&0x02)<<2)) | |
| 175 | |
| 184 | 176 /* Macros for setting/getting registers in TFR/EXG instructions */ |
| 177 /* see http://www.6809.org.uk/dragon/illegal-opcodes.shtml */ | |
| 178 /* 8 <-> 16, high byte is filled with $ff! */ | |
| 0 | 179 #define GETREG(val,reg) switch(reg) {\ |
| 180 case 0: val=GETDREG;break;\ | |
| 181 case 1: val=ixreg;break;\ | |
| 182 case 2: val=iyreg;break;\ | |
| 184 | 183 case 3: val=iureg;break;\ |
| 184 case 4: val=isreg;break;\ | |
| 185 case 5: val=ipcreg;break;\ | |
| 186 case 6: val=0xffff;break;\ | |
| 187 case 7: val=0xffff;break;\ | |
| 188 case 8: val=iareg|0xff00;break;\ | |
| 189 case 9: val=ibreg|0xff00;break;\ | |
| 190 case 10: val=iccreg|(iccreg<<8);break;\ | |
| 191 case 11: val=idpreg|(idpreg<<8);break;\ | |
| 192 case 12: val=0xffff;break;\ | |
| 193 case 13: val=0xffff;break;\ | |
| 194 case 14: val=0xffff;break;\ | |
| 195 case 15: val=0xffff;break;} | |
| 0 | 196 |
| 197 #define SETREG(val,reg) switch(reg) {\ | |
| 184 | 198 case 0: SETDREG(val) break;\ |
| 199 case 1: ixreg=val;break;\ | |
| 200 case 2: iyreg=val;break;\ | |
| 201 case 3: iureg=val;break;\ | |
| 202 case 4: isreg=val;break;\ | |
| 203 case 5: ipcreg=val;break;\ | |
| 204 case 6: val=0xffff;break;\ | |
| 205 case 7: val=0xffff;break;\ | |
| 206 case 8: iareg=val&0xff;break;\ | |
| 207 case 9: ibreg=val&0xff;break;\ | |
| 208 case 10: iccreg=val&0xff;break;\ | |
| 209 case 11: idpreg=val&0xff;break;\ | |
| 210 case 12: val=0xffff;break;\ | |
| 211 case 13: val=0xffff;break;\ | |
| 212 case 14: val=0xffff;break;\ | |
| 213 case 15: val=0xffff;break;} | |
| 11 | 214 |
| 215 #define LOADAC(reg) reg=mem(eaddr); | |
| 216 #define STOREAC(reg) SETBYTE(eaddr,reg); | |
| 0 | 217 |
| 218 #define LOADREGS ixreg=xreg;iyreg=yreg;\ | |
| 219 iureg=ureg;isreg=sreg;\ | |
| 220 ipcreg=pcreg;\ | |
| 221 iareg=*areg;ibreg=*breg;\ | |
| 4 | 222 idpreg=dpreg;iccreg=ccreg;immu=mmu; |
| 0 | 223 |
| 224 #define SAVEREGS xreg=ixreg;yreg=iyreg;\ | |
| 225 ureg=iureg;sreg=isreg;\ | |
| 226 pcreg=ipcreg;\ | |
| 227 *areg=iareg;*breg=ibreg;\ | |
| 4 | 228 dpreg=idpreg;ccreg=iccreg;mmu=immu; |
| 0 | 229 |
| 230 | |
| 231 unsigned char haspostbyte[] = { | |
| 232 /*0*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 233 /*1*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 234 /*2*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 235 /*3*/ 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 236 /*4*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 237 /*5*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 238 /*6*/ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, | |
| 239 /*7*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 240 /*8*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 241 /*9*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 242 /*A*/ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, | |
| 243 /*B*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 244 /*C*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 245 /*D*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 246 /*E*/ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, | |
| 247 /*F*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | |
| 248 }; | |
| 249 | |
| 9 | 250 extern char *prog ; |
| 251 | |
| 0 | 252 void interpr(void) |
| 253 { | |
| 254 Word ixreg,iyreg,iureg,isreg,ipcreg; | |
| 255 Byte idpreg,iccreg,iareg,ibreg; | |
| 256 /* Make local variables for the registers. On a real processor (non-Intel) | |
| 257 these could be implemented as fast registers. */ | |
| 258 Word eaddr; /* effective address */ | |
| 259 Byte ireg; /* instruction register */ | |
| 260 Byte iflag; /* flag to indicate $10 or $11 prebyte */ | |
| 261 Byte tb;Word tw; | |
| 4 | 262 Byte *immu = 0; |
| 263 #ifdef USE_MMU | |
| 264 Byte *iphymem = (Byte *)phymem; | |
| 265 #endif | |
| 0 | 266 LOADREGS |
| 267 for(;;){ | |
| 268 if(attention) { | |
| 9 | 269 if(tracing && ipcreg>=tracelo && ipcreg<=tracehi) { |
| 270 SAVEREGS | |
| 271 #ifdef USE_MMU | |
| 18 | 272 Byte *phyadr = mem0(phymem,ipcreg,immu); |
| 273 prog = (char *)(phyadr - ipcreg); | |
| 9 | 274 #endif |
| 275 do_trace(tracefile); | |
| 276 } | |
| 0 | 277 if(irq) { |
| 278 if(irq==1&&!(iccreg&0x10)) { /* standard IRQ */ | |
| 279 PUSHWORD(ipcreg) | |
| 280 PUSHWORD(iureg) | |
| 281 PUSHWORD(iyreg) | |
| 282 PUSHWORD(ixreg) | |
| 283 PUSHBYTE(idpreg) | |
| 284 PUSHBYTE(ibreg) | |
| 285 PUSHBYTE(iareg) | |
| 13 | 286 iccreg|=0x80; |
| 0 | 287 PUSHBYTE(iccreg) |
| 288 iccreg|=0x90; | |
| 289 ipcreg=GETWORD(0xfff8); | |
| 290 } | |
| 291 if(irq==2&&!(iccreg&0x40)) { /* Fast IRQ */ | |
| 292 PUSHWORD(ipcreg) | |
| 13 | 293 iccreg&=0x7f; |
| 0 | 294 PUSHBYTE(iccreg) |
| 295 iccreg|=0x50; | |
| 296 ipcreg=GETWORD(0xfff6); | |
| 297 } | |
| 298 if(!tracing)attention=0; | |
| 299 irq=0; | |
| 300 } | |
| 301 } | |
| 53 | 302 if(escape){ SAVEREGS do_escape(); LOADREGS } |
| 0 | 303 iflag=0; |
| 304 flaginstr: /* $10 and $11 instructions return here */ | |
| 4 | 305 ireg=mem(ipcreg++); |
| 0 | 306 if(haspostbyte[ireg]) { |
| 4 | 307 Byte postbyte=mem(ipcreg++); |
| 0 | 308 switch(postbyte) { |
| 309 case 0x00: eaddr=ixreg;break; | |
| 310 case 0x01: eaddr=ixreg+1;break; | |
| 311 case 0x02: eaddr=ixreg+2;break; | |
| 312 case 0x03: eaddr=ixreg+3;break; | |
| 313 case 0x04: eaddr=ixreg+4;break; | |
| 314 case 0x05: eaddr=ixreg+5;break; | |
| 315 case 0x06: eaddr=ixreg+6;break; | |
| 316 case 0x07: eaddr=ixreg+7;break; | |
| 317 case 0x08: eaddr=ixreg+8;break; | |
| 318 case 0x09: eaddr=ixreg+9;break; | |
| 319 case 0x0A: eaddr=ixreg+10;break; | |
| 320 case 0x0B: eaddr=ixreg+11;break; | |
| 321 case 0x0C: eaddr=ixreg+12;break; | |
| 322 case 0x0D: eaddr=ixreg+13;break; | |
| 323 case 0x0E: eaddr=ixreg+14;break; | |
| 324 case 0x0F: eaddr=ixreg+15;break; | |
| 325 case 0x10: eaddr=ixreg-16;break; | |
| 326 case 0x11: eaddr=ixreg-15;break; | |
| 327 case 0x12: eaddr=ixreg-14;break; | |
| 328 case 0x13: eaddr=ixreg-13;break; | |
| 329 case 0x14: eaddr=ixreg-12;break; | |
| 330 case 0x15: eaddr=ixreg-11;break; | |
| 331 case 0x16: eaddr=ixreg-10;break; | |
| 332 case 0x17: eaddr=ixreg-9;break; | |
| 333 case 0x18: eaddr=ixreg-8;break; | |
| 334 case 0x19: eaddr=ixreg-7;break; | |
| 335 case 0x1A: eaddr=ixreg-6;break; | |
| 336 case 0x1B: eaddr=ixreg-5;break; | |
| 337 case 0x1C: eaddr=ixreg-4;break; | |
| 338 case 0x1D: eaddr=ixreg-3;break; | |
| 339 case 0x1E: eaddr=ixreg-2;break; | |
| 340 case 0x1F: eaddr=ixreg-1;break; | |
| 341 case 0x20: eaddr=iyreg;break; | |
| 342 case 0x21: eaddr=iyreg+1;break; | |
| 343 case 0x22: eaddr=iyreg+2;break; | |
| 344 case 0x23: eaddr=iyreg+3;break; | |
| 345 case 0x24: eaddr=iyreg+4;break; | |
| 346 case 0x25: eaddr=iyreg+5;break; | |
| 347 case 0x26: eaddr=iyreg+6;break; | |
| 348 case 0x27: eaddr=iyreg+7;break; | |
| 349 case 0x28: eaddr=iyreg+8;break; | |
| 350 case 0x29: eaddr=iyreg+9;break; | |
| 351 case 0x2A: eaddr=iyreg+10;break; | |
| 352 case 0x2B: eaddr=iyreg+11;break; | |
| 353 case 0x2C: eaddr=iyreg+12;break; | |
| 354 case 0x2D: eaddr=iyreg+13;break; | |
| 355 case 0x2E: eaddr=iyreg+14;break; | |
| 356 case 0x2F: eaddr=iyreg+15;break; | |
| 357 case 0x30: eaddr=iyreg-16;break; | |
| 358 case 0x31: eaddr=iyreg-15;break; | |
| 359 case 0x32: eaddr=iyreg-14;break; | |
| 360 case 0x33: eaddr=iyreg-13;break; | |
| 361 case 0x34: eaddr=iyreg-12;break; | |
| 362 case 0x35: eaddr=iyreg-11;break; | |
| 363 case 0x36: eaddr=iyreg-10;break; | |
| 364 case 0x37: eaddr=iyreg-9;break; | |
| 365 case 0x38: eaddr=iyreg-8;break; | |
| 366 case 0x39: eaddr=iyreg-7;break; | |
| 367 case 0x3A: eaddr=iyreg-6;break; | |
| 368 case 0x3B: eaddr=iyreg-5;break; | |
| 369 case 0x3C: eaddr=iyreg-4;break; | |
| 370 case 0x3D: eaddr=iyreg-3;break; | |
| 371 case 0x3E: eaddr=iyreg-2;break; | |
| 372 case 0x3F: eaddr=iyreg-1;break; | |
| 373 case 0x40: eaddr=iureg;break; | |
| 374 case 0x41: eaddr=iureg+1;break; | |
| 375 case 0x42: eaddr=iureg+2;break; | |
| 376 case 0x43: eaddr=iureg+3;break; | |
| 377 case 0x44: eaddr=iureg+4;break; | |
| 378 case 0x45: eaddr=iureg+5;break; | |
| 379 case 0x46: eaddr=iureg+6;break; | |
| 380 case 0x47: eaddr=iureg+7;break; | |
| 381 case 0x48: eaddr=iureg+8;break; | |
| 382 case 0x49: eaddr=iureg+9;break; | |
| 383 case 0x4A: eaddr=iureg+10;break; | |
| 384 case 0x4B: eaddr=iureg+11;break; | |
| 385 case 0x4C: eaddr=iureg+12;break; | |
| 386 case 0x4D: eaddr=iureg+13;break; | |
| 387 case 0x4E: eaddr=iureg+14;break; | |
| 388 case 0x4F: eaddr=iureg+15;break; | |
| 389 case 0x50: eaddr=iureg-16;break; | |
| 390 case 0x51: eaddr=iureg-15;break; | |
| 391 case 0x52: eaddr=iureg-14;break; | |
| 392 case 0x53: eaddr=iureg-13;break; | |
| 393 case 0x54: eaddr=iureg-12;break; | |
| 394 case 0x55: eaddr=iureg-11;break; | |
| 395 case 0x56: eaddr=iureg-10;break; | |
| 396 case 0x57: eaddr=iureg-9;break; | |
| 397 case 0x58: eaddr=iureg-8;break; | |
| 398 case 0x59: eaddr=iureg-7;break; | |
| 399 case 0x5A: eaddr=iureg-6;break; | |
| 400 case 0x5B: eaddr=iureg-5;break; | |
| 401 case 0x5C: eaddr=iureg-4;break; | |
| 402 case 0x5D: eaddr=iureg-3;break; | |
| 403 case 0x5E: eaddr=iureg-2;break; | |
| 404 case 0x5F: eaddr=iureg-1;break; | |
| 405 case 0x60: eaddr=isreg;break; | |
| 406 case 0x61: eaddr=isreg+1;break; | |
| 407 case 0x62: eaddr=isreg+2;break; | |
| 408 case 0x63: eaddr=isreg+3;break; | |
| 409 case 0x64: eaddr=isreg+4;break; | |
| 410 case 0x65: eaddr=isreg+5;break; | |
| 411 case 0x66: eaddr=isreg+6;break; | |
| 412 case 0x67: eaddr=isreg+7;break; | |
| 413 case 0x68: eaddr=isreg+8;break; | |
| 414 case 0x69: eaddr=isreg+9;break; | |
| 415 case 0x6A: eaddr=isreg+10;break; | |
| 416 case 0x6B: eaddr=isreg+11;break; | |
| 417 case 0x6C: eaddr=isreg+12;break; | |
| 418 case 0x6D: eaddr=isreg+13;break; | |
| 419 case 0x6E: eaddr=isreg+14;break; | |
| 420 case 0x6F: eaddr=isreg+15;break; | |
| 421 case 0x70: eaddr=isreg-16;break; | |
| 422 case 0x71: eaddr=isreg-15;break; | |
| 423 case 0x72: eaddr=isreg-14;break; | |
| 424 case 0x73: eaddr=isreg-13;break; | |
| 425 case 0x74: eaddr=isreg-12;break; | |
| 426 case 0x75: eaddr=isreg-11;break; | |
| 427 case 0x76: eaddr=isreg-10;break; | |
| 428 case 0x77: eaddr=isreg-9;break; | |
| 429 case 0x78: eaddr=isreg-8;break; | |
| 430 case 0x79: eaddr=isreg-7;break; | |
| 431 case 0x7A: eaddr=isreg-6;break; | |
| 432 case 0x7B: eaddr=isreg-5;break; | |
| 433 case 0x7C: eaddr=isreg-4;break; | |
| 434 case 0x7D: eaddr=isreg-3;break; | |
| 435 case 0x7E: eaddr=isreg-2;break; | |
| 436 case 0x7F: eaddr=isreg-1;break; | |
| 437 case 0x80: eaddr=ixreg;ixreg++;break; | |
| 438 case 0x81: eaddr=ixreg;ixreg+=2;break; | |
| 439 case 0x82: ixreg--;eaddr=ixreg;break; | |
| 440 case 0x83: ixreg-=2;eaddr=ixreg;break; | |
| 441 case 0x84: eaddr=ixreg;break; | |
| 442 case 0x85: eaddr=ixreg+SIGNED(ibreg);break; | |
| 443 case 0x86: eaddr=ixreg+SIGNED(iareg);break; | |
| 444 case 0x87: eaddr=0;break; /*ILELGAL*/ | |
| 445 case 0x88: IMMBYTE(eaddr);eaddr=ixreg+SIGNED(eaddr);break; | |
| 446 case 0x89: IMMWORD(eaddr);eaddr+=ixreg;break; | |
| 447 case 0x8A: eaddr=0;break; /*ILLEGAL*/ | |
| 448 case 0x8B: eaddr=ixreg+GETDREG;break; | |
| 449 case 0x8C: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break; | |
| 450 case 0x8D: IMMWORD(eaddr);eaddr+=ipcreg;break; | |
| 451 case 0x8E: eaddr=0;break; /*ILLEGAL*/ | |
| 452 case 0x8F: IMMWORD(eaddr);break; | |
| 453 case 0x90: eaddr=ixreg;ixreg++;eaddr=GETWORD(eaddr);break; | |
| 454 case 0x91: eaddr=ixreg;ixreg+=2;eaddr=GETWORD(eaddr);break; | |
| 455 case 0x92: ixreg--;eaddr=ixreg;eaddr=GETWORD(eaddr);break; | |
| 456 case 0x93: ixreg-=2;eaddr=ixreg;eaddr=GETWORD(eaddr);break; | |
| 457 case 0x94: eaddr=ixreg;eaddr=GETWORD(eaddr);break; | |
| 458 case 0x95: eaddr=ixreg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break; | |
| 459 case 0x96: eaddr=ixreg+SIGNED(iareg);eaddr=GETWORD(eaddr);break; | |
| 460 case 0x97: eaddr=0;break; /*ILELGAL*/ | |
| 461 case 0x98: IMMBYTE(eaddr);eaddr=ixreg+SIGNED(eaddr); | |
| 462 eaddr=GETWORD(eaddr);break; | |
| 463 case 0x99: IMMWORD(eaddr);eaddr+=ixreg;eaddr=GETWORD(eaddr);break; | |
| 464 case 0x9A: eaddr=0;break; /*ILLEGAL*/ | |
| 465 case 0x9B: eaddr=ixreg+GETDREG;eaddr=GETWORD(eaddr);break; | |
| 466 case 0x9C: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr); | |
| 467 eaddr=GETWORD(eaddr);break; | |
| 468 case 0x9D: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break; | |
| 469 case 0x9E: eaddr=0;break; /*ILLEGAL*/ | |
| 470 case 0x9F: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break; | |
| 471 case 0xA0: eaddr=iyreg;iyreg++;break; | |
| 472 case 0xA1: eaddr=iyreg;iyreg+=2;break; | |
| 473 case 0xA2: iyreg--;eaddr=iyreg;break; | |
| 474 case 0xA3: iyreg-=2;eaddr=iyreg;break; | |
| 475 case 0xA4: eaddr=iyreg;break; | |
| 476 case 0xA5: eaddr=iyreg+SIGNED(ibreg);break; | |
| 477 case 0xA6: eaddr=iyreg+SIGNED(iareg);break; | |
| 478 case 0xA7: eaddr=0;break; /*ILELGAL*/ | |
| 479 case 0xA8: IMMBYTE(eaddr);eaddr=iyreg+SIGNED(eaddr);break; | |
| 480 case 0xA9: IMMWORD(eaddr);eaddr+=iyreg;break; | |
| 481 case 0xAA: eaddr=0;break; /*ILLEGAL*/ | |
| 482 case 0xAB: eaddr=iyreg+GETDREG;break; | |
| 483 case 0xAC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break; | |
| 484 case 0xAD: IMMWORD(eaddr);eaddr+=ipcreg;break; | |
| 485 case 0xAE: eaddr=0;break; /*ILLEGAL*/ | |
| 486 case 0xAF: IMMWORD(eaddr);break; | |
| 487 case 0xB0: eaddr=iyreg;iyreg++;eaddr=GETWORD(eaddr);break; | |
| 488 case 0xB1: eaddr=iyreg;iyreg+=2;eaddr=GETWORD(eaddr);break; | |
| 489 case 0xB2: iyreg--;eaddr=iyreg;eaddr=GETWORD(eaddr);break; | |
| 490 case 0xB3: iyreg-=2;eaddr=iyreg;eaddr=GETWORD(eaddr);break; | |
| 491 case 0xB4: eaddr=iyreg;eaddr=GETWORD(eaddr);break; | |
| 492 case 0xB5: eaddr=iyreg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break; | |
| 493 case 0xB6: eaddr=iyreg+SIGNED(iareg);eaddr=GETWORD(eaddr);break; | |
| 494 case 0xB7: eaddr=0;break; /*ILELGAL*/ | |
| 495 case 0xB8: IMMBYTE(eaddr);eaddr=iyreg+SIGNED(eaddr); | |
| 496 eaddr=GETWORD(eaddr);break; | |
| 497 case 0xB9: IMMWORD(eaddr);eaddr+=iyreg;eaddr=GETWORD(eaddr);break; | |
| 498 case 0xBA: eaddr=0;break; /*ILLEGAL*/ | |
| 499 case 0xBB: eaddr=iyreg+GETDREG;eaddr=GETWORD(eaddr);break; | |
| 500 case 0xBC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr); | |
| 501 eaddr=GETWORD(eaddr);break; | |
| 502 case 0xBD: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break; | |
| 503 case 0xBE: eaddr=0;break; /*ILLEGAL*/ | |
| 504 case 0xBF: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break; | |
| 505 case 0xC0: eaddr=iureg;iureg++;break; | |
| 506 case 0xC1: eaddr=iureg;iureg+=2;break; | |
| 507 case 0xC2: iureg--;eaddr=iureg;break; | |
| 508 case 0xC3: iureg-=2;eaddr=iureg;break; | |
| 509 case 0xC4: eaddr=iureg;break; | |
| 510 case 0xC5: eaddr=iureg+SIGNED(ibreg);break; | |
| 511 case 0xC6: eaddr=iureg+SIGNED(iareg);break; | |
| 512 case 0xC7: eaddr=0;break; /*ILELGAL*/ | |
| 513 case 0xC8: IMMBYTE(eaddr);eaddr=iureg+SIGNED(eaddr);break; | |
| 514 case 0xC9: IMMWORD(eaddr);eaddr+=iureg;break; | |
| 515 case 0xCA: eaddr=0;break; /*ILLEGAL*/ | |
| 516 case 0xCB: eaddr=iureg+GETDREG;break; | |
| 517 case 0xCC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break; | |
| 518 case 0xCD: IMMWORD(eaddr);eaddr+=ipcreg;break; | |
| 519 case 0xCE: eaddr=0;break; /*ILLEGAL*/ | |
| 520 case 0xCF: IMMWORD(eaddr);break; | |
| 521 case 0xD0: eaddr=iureg;iureg++;eaddr=GETWORD(eaddr);break; | |
| 522 case 0xD1: eaddr=iureg;iureg+=2;eaddr=GETWORD(eaddr);break; | |
| 523 case 0xD2: iureg--;eaddr=iureg;eaddr=GETWORD(eaddr);break; | |
| 524 case 0xD3: iureg-=2;eaddr=iureg;eaddr=GETWORD(eaddr);break; | |
| 525 case 0xD4: eaddr=iureg;eaddr=GETWORD(eaddr);break; | |
| 526 case 0xD5: eaddr=iureg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break; | |
| 527 case 0xD6: eaddr=iureg+SIGNED(iareg);eaddr=GETWORD(eaddr);break; | |
| 528 case 0xD7: eaddr=0;break; /*ILELGAL*/ | |
| 529 case 0xD8: IMMBYTE(eaddr);eaddr=iureg+SIGNED(eaddr); | |
| 530 eaddr=GETWORD(eaddr);break; | |
| 531 case 0xD9: IMMWORD(eaddr);eaddr+=iureg;eaddr=GETWORD(eaddr);break; | |
| 532 case 0xDA: eaddr=0;break; /*ILLEGAL*/ | |
| 533 case 0xDB: eaddr=iureg+GETDREG;eaddr=GETWORD(eaddr);break; | |
| 534 case 0xDC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr); | |
| 535 eaddr=GETWORD(eaddr);break; | |
| 536 case 0xDD: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break; | |
| 537 case 0xDE: eaddr=0;break; /*ILLEGAL*/ | |
| 538 case 0xDF: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break; | |
| 539 case 0xE0: eaddr=isreg;isreg++;break; | |
| 540 case 0xE1: eaddr=isreg;isreg+=2;break; | |
| 541 case 0xE2: isreg--;eaddr=isreg;break; | |
| 542 case 0xE3: isreg-=2;eaddr=isreg;break; | |
| 543 case 0xE4: eaddr=isreg;break; | |
| 544 case 0xE5: eaddr=isreg+SIGNED(ibreg);break; | |
| 545 case 0xE6: eaddr=isreg+SIGNED(iareg);break; | |
| 546 case 0xE7: eaddr=0;break; /*ILELGAL*/ | |
| 547 case 0xE8: IMMBYTE(eaddr);eaddr=isreg+SIGNED(eaddr);break; | |
| 548 case 0xE9: IMMWORD(eaddr);eaddr+=isreg;break; | |
| 549 case 0xEA: eaddr=0;break; /*ILLEGAL*/ | |
| 550 case 0xEB: eaddr=isreg+GETDREG;break; | |
| 551 case 0xEC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break; | |
| 552 case 0xED: IMMWORD(eaddr);eaddr+=ipcreg;break; | |
| 553 case 0xEE: eaddr=0;break; /*ILLEGAL*/ | |
| 554 case 0xEF: IMMWORD(eaddr);break; | |
| 555 case 0xF0: eaddr=isreg;isreg++;eaddr=GETWORD(eaddr);break; | |
| 556 case 0xF1: eaddr=isreg;isreg+=2;eaddr=GETWORD(eaddr);break; | |
| 557 case 0xF2: isreg--;eaddr=isreg;eaddr=GETWORD(eaddr);break; | |
| 558 case 0xF3: isreg-=2;eaddr=isreg;eaddr=GETWORD(eaddr);break; | |
| 559 case 0xF4: eaddr=isreg;eaddr=GETWORD(eaddr);break; | |
| 560 case 0xF5: eaddr=isreg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break; | |
| 561 case 0xF6: eaddr=isreg+SIGNED(iareg);eaddr=GETWORD(eaddr);break; | |
| 562 case 0xF7: eaddr=0;break; /*ILELGAL*/ | |
| 563 case 0xF8: IMMBYTE(eaddr);eaddr=isreg+SIGNED(eaddr); | |
| 564 eaddr=GETWORD(eaddr);break; | |
| 565 case 0xF9: IMMWORD(eaddr);eaddr+=isreg;eaddr=GETWORD(eaddr);break; | |
| 566 case 0xFA: eaddr=0;break; /*ILLEGAL*/ | |
| 567 case 0xFB: eaddr=isreg+GETDREG;eaddr=GETWORD(eaddr);break; | |
| 568 case 0xFC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr); | |
| 569 eaddr=GETWORD(eaddr);break; | |
| 570 case 0xFD: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break; | |
| 571 case 0xFE: eaddr=0;break; /*ILLEGAL*/ | |
| 572 case 0xFF: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break; | |
| 573 } | |
| 574 } | |
| 575 switch(ireg) { | |
| 4 | 576 case 0x00: /*NEG direct*/ DIRECT tw=-mem(eaddr);SETSTATUS(0,mem(eaddr),tw) |
| 0 | 577 SETBYTE(eaddr,tw)break; |
| 578 case 0x01: break;/*ILLEGAL*/ | |
| 579 case 0x02: break;/*ILLEGAL*/ | |
| 4 | 580 case 0x03: /*COM direct*/ DIRECT tb=~mem(eaddr);SETNZ8(tb);SEC CLV |
| 0 | 581 SETBYTE(eaddr,tb)break; |
| 4 | 582 case 0x04: /*LSR direct*/ DIRECT tb=mem(eaddr);if(tb&0x01)SEC else CLC |
| 0 | 583 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb) |
| 584 SETBYTE(eaddr,tb)break; | |
| 585 case 0x05: break;/* ILLEGAL*/ | |
| 586 case 0x06: /*ROR direct*/ DIRECT tb=(iccreg&0x01)<<7; | |
| 4 | 587 if(mem(eaddr)&0x01)SEC else CLC |
| 588 tw=(mem(eaddr)>>1)+tb;SETNZ8(tw) | |
| 0 | 589 SETBYTE(eaddr,tw) |
| 590 break; | |
| 4 | 591 case 0x07: /*ASR direct*/ DIRECT tb=mem(eaddr);if(tb&0x01)SEC else CLC |
| 0 | 592 if(tb&0x10)SEH else CLH tb>>=1; |
| 593 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb) | |
| 594 break; | |
| 4 | 595 case 0x08: /*ASL direct*/ DIRECT tw=mem(eaddr)<<1; |
| 596 SETSTATUS(mem(eaddr),mem(eaddr),tw) | |
| 0 | 597 SETBYTE(eaddr,tw)break; |
| 4 | 598 case 0x09: /*ROL direct*/ DIRECT tb=mem(eaddr);tw=iccreg&0x01; |
| 0 | 599 if(tb&0x80)SEC else CLC |
| 600 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV | |
| 601 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break; | |
| 4 | 602 case 0x0A: /*DEC direct*/ DIRECT tb=mem(eaddr)-1;if(tb==0x7F)SEV else CLV |
| 0 | 603 SETNZ8(tb) SETBYTE(eaddr,tb)break; |
| 604 case 0x0B: break; /*ILLEGAL*/ | |
| 4 | 605 case 0x0C: /*INC direct*/ DIRECT tb=mem(eaddr)+1;if(tb==0x80)SEV else CLV |
| 0 | 606 SETNZ8(tb) SETBYTE(eaddr,tb)break; |
| 4 | 607 case 0x0D: /*TST direct*/ DIRECT tb=mem(eaddr);SETNZ8(tb) break; |
| 0 | 608 case 0x0E: /*JMP direct*/ DIRECT ipcreg=eaddr;break; |
| 609 case 0x0F: /*CLR direct*/ DIRECT SETBYTE(eaddr,0);CLN CLV SEZ CLC break; | |
| 610 case 0x10: /* flag10 */ iflag=1;goto flaginstr; | |
| 611 case 0x11: /* flag11 */ iflag=2;goto flaginstr; | |
| 612 case 0x12: /* NOP */ break; | |
| 613 case 0x13: /* SYNC */ | |
| 614 do usleep(USLEEP); /* Wait for IRQ */ | |
| 615 while(!irq && !attention); | |
| 616 if(iccreg&0x40)tracetrick=1; | |
| 617 break; | |
| 618 case 0x14: break; /*ILLEGAL*/ | |
| 619 case 0x15: break; /*ILLEGAL*/ | |
| 620 case 0x16: /*LBRA*/ IMMWORD(eaddr) ipcreg+=eaddr;break; | |
| 621 case 0x17: /*LBSR*/ IMMWORD(eaddr) PUSHWORD(ipcreg) ipcreg+=eaddr;break; | |
| 622 case 0x18: break; /*ILLEGAL*/ | |
| 623 case 0x19: /* DAA*/ tw=iareg; | |
| 624 if(iccreg&0x20)tw+=6; | |
| 625 if((tw&0x0f)>9)tw+=6; | |
| 626 if(iccreg&0x01)tw+=0x60; | |
| 627 if((tw&0xf0)>0x90)tw+=0x60; | |
| 628 if(tw&0x100)SEC | |
| 629 iareg=tw;break; | |
| 630 case 0x1A: /* ORCC*/ IMMBYTE(tb) iccreg|=tb;break; | |
| 631 case 0x1B: break; /*ILLEGAL*/ | |
| 632 case 0x1C: /* ANDCC*/ IMMBYTE(tb) iccreg&=tb;break; | |
| 633 case 0x1D: /* SEX */ tw=SIGNED(ibreg); SETNZ16(tw) SETDREG(tw) break; | |
| 184 | 634 case 0x1E: /* EXG */ IMMBYTE(tb) { Word t2; |
| 635 GETREG(tw,tb>>4) GETREG(t2,tb&15) | |
| 636 SETREG(t2,tb>>4) SETREG(tw,tb&15) | |
| 637 } | |
| 638 break; | |
| 639 case 0x1F: /* TFR */ IMMBYTE(tb) | |
| 640 GETREG(tw,tb>>4) | |
| 641 SETREG(tw,tb&15) | |
| 642 break; | |
| 0 | 643 case 0x20: /* (L)BRA*/ BRANCH(1) break; |
| 644 case 0x21: /* (L)BRN*/ BRANCH(0) break; | |
| 645 case 0x22: /* (L)BHI*/ BRANCH(!(iccreg&0x05)) break; | |
| 646 case 0x23: /* (L)BLS*/ BRANCH(iccreg&0x05) break; | |
| 647 case 0x24: /* (L)BCC*/ BRANCH(!(iccreg&0x01)) break; | |
| 648 case 0x25: /* (L)BCS*/ BRANCH(iccreg&0x01) break; | |
| 649 case 0x26: /* (L)BNE*/ BRANCH(!(iccreg&0x04)) break; | |
| 650 case 0x27: /* (L)BEQ*/ BRANCH(iccreg&0x04) break; | |
| 651 case 0x28: /* (L)BVC*/ BRANCH(!(iccreg&0x02)) break; | |
| 652 case 0x29: /* (L)BVS*/ BRANCH(iccreg&0x02) break; | |
| 653 case 0x2A: /* (L)BPL*/ BRANCH(!(iccreg&0x08)) break; | |
| 654 case 0x2B: /* (L)BMI*/ BRANCH(iccreg&0x08) break; | |
| 655 case 0x2C: /* (L)BGE*/ BRANCH(!NXORV) break; | |
| 656 case 0x2D: /* (L)BLT*/ BRANCH(NXORV) break; | |
| 657 case 0x2E: /* (L)BGT*/ BRANCH(!(NXORV||iccreg&0x04)) break; | |
| 658 case 0x2F: /* (L)BLE*/ BRANCH(NXORV||iccreg&0x04) break; | |
| 659 case 0x30: /* LEAX*/ ixreg=eaddr; if(ixreg) CLZ else SEZ break; | |
| 660 case 0x31: /* LEAY*/ iyreg=eaddr; if(iyreg) CLZ else SEZ break; | |
| 661 case 0x32: /* LEAS*/ isreg=eaddr;break; | |
| 662 case 0x33: /* LEAU*/ iureg=eaddr;break; | |
| 663 case 0x34: /* PSHS*/ IMMBYTE(tb) | |
| 664 if(tb&0x80)PUSHWORD(ipcreg) | |
| 665 if(tb&0x40)PUSHWORD(iureg) | |
| 666 if(tb&0x20)PUSHWORD(iyreg) | |
| 667 if(tb&0x10)PUSHWORD(ixreg) | |
| 668 if(tb&0x08)PUSHBYTE(idpreg) | |
| 669 if(tb&0x04)PUSHBYTE(ibreg) | |
| 670 if(tb&0x02)PUSHBYTE(iareg) | |
| 671 if(tb&0x01)PUSHBYTE(iccreg) break; | |
| 672 case 0x35: /* PULS*/ IMMBYTE(tb) | |
| 673 if(tb&0x01)PULLBYTE(iccreg) | |
| 674 if(tb&0x02)PULLBYTE(iareg) | |
| 675 if(tb&0x04)PULLBYTE(ibreg) | |
| 676 if(tb&0x08)PULLBYTE(idpreg) | |
| 677 if(tb&0x10)PULLWORD(ixreg) | |
| 678 if(tb&0x20)PULLWORD(iyreg) | |
| 679 if(tb&0x40)PULLWORD(iureg) | |
| 680 if(tb&0x80)PULLWORD(ipcreg) | |
| 681 if(tracetrick&&tb==0xff) { /* Arrange fake FIRQ after next insn | |
| 682 for hardware tracing */ | |
| 683 tracetrick=0; | |
| 684 irq=2; | |
| 685 attention=1; | |
| 686 goto flaginstr; | |
| 687 } | |
| 688 break; | |
| 689 case 0x36: /* PSHU*/ IMMBYTE(tb) | |
| 690 if(tb&0x80)PSHUWORD(ipcreg) | |
| 691 if(tb&0x40)PSHUWORD(isreg) | |
| 692 if(tb&0x20)PSHUWORD(iyreg) | |
| 693 if(tb&0x10)PSHUWORD(ixreg) | |
| 694 if(tb&0x08)PSHUBYTE(idpreg) | |
| 695 if(tb&0x04)PSHUBYTE(ibreg) | |
| 696 if(tb&0x02)PSHUBYTE(iareg) | |
| 697 if(tb&0x01)PSHUBYTE(iccreg) break; | |
| 698 case 0x37: /* PULU*/ IMMBYTE(tb) | |
| 699 if(tb&0x01)PULUBYTE(iccreg) | |
| 700 if(tb&0x02)PULUBYTE(iareg) | |
| 701 if(tb&0x04)PULUBYTE(ibreg) | |
| 702 if(tb&0x08)PULUBYTE(idpreg) | |
| 703 if(tb&0x10)PULUWORD(ixreg) | |
| 704 if(tb&0x20)PULUWORD(iyreg) | |
| 705 if(tb&0x40)PULUWORD(isreg) | |
| 706 if(tb&0x80)PULUWORD(ipcreg) break; | |
| 707 case 0x39: /* RTS*/ PULLWORD(ipcreg) break; | |
| 708 case 0x3A: /* ABX*/ ixreg+=ibreg; break; | |
| 13 | 709 case 0x3B: /* RTI*/ PULLBYTE(iccreg) |
| 710 tb=iccreg&0x80; | |
| 0 | 711 if(tb) |
| 712 { | |
| 713 PULLBYTE(iareg) | |
| 714 PULLBYTE(ibreg) | |
| 715 PULLBYTE(idpreg) | |
| 716 PULLWORD(ixreg) | |
| 717 PULLWORD(iyreg) | |
| 718 PULLWORD(iureg) | |
| 719 } | |
| 720 PULLWORD(ipcreg) break; | |
| 721 case 0x3C: /* CWAI*/ IMMBYTE(tb) | |
| 722 PUSHWORD(ipcreg) | |
| 723 PUSHWORD(iureg) | |
| 724 PUSHWORD(iyreg) | |
| 725 PUSHWORD(ixreg) | |
| 726 PUSHBYTE(idpreg) | |
| 727 PUSHBYTE(ibreg) | |
| 728 PUSHBYTE(iareg) | |
| 729 PUSHBYTE(iccreg) | |
| 730 iccreg&=tb; | |
| 731 iccreg|=0x80; | |
| 732 do usleep(USLEEP); /* Wait for IRQ */ | |
| 733 while(!attention && !((irq==1&&!(iccreg&0x10))||(irq==2&&!(iccreg&0x040)))); | |
| 734 if(irq==1)ipcreg=GETWORD(0xfff8); | |
| 735 else ipcreg=GETWORD(0xfff6); | |
| 736 irq=0; | |
| 737 if(!tracing)attention=0; | |
| 738 break; | |
| 739 case 0x3D: /* MUL*/ tw=iareg*ibreg; if(tw)CLZ else SEZ | |
| 740 if(tw&0x80) SEC else CLC SETDREG(tw) break; | |
| 741 case 0x3E: break; /*ILLEGAL*/ | |
| 742 case 0x3F: /* SWI (SWI2 SWI3)*/ { | |
| 743 PUSHWORD(ipcreg) | |
| 744 PUSHWORD(iureg) | |
| 745 PUSHWORD(iyreg) | |
| 746 PUSHWORD(ixreg) | |
| 747 PUSHBYTE(idpreg) | |
| 748 PUSHBYTE(ibreg) | |
| 749 PUSHBYTE(iareg) | |
| 13 | 750 iccreg|=0x80; |
| 0 | 751 PUSHBYTE(iccreg) |
| 752 if(!iflag)iccreg|=0x50; | |
| 753 switch(iflag) { | |
| 754 case 0:ipcreg=GETWORD(0xfffa);break; | |
| 755 case 1:ipcreg=GETWORD(0xfff4);break; | |
| 756 case 2:ipcreg=GETWORD(0xfff2);break; | |
| 757 } | |
| 758 }break; | |
| 759 case 0x40: /*NEGA*/ tw=-iareg;SETSTATUS(0,iareg,tw) | |
| 760 iareg=tw;break; | |
|
189
f524c0c95559
add instros9 source and break instruction
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents:
184
diff
changeset
|
761 case 0x41: /*ILLEGAL*/ |
|
f524c0c95559
add instros9 source and break instruction
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents:
184
diff
changeset
|
762 SAVEREGS do_escape(); LOADREGS |
|
f524c0c95559
add instros9 source and break instruction
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents:
184
diff
changeset
|
763 break; |
| 0 | 764 case 0x42: break;/*ILLEGAL*/ |
| 765 case 0x43: /*COMA*/ tb=~iareg;SETNZ8(tb);SEC CLV | |
| 766 iareg=tb;break; | |
| 767 case 0x44: /*LSRA*/ tb=iareg;if(tb&0x01)SEC else CLC | |
| 184 | 768 tb>>=1;SETNZ8(tb) |
| 0 | 769 iareg=tb;break; |
| 770 case 0x45: break;/* ILLEGAL*/ | |
| 771 case 0x46: /*RORA*/ tb=(iccreg&0x01)<<7; | |
| 772 if(iareg&0x01)SEC else CLC | |
| 773 iareg=(iareg>>1)+tb;SETNZ8(iareg) | |
| 774 break; | |
| 775 case 0x47: /*ASRA*/ tb=iareg;if(tb&0x01)SEC else CLC | |
| 776 if(tb&0x10)SEH else CLH tb>>=1; | |
| 777 if(tb&0x40)tb|=0x80;iareg=tb;SETNZ8(tb) | |
| 778 break; | |
| 779 case 0x48: /*ASLA*/ tw=iareg<<1; | |
| 184 | 780 SETSTATUSH(iareg,iareg,tw) |
| 0 | 781 iareg=tw;break; |
| 782 case 0x49: /*ROLA*/ tb=iareg;tw=iccreg&0x01; | |
| 783 if(tb&0x80)SEC else CLC | |
| 784 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV | |
| 785 tb=(tb<<1)+tw;SETNZ8(tb) iareg=tb;break; | |
| 786 case 0x4A: /*DECA*/ tb=iareg-1;if(tb==0x7F)SEV else CLV | |
| 787 SETNZ8(tb) iareg=tb;break; | |
| 788 case 0x4B: break; /*ILLEGAL*/ | |
| 789 case 0x4C: /*INCA*/ tb=iareg+1;if(tb==0x80)SEV else CLV | |
| 790 SETNZ8(tb) iareg=tb;break; | |
| 791 case 0x4D: /*TSTA*/ SETNZ8(iareg) break; | |
| 792 case 0x4E: break; /*ILLEGAL*/ | |
| 793 case 0x4F: /*CLRA*/ iareg=0;CLN CLV SEZ CLC break; | |
| 794 case 0x50: /*NEGB*/ tw=-ibreg;SETSTATUS(0,ibreg,tw) | |
| 795 ibreg=tw;break; | |
| 796 case 0x51: break;/*ILLEGAL*/ | |
| 797 case 0x52: break;/*ILLEGAL*/ | |
| 798 case 0x53: /*COMB*/ tb=~ibreg;SETNZ8(tb);SEC CLV | |
| 799 ibreg=tb;break; | |
| 800 case 0x54: /*LSRB*/ tb=ibreg;if(tb&0x01)SEC else CLC | |
| 184 | 801 tb>>=1;SETNZ8(tb) |
| 0 | 802 ibreg=tb;break; |
| 803 case 0x55: break;/* ILLEGAL*/ | |
| 804 case 0x56: /*RORB*/ tb=(iccreg&0x01)<<7; | |
| 805 if(ibreg&0x01)SEC else CLC | |
| 806 ibreg=(ibreg>>1)+tb;SETNZ8(ibreg) | |
| 807 break; | |
| 808 case 0x57: /*ASRB*/ tb=ibreg;if(tb&0x01)SEC else CLC | |
| 184 | 809 tb>>=1; |
| 0 | 810 if(tb&0x40)tb|=0x80;ibreg=tb;SETNZ8(tb) |
| 811 break; | |
| 812 case 0x58: /*ASLB*/ tw=ibreg<<1; | |
| 184 | 813 SETSTATUSH(ibreg,ibreg,tw) |
| 0 | 814 ibreg=tw;break; |
| 815 case 0x59: /*ROLB*/ tb=ibreg;tw=iccreg&0x01; | |
| 816 if(tb&0x80)SEC else CLC | |
| 817 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV | |
| 818 tb=(tb<<1)+tw;SETNZ8(tb) ibreg=tb;break; | |
| 819 case 0x5A: /*DECB*/ tb=ibreg-1;if(tb==0x7F)SEV else CLV | |
| 820 SETNZ8(tb) ibreg=tb;break; | |
| 821 case 0x5B: break; /*ILLEGAL*/ | |
| 822 case 0x5C: /*INCB*/ tb=ibreg+1;if(tb==0x80)SEV else CLV | |
| 823 SETNZ8(tb) ibreg=tb;break; | |
| 824 case 0x5D: /*TSTB*/ SETNZ8(ibreg) break; | |
| 825 case 0x5E: break; /*ILLEGAL*/ | |
| 826 case 0x5F: /*CLRB*/ ibreg=0;CLN CLV SEZ CLC break; | |
| 4 | 827 case 0x60: /*NEG indexed*/ tw=-mem(eaddr);SETSTATUS(0,mem(eaddr),tw) |
| 0 | 828 SETBYTE(eaddr,tw)break; |
| 829 case 0x61: break;/*ILLEGAL*/ | |
| 830 case 0x62: break;/*ILLEGAL*/ | |
| 4 | 831 case 0x63: /*COM indexed*/ tb=~mem(eaddr);SETNZ8(tb);SEC CLV |
| 0 | 832 SETBYTE(eaddr,tb)break; |
| 4 | 833 case 0x64: /*LSR indexed*/ tb=mem(eaddr);if(tb&0x01)SEC else CLC |
| 0 | 834 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb) |
| 835 SETBYTE(eaddr,tb)break; | |
| 836 case 0x65: break;/* ILLEGAL*/ | |
| 837 case 0x66: /*ROR indexed*/ tb=(iccreg&0x01)<<7; | |
| 4 | 838 if(mem(eaddr)&0x01)SEC else CLC |
| 839 tw=(mem(eaddr)>>1)+tb;SETNZ8(tw) | |
| 0 | 840 SETBYTE(eaddr,tw) |
| 841 break; | |
| 4 | 842 case 0x67: /*ASR indexed*/ tb=mem(eaddr);if(tb&0x01)SEC else CLC |
| 0 | 843 if(tb&0x10)SEH else CLH tb>>=1; |
| 844 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb) | |
| 845 break; | |
| 4 | 846 case 0x68: /*ASL indexed*/ tw=mem(eaddr)<<1; |
| 847 SETSTATUS(mem(eaddr),mem(eaddr),tw) | |
| 0 | 848 SETBYTE(eaddr,tw)break; |
| 4 | 849 case 0x69: /*ROL indexed*/ tb=mem(eaddr);tw=iccreg&0x01; |
| 0 | 850 if(tb&0x80)SEC else CLC |
| 851 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV | |
| 852 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break; | |
| 4 | 853 case 0x6A: /*DEC indexed*/ tb=mem(eaddr)-1;if(tb==0x7F)SEV else CLV |
| 0 | 854 SETNZ8(tb) SETBYTE(eaddr,tb)break; |
| 855 case 0x6B: break; /*ILLEGAL*/ | |
| 4 | 856 case 0x6C: /*INC indexed*/ tb=mem(eaddr)+1;if(tb==0x80)SEV else CLV |
| 0 | 857 SETNZ8(tb) SETBYTE(eaddr,tb)break; |
| 4 | 858 case 0x6D: /*TST indexed*/ tb=mem(eaddr);SETNZ8(tb) break; |
| 0 | 859 case 0x6E: /*JMP indexed*/ ipcreg=eaddr;break; |
| 860 case 0x6F: /*CLR indexed*/ SETBYTE(eaddr,0)CLN CLV SEZ CLC break; | |
| 4 | 861 case 0x70: /*NEG ext*/ EXTENDED tw=-mem(eaddr);SETSTATUS(0,mem(eaddr),tw) |
| 0 | 862 SETBYTE(eaddr,tw)break; |
| 863 case 0x71: break;/*ILLEGAL*/ | |
| 864 case 0x72: break;/*ILLEGAL*/ | |
| 4 | 865 case 0x73: /*COM ext*/ EXTENDED tb=~mem(eaddr);SETNZ8(tb);SEC CLV |
| 0 | 866 SETBYTE(eaddr,tb)break; |
| 4 | 867 case 0x74: /*LSR ext*/ EXTENDED tb=mem(eaddr);if(tb&0x01)SEC else CLC |
| 0 | 868 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb) |
| 869 SETBYTE(eaddr,tb)break; | |
| 870 case 0x75: break;/* ILLEGAL*/ | |
| 871 case 0x76: /*ROR ext*/ EXTENDED tb=(iccreg&0x01)<<7; | |
| 4 | 872 if(mem(eaddr)&0x01)SEC else CLC |
| 873 tw=(mem(eaddr)>>1)+tb;SETNZ8(tw) | |
| 0 | 874 SETBYTE(eaddr,tw) |
| 875 break; | |
| 4 | 876 case 0x77: /*ASR ext*/ EXTENDED tb=mem(eaddr);if(tb&0x01)SEC else CLC |
| 0 | 877 if(tb&0x10)SEH else CLH tb>>=1; |
| 878 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb) | |
| 879 break; | |
| 4 | 880 case 0x78: /*ASL ext*/ EXTENDED tw=mem(eaddr)<<1; |
| 881 SETSTATUS(mem(eaddr),mem(eaddr),tw) | |
| 0 | 882 SETBYTE(eaddr,tw)break; |
| 4 | 883 case 0x79: /*ROL ext*/ EXTENDED tb=mem(eaddr);tw=iccreg&0x01; |
| 0 | 884 if(tb&0x80)SEC else CLC |
| 885 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV | |
| 886 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break; | |
| 4 | 887 case 0x7A: /*DEC ext*/ EXTENDED tb=mem(eaddr)-1;if(tb==0x7F)SEV else CLV |
| 0 | 888 SETNZ8(tb) SETBYTE(eaddr,tb)break; |
| 889 case 0x7B: break; /*ILLEGAL*/ | |
| 4 | 890 case 0x7C: /*INC ext*/ EXTENDED tb=mem(eaddr)+1;if(tb==0x80)SEV else CLV |
| 0 | 891 SETNZ8(tb) SETBYTE(eaddr,tb)break; |
| 4 | 892 case 0x7D: /*TST ext*/ EXTENDED tb=mem(eaddr);SETNZ8(tb) break; |
| 0 | 893 case 0x7E: /*JMP ext*/ EXTENDED ipcreg=eaddr;break; |
| 894 case 0x7F: /*CLR ext*/ EXTENDED SETBYTE(eaddr,0)CLN CLV SEZ CLC break; | |
| 4 | 895 case 0x80: /*SUBA immediate*/ IMM8 tw=iareg-mem(eaddr); |
| 896 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 897 iareg=tw;break; |
| 4 | 898 case 0x81: /*CMPA immediate*/ IMM8 tw=iareg-mem(eaddr); |
| 899 SETSTATUS(iareg,mem(eaddr),tw) break; | |
| 900 case 0x82: /*SBCA immediate*/ IMM8 tw=iareg-mem(eaddr)-(iccreg&0x01); | |
| 901 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 902 iareg=tw;break; |
| 903 case 0x83: /*SUBD (CMPD CMPU) immediate*/ IMM16 | |
| 904 {unsigned long res,dreg,breg; | |
| 905 if(iflag==2)dreg=iureg;else dreg=GETDREG; | |
| 906 breg=GETWORD(eaddr); | |
| 907 res=dreg-breg; | |
| 908 SETSTATUSD(dreg,breg,res) | |
| 909 if(iflag==0) SETDREG(res) | |
| 910 }break; | |
| 4 | 911 case 0x84: /*ANDA immediate*/ IMM8 iareg=iareg&mem(eaddr);SETNZ8(iareg) |
| 0 | 912 CLV break; |
| 4 | 913 case 0x85: /*BITA immediate*/ IMM8 tb=iareg&mem(eaddr);SETNZ8(tb) |
| 0 | 914 CLV break; |
| 915 case 0x86: /*LDA immediate*/ IMM8 LOADAC(iareg) CLV SETNZ8(iareg) | |
| 916 break; | |
| 917 case 0x87: /*STA immediate (for the sake of orthogonality) */ IMM8 | |
| 918 SETNZ8(iareg) CLV STOREAC(iareg) break; | |
| 4 | 919 case 0x88: /*EORA immediate*/ IMM8 iareg=iareg^mem(eaddr);SETNZ8(iareg) |
| 0 | 920 CLV break; |
| 4 | 921 case 0x89: /*ADCA immediate*/ IMM8 tw=iareg+mem(eaddr)+(iccreg&0x01); |
| 922 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 923 iareg=tw;break; |
| 4 | 924 case 0x8A: /*ORA immediate*/ IMM8 iareg=iareg|mem(eaddr);SETNZ8(iareg) |
| 0 | 925 CLV break; |
| 4 | 926 case 0x8B: /*ADDA immediate*/ IMM8 tw=iareg+mem(eaddr); |
| 927 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 928 iareg=tw;break; |
| 929 case 0x8C: /*CMPX (CMPY CMPS) immediate */ IMM16 | |
| 930 {unsigned long dreg,breg,res; | |
| 931 if(iflag==0)dreg=ixreg;else if(iflag==1) | |
| 932 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr); | |
| 933 res=dreg-breg; | |
| 934 SETSTATUSD(dreg,breg,res) | |
| 935 }break; | |
| 936 case 0x8D: /*BSR */ IMMBYTE(tb) PUSHWORD(ipcreg) ipcreg+=SIGNED(tb); | |
| 937 break; | |
| 938 case 0x8E: /* LDX (LDY) immediate */ IMM16 tw=GETWORD(eaddr); | |
| 939 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else | |
| 940 iyreg=tw;break; | |
| 941 case 0x8F: /* STX (STY) immediate (orthogonality) */ IMM16 | |
| 942 if(!iflag) tw=ixreg; else tw=iyreg; | |
| 943 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
| 4 | 944 case 0x90: /*SUBA direct*/ DIRECT tw=iareg-mem(eaddr); |
| 945 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 946 iareg=tw;break; |
| 4 | 947 case 0x91: /*CMPA direct*/ DIRECT tw=iareg-mem(eaddr); |
| 948 SETSTATUS(iareg,mem(eaddr),tw) break; | |
| 949 case 0x92: /*SBCA direct*/ DIRECT tw=iareg-mem(eaddr)-(iccreg&0x01); | |
| 950 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 951 iareg=tw;break; |
| 952 case 0x93: /*SUBD (CMPD CMPU) direct*/ DIRECT | |
| 953 {unsigned long res,dreg,breg; | |
| 954 if(iflag==2)dreg=iureg;else dreg=GETDREG; | |
| 955 breg=GETWORD(eaddr); | |
| 956 res=dreg-breg; | |
| 957 SETSTATUSD(dreg,breg,res) | |
| 958 if(iflag==0) SETDREG(res) | |
| 959 }break; | |
| 4 | 960 case 0x94: /*ANDA direct*/ DIRECT iareg=iareg&mem(eaddr);SETNZ8(iareg) |
| 0 | 961 CLV break; |
| 4 | 962 case 0x95: /*BITA direct*/ DIRECT tb=iareg&mem(eaddr);SETNZ8(tb) |
| 0 | 963 CLV break; |
| 964 case 0x96: /*LDA direct*/ DIRECT LOADAC(iareg) CLV SETNZ8(iareg) | |
| 965 break; | |
| 966 case 0x97: /*STA direct */ DIRECT | |
| 967 SETNZ8(iareg) CLV STOREAC(iareg) break; | |
| 4 | 968 case 0x98: /*EORA direct*/ DIRECT iareg=iareg^mem(eaddr);SETNZ8(iareg) |
| 0 | 969 CLV break; |
| 4 | 970 case 0x99: /*ADCA direct*/ DIRECT tw=iareg+mem(eaddr)+(iccreg&0x01); |
| 971 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 972 iareg=tw;break; |
| 4 | 973 case 0x9A: /*ORA direct*/ DIRECT iareg=iareg|mem(eaddr);SETNZ8(iareg) |
| 0 | 974 CLV break; |
| 4 | 975 case 0x9B: /*ADDA direct*/ DIRECT tw=iareg+mem(eaddr); |
| 976 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 977 iareg=tw;break; |
| 978 case 0x9C: /*CMPX (CMPY CMPS) direct */ DIRECT | |
| 979 {unsigned long dreg,breg,res; | |
| 980 if(iflag==0)dreg=ixreg;else if(iflag==1) | |
| 981 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr); | |
| 982 res=dreg-breg; | |
| 983 SETSTATUSD(dreg,breg,res) | |
| 984 }break; | |
| 985 case 0x9D: /*JSR direct */ DIRECT PUSHWORD(ipcreg) ipcreg=eaddr; | |
| 986 break; | |
| 987 case 0x9E: /* LDX (LDY) direct */ DIRECT tw=GETWORD(eaddr); | |
| 988 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else | |
| 989 iyreg=tw;break; | |
| 990 case 0x9F: /* STX (STY) direct */ DIRECT | |
| 991 if(!iflag) tw=ixreg; else tw=iyreg; | |
| 992 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
| 4 | 993 case 0xA0: /*SUBA indexed*/ tw=iareg-mem(eaddr); |
| 994 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 995 iareg=tw;break; |
| 4 | 996 case 0xA1: /*CMPA indexed*/ tw=iareg-mem(eaddr); |
| 997 SETSTATUS(iareg,mem(eaddr),tw) break; | |
| 998 case 0xA2: /*SBCA indexed*/ tw=iareg-mem(eaddr)-(iccreg&0x01); | |
| 999 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 1000 iareg=tw;break; |
| 1001 case 0xA3: /*SUBD (CMPD CMPU) indexed*/ | |
| 1002 {unsigned long res,dreg,breg; | |
| 1003 if(iflag==2)dreg=iureg;else dreg=GETDREG; | |
| 1004 breg=GETWORD(eaddr); | |
| 1005 res=dreg-breg; | |
| 1006 SETSTATUSD(dreg,breg,res) | |
| 1007 if(iflag==0) SETDREG(res) | |
| 1008 }break; | |
| 4 | 1009 case 0xA4: /*ANDA indexed*/ iareg=iareg&mem(eaddr);SETNZ8(iareg) |
| 0 | 1010 CLV break; |
| 4 | 1011 case 0xA5: /*BITA indexed*/ tb=iareg&mem(eaddr);SETNZ8(tb) |
| 0 | 1012 CLV break; |
| 1013 case 0xA6: /*LDA indexed*/ LOADAC(iareg) CLV SETNZ8(iareg) | |
| 1014 break; | |
| 1015 case 0xA7: /*STA indexed */ | |
| 1016 SETNZ8(iareg) CLV STOREAC(iareg) break; | |
| 4 | 1017 case 0xA8: /*EORA indexed*/ iareg=iareg^mem(eaddr);SETNZ8(iareg) |
| 0 | 1018 CLV break; |
| 4 | 1019 case 0xA9: /*ADCA indexed*/ tw=iareg+mem(eaddr)+(iccreg&0x01); |
| 1020 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 1021 iareg=tw;break; |
| 4 | 1022 case 0xAA: /*ORA indexed*/ iareg=iareg|mem(eaddr);SETNZ8(iareg) |
| 0 | 1023 CLV break; |
| 4 | 1024 case 0xAB: /*ADDA indexed*/ tw=iareg+mem(eaddr); |
| 1025 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 1026 iareg=tw;break; |
| 1027 case 0xAC: /*CMPX (CMPY CMPS) indexed */ | |
| 1028 {unsigned long dreg,breg,res; | |
| 1029 if(iflag==0)dreg=ixreg;else if(iflag==1) | |
| 1030 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr); | |
| 1031 res=dreg-breg; | |
| 1032 SETSTATUSD(dreg,breg,res) | |
| 1033 }break; | |
| 1034 case 0xAD: /*JSR indexed */ PUSHWORD(ipcreg) ipcreg=eaddr; | |
| 1035 break; | |
| 1036 case 0xAE: /* LDX (LDY) indexed */ tw=GETWORD(eaddr); | |
| 1037 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else | |
| 1038 iyreg=tw;break; | |
| 1039 case 0xAF: /* STX (STY) indexed */ | |
| 1040 if(!iflag) tw=ixreg; else tw=iyreg; | |
| 1041 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
| 4 | 1042 case 0xB0: /*SUBA ext*/ EXTENDED tw=iareg-mem(eaddr); |
| 1043 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 1044 iareg=tw;break; |
| 4 | 1045 case 0xB1: /*CMPA ext*/ EXTENDED tw=iareg-mem(eaddr); |
| 1046 SETSTATUS(iareg,mem(eaddr),tw) break; | |
| 1047 case 0xB2: /*SBCA ext*/ EXTENDED tw=iareg-mem(eaddr)-(iccreg&0x01); | |
| 1048 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 1049 iareg=tw;break; |
| 1050 case 0xB3: /*SUBD (CMPD CMPU) ext*/ EXTENDED | |
| 1051 {unsigned long res,dreg,breg; | |
| 1052 if(iflag==2)dreg=iureg;else dreg=GETDREG; | |
| 1053 breg=GETWORD(eaddr); | |
| 1054 res=dreg-breg; | |
| 1055 SETSTATUSD(dreg,breg,res) | |
| 1056 if(iflag==0) SETDREG(res) | |
| 1057 }break; | |
| 4 | 1058 case 0xB4: /*ANDA ext*/ EXTENDED iareg=iareg&mem(eaddr);SETNZ8(iareg) |
| 0 | 1059 CLV break; |
| 4 | 1060 case 0xB5: /*BITA ext*/ EXTENDED tb=iareg&mem(eaddr);SETNZ8(tb) |
| 0 | 1061 CLV break; |
| 1062 case 0xB6: /*LDA ext*/ EXTENDED LOADAC(iareg) CLV SETNZ8(iareg) | |
| 1063 break; | |
| 1064 case 0xB7: /*STA ext */ EXTENDED | |
| 1065 SETNZ8(iareg) CLV STOREAC(iareg) break; | |
| 4 | 1066 case 0xB8: /*EORA ext*/ EXTENDED iareg=iareg^mem(eaddr);SETNZ8(iareg) |
| 0 | 1067 CLV break; |
| 4 | 1068 case 0xB9: /*ADCA ext*/ EXTENDED tw=iareg+mem(eaddr)+(iccreg&0x01); |
| 1069 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 1070 iareg=tw;break; |
| 4 | 1071 case 0xBA: /*ORA ext*/ EXTENDED iareg=iareg|mem(eaddr);SETNZ8(iareg) |
| 0 | 1072 CLV break; |
| 4 | 1073 case 0xBB: /*ADDA ext*/ EXTENDED tw=iareg+mem(eaddr); |
| 1074 SETSTATUS(iareg,mem(eaddr),tw) | |
| 0 | 1075 iareg=tw;break; |
| 1076 case 0xBC: /*CMPX (CMPY CMPS) ext */ EXTENDED | |
| 1077 {unsigned long dreg,breg,res; | |
| 1078 if(iflag==0)dreg=ixreg;else if(iflag==1) | |
| 1079 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr); | |
| 1080 res=dreg-breg; | |
| 1081 SETSTATUSD(dreg,breg,res) | |
| 1082 }break; | |
| 1083 case 0xBD: /*JSR ext */ EXTENDED PUSHWORD(ipcreg) ipcreg=eaddr; | |
| 1084 break; | |
| 1085 case 0xBE: /* LDX (LDY) ext */ EXTENDED tw=GETWORD(eaddr); | |
| 1086 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else | |
| 1087 iyreg=tw;break; | |
| 1088 case 0xBF: /* STX (STY) ext */ EXTENDED | |
| 1089 if(!iflag) tw=ixreg; else tw=iyreg; | |
| 1090 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
| 4 | 1091 case 0xC0: /*SUBB immediate*/ IMM8 tw=ibreg-mem(eaddr); |
| 1092 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1093 ibreg=tw;break; |
| 4 | 1094 case 0xC1: /*CMPB immediate*/ IMM8 tw=ibreg-mem(eaddr); |
| 1095 SETSTATUS(ibreg,mem(eaddr),tw) break; | |
| 1096 case 0xC2: /*SBCB immediate*/ IMM8 tw=ibreg-mem(eaddr)-(iccreg&0x01); | |
| 1097 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1098 ibreg=tw;break; |
| 1099 case 0xC3: /*ADDD immediate*/ IMM16 | |
| 1100 {unsigned long res,dreg,breg; | |
| 1101 dreg=GETDREG; | |
| 1102 breg=GETWORD(eaddr); | |
| 1103 res=dreg+breg; | |
| 1104 SETSTATUSD(dreg,breg,res) | |
| 1105 SETDREG(res) | |
| 1106 }break; | |
| 4 | 1107 case 0xC4: /*ANDB immediate*/ IMM8 ibreg=ibreg&mem(eaddr);SETNZ8(ibreg) |
| 0 | 1108 CLV break; |
| 4 | 1109 case 0xC5: /*BITB immediate*/ IMM8 tb=ibreg&mem(eaddr);SETNZ8(tb) |
| 0 | 1110 CLV break; |
| 1111 case 0xC6: /*LDB immediate*/ IMM8 LOADAC(ibreg) CLV SETNZ8(ibreg) | |
| 1112 break; | |
| 1113 case 0xC7: /*STB immediate (for the sake of orthogonality) */ IMM8 | |
| 1114 SETNZ8(ibreg) CLV STOREAC(ibreg) break; | |
| 4 | 1115 case 0xC8: /*EORB immediate*/ IMM8 ibreg=ibreg^mem(eaddr);SETNZ8(ibreg) |
| 0 | 1116 CLV break; |
| 4 | 1117 case 0xC9: /*ADCB immediate*/ IMM8 tw=ibreg+mem(eaddr)+(iccreg&0x01); |
| 1118 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1119 ibreg=tw;break; |
| 4 | 1120 case 0xCA: /*ORB immediate*/ IMM8 ibreg=ibreg|mem(eaddr);SETNZ8(ibreg) |
| 0 | 1121 CLV break; |
| 4 | 1122 case 0xCB: /*ADDB immediate*/ IMM8 tw=ibreg+mem(eaddr); |
| 1123 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1124 ibreg=tw;break; |
| 1125 case 0xCC: /*LDD immediate */ IMM16 tw=GETWORD(eaddr);SETNZ16(tw) | |
| 1126 CLV SETDREG(tw) break; | |
| 1127 case 0xCD: /*STD immediate (orthogonality) */ IMM16 | |
| 1128 tw=GETDREG; SETNZ16(tw) CLV | |
| 1129 SETWORD(eaddr,tw) break; | |
| 1130 case 0xCE: /* LDU (LDS) immediate */ IMM16 tw=GETWORD(eaddr); | |
| 1131 CLV SETNZ16(tw) if(!iflag)iureg=tw; else | |
| 1132 isreg=tw;break; | |
| 1133 case 0xCF: /* STU (STS) immediate (orthogonality) */ IMM16 | |
| 1134 if(!iflag) tw=iureg; else tw=isreg; | |
| 1135 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
| 4 | 1136 case 0xD0: /*SUBB direct*/ DIRECT tw=ibreg-mem(eaddr); |
| 1137 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1138 ibreg=tw;break; |
| 4 | 1139 case 0xD1: /*CMPB direct*/ DIRECT tw=ibreg-mem(eaddr); |
| 1140 SETSTATUS(ibreg,mem(eaddr),tw) break; | |
| 1141 case 0xD2: /*SBCB direct*/ DIRECT tw=ibreg-mem(eaddr)-(iccreg&0x01); | |
| 1142 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1143 ibreg=tw;break; |
| 1144 case 0xD3: /*ADDD direct*/ DIRECT | |
| 1145 {unsigned long res,dreg,breg; | |
| 1146 dreg=GETDREG; | |
| 1147 breg=GETWORD(eaddr); | |
| 1148 res=dreg+breg; | |
| 1149 SETSTATUSD(dreg,breg,res) | |
| 1150 SETDREG(res) | |
| 1151 }break; | |
| 4 | 1152 case 0xD4: /*ANDB direct*/ DIRECT ibreg=ibreg&mem(eaddr);SETNZ8(ibreg) |
| 0 | 1153 CLV break; |
| 4 | 1154 case 0xD5: /*BITB direct*/ DIRECT tb=ibreg&mem(eaddr);SETNZ8(tb) |
| 0 | 1155 CLV break; |
| 1156 case 0xD6: /*LDB direct*/ DIRECT LOADAC(ibreg) CLV SETNZ8(ibreg) | |
| 1157 break; | |
| 1158 case 0xD7: /*STB direct */ DIRECT | |
| 1159 SETNZ8(ibreg) CLV STOREAC(ibreg) break; | |
| 4 | 1160 case 0xD8: /*EORB direct*/ DIRECT ibreg=ibreg^mem(eaddr);SETNZ8(ibreg) |
| 0 | 1161 CLV break; |
| 4 | 1162 case 0xD9: /*ADCB direct*/ DIRECT tw=ibreg+mem(eaddr)+(iccreg&0x01); |
| 1163 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1164 ibreg=tw;break; |
| 4 | 1165 case 0xDA: /*ORB direct*/ DIRECT ibreg=ibreg|mem(eaddr);SETNZ8(ibreg) |
| 0 | 1166 CLV break; |
| 4 | 1167 case 0xDB: /*ADDB direct*/ DIRECT tw=ibreg+mem(eaddr); |
| 1168 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1169 ibreg=tw;break; |
| 1170 case 0xDC: /*LDD direct */ DIRECT tw=GETWORD(eaddr);SETNZ16(tw) | |
| 1171 CLV SETDREG(tw) break; | |
| 1172 case 0xDD: /*STD direct */ DIRECT | |
| 1173 tw=GETDREG; SETNZ16(tw) CLV | |
| 11 | 1174 #ifdef USE_MMU |
| 1175 STOREAC((tw>>8)&0x0ff); eaddr++; | |
| 1176 STOREAC(tw&0x0ff); break; | |
| 1177 #else | |
| 0 | 1178 SETWORD(eaddr,tw) break; |
| 11 | 1179 #endif |
| 0 | 1180 case 0xDE: /* LDU (LDS) direct */ DIRECT tw=GETWORD(eaddr); |
| 1181 CLV SETNZ16(tw) if(!iflag)iureg=tw; else | |
| 1182 isreg=tw;break; | |
| 1183 case 0xDF: /* STU (STS) direct */ DIRECT | |
| 1184 if(!iflag) tw=iureg; else tw=isreg; | |
| 1185 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
| 4 | 1186 case 0xE0: /*SUBB indexed*/ tw=ibreg-mem(eaddr); |
| 1187 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1188 ibreg=tw;break; |
| 4 | 1189 case 0xE1: /*CMPB indexed*/ tw=ibreg-mem(eaddr); |
| 1190 SETSTATUS(ibreg,mem(eaddr),tw) break; | |
| 1191 case 0xE2: /*SBCB indexed*/ tw=ibreg-mem(eaddr)-(iccreg&0x01); | |
| 1192 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1193 ibreg=tw;break; |
| 1194 case 0xE3: /*ADDD indexed*/ | |
| 1195 {unsigned long res,dreg,breg; | |
| 1196 dreg=GETDREG; | |
| 1197 breg=GETWORD(eaddr); | |
| 1198 res=dreg+breg; | |
| 1199 SETSTATUSD(dreg,breg,res) | |
| 1200 SETDREG(res) | |
| 1201 }break; | |
| 4 | 1202 case 0xE4: /*ANDB indexed*/ ibreg=ibreg&mem(eaddr);SETNZ8(ibreg) |
| 0 | 1203 CLV break; |
| 4 | 1204 case 0xE5: /*BITB indexed*/ tb=ibreg&mem(eaddr);SETNZ8(tb) |
| 0 | 1205 CLV break; |
| 1206 case 0xE6: /*LDB indexed*/ LOADAC(ibreg) CLV SETNZ8(ibreg) | |
| 1207 break; | |
| 1208 case 0xE7: /*STB indexed */ | |
| 1209 SETNZ8(ibreg) CLV STOREAC(ibreg) break; | |
| 4 | 1210 case 0xE8: /*EORB indexed*/ ibreg=ibreg^mem(eaddr);SETNZ8(ibreg) |
| 0 | 1211 CLV break; |
| 4 | 1212 case 0xE9: /*ADCB indexed*/ tw=ibreg+mem(eaddr)+(iccreg&0x01); |
| 1213 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1214 ibreg=tw;break; |
| 4 | 1215 case 0xEA: /*ORB indexed*/ ibreg=ibreg|mem(eaddr);SETNZ8(ibreg) |
| 0 | 1216 CLV break; |
| 4 | 1217 case 0xEB: /*ADDB indexed*/ tw=ibreg+mem(eaddr); |
| 1218 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1219 ibreg=tw;break; |
| 1220 case 0xEC: /*LDD indexed */ tw=GETWORD(eaddr);SETNZ16(tw) | |
| 1221 CLV SETDREG(tw) break; | |
| 1222 case 0xED: /*STD indexed */ | |
| 1223 tw=GETDREG; SETNZ16(tw) CLV | |
| 10 | 1224 #ifdef USE_MMU |
| 11 | 1225 STOREAC((tw>>8)&0x0ff); eaddr++; |
| 10 | 1226 STOREAC(tw&0x0ff); |
| 1227 break; | |
| 1228 #else | |
| 0 | 1229 SETWORD(eaddr,tw) break; |
| 10 | 1230 #endif |
| 0 | 1231 case 0xEE: /* LDU (LDS) indexed */ tw=GETWORD(eaddr); |
| 1232 CLV SETNZ16(tw) if(!iflag)iureg=tw; else | |
| 1233 isreg=tw;break; | |
| 1234 case 0xEF: /* STU (STS) indexed */ | |
| 1235 if(!iflag) tw=iureg; else tw=isreg; | |
| 1236 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
| 4 | 1237 case 0xF0: /*SUBB ext*/ EXTENDED tw=ibreg-mem(eaddr); |
| 1238 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1239 ibreg=tw;break; |
| 4 | 1240 case 0xF1: /*CMPB ext*/ EXTENDED tw=ibreg-mem(eaddr); |
| 1241 SETSTATUS(ibreg,mem(eaddr),tw) break; | |
| 1242 case 0xF2: /*SBCB ext*/ EXTENDED tw=ibreg-mem(eaddr)-(iccreg&0x01); | |
| 1243 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1244 ibreg=tw;break; |
| 1245 case 0xF3: /*ADDD ext*/ EXTENDED | |
| 1246 {unsigned long res,dreg,breg; | |
| 1247 dreg=GETDREG; | |
| 1248 breg=GETWORD(eaddr); | |
| 1249 res=dreg+breg; | |
| 1250 SETSTATUSD(dreg,breg,res) | |
| 1251 SETDREG(res) | |
| 1252 }break; | |
| 4 | 1253 case 0xF4: /*ANDB ext*/ EXTENDED ibreg=ibreg&mem(eaddr);SETNZ8(ibreg) |
| 0 | 1254 CLV break; |
| 4 | 1255 case 0xF5: /*BITB ext*/ EXTENDED tb=ibreg&mem(eaddr);SETNZ8(tb) |
| 0 | 1256 CLV break; |
| 1257 case 0xF6: /*LDB ext*/ EXTENDED LOADAC(ibreg) CLV SETNZ8(ibreg) | |
| 1258 break; | |
| 1259 case 0xF7: /*STB ext */ EXTENDED | |
| 1260 SETNZ8(ibreg) CLV STOREAC(ibreg) break; | |
| 4 | 1261 case 0xF8: /*EORB ext*/ EXTENDED ibreg=ibreg^mem(eaddr);SETNZ8(ibreg) |
| 0 | 1262 CLV break; |
| 4 | 1263 case 0xF9: /*ADCB ext*/ EXTENDED tw=ibreg+mem(eaddr)+(iccreg&0x01); |
| 1264 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1265 ibreg=tw;break; |
| 4 | 1266 case 0xFA: /*ORB ext*/ EXTENDED ibreg=ibreg|mem(eaddr);SETNZ8(ibreg) |
| 0 | 1267 CLV break; |
| 4 | 1268 case 0xFB: /*ADDB ext*/ EXTENDED tw=ibreg+mem(eaddr); |
| 1269 SETSTATUS(ibreg,mem(eaddr),tw) | |
| 0 | 1270 ibreg=tw;break; |
| 1271 case 0xFC: /*LDD ext */ EXTENDED tw=GETWORD(eaddr);SETNZ16(tw) | |
| 1272 CLV SETDREG(tw) break; | |
| 1273 case 0xFD: /*STD ext */ EXTENDED | |
| 1274 tw=GETDREG; SETNZ16(tw) CLV | |
| 10 | 1275 #ifdef USE_MMU |
| 11 | 1276 STOREAC((tw>>8)&0x0ff); eaddr++; |
| 10 | 1277 STOREAC(tw&0x0ff); |
| 1278 break; | |
| 1279 #else | |
| 0 | 1280 SETWORD(eaddr,tw) break; |
| 10 | 1281 #endif |
| 0 | 1282 case 0xFE: /* LDU (LDS) ext */ EXTENDED tw=GETWORD(eaddr); |
| 1283 CLV SETNZ16(tw) if(!iflag)iureg=tw; else | |
| 1284 isreg=tw;break; | |
| 1285 case 0xFF: /* STU (STS) ext */ EXTENDED | |
| 1286 if(!iflag) tw=iureg; else tw=isreg; | |
| 1287 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; | |
| 1288 | |
| 1289 | |
| 1290 } | |
| 1291 } | |
| 1292 } | |
| 1293 |