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annotate gcc/config/s390/2084.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents f6334be47118
children 84e7813d76e9
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 ;; Scheduling description for z990 (cpu 2084).
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2 ;; Copyright (C) 2003-2017 Free Software Foundation, Inc.
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3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
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4 ;; Ulrich Weigand (uweigand@de.ibm.com).
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5
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6 ;; This file is part of GCC.
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7
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8 ;; GCC is free software; you can redistribute it and/or modify it under
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9 ;; the terms of the GNU General Public License as published by the Free
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10 ;; Software Foundation; either version 3, or (at your option) any later
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11 ;; version.
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12
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13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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14 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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15 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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16 ;; for more details.
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17
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 (define_automaton "x_ipu")
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23
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24 (define_cpu_unit "x_e1_r,x_e1_s,x_e1_t" "x_ipu")
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25 (define_cpu_unit "x_wr_r,x_wr_s,x_wr_t,x_wr_fp" "x_ipu")
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26 (define_cpu_unit "x_s1,x_s2,x_s3,x_s4" "x_ipu")
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27 (define_cpu_unit "x_t1,x_t2,x_t3,x_t4" "x_ipu")
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28 (define_cpu_unit "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6" "x_ipu")
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29 (define_cpu_unit "x_store_tok" "x_ipu")
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30 (define_cpu_unit "x_ms,x_mt" "x_ipu")
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32 (define_reservation "x-e1-st" "(x_e1_s | x_e1_t)")
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33
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34 (define_reservation "x-e1-np" "(x_e1_r + x_e1_s + x_e1_t)")
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36 (absence_set "x_e1_r" "x_e1_s,x_e1_t")
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37 (absence_set "x_e1_s" "x_e1_t")
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38
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39 ;; Try to avoid int <-> fp transitions.
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40
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41 (define_reservation "x-x" "x_s1|x_t1,x_s2|x_t2,x_s3|x_t3,x_s4|x_t4")
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42 (define_reservation "x-f" "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6")
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43 (define_reservation "x-wr-st" "((x_wr_s | x_wr_t),x-x)")
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44 (define_reservation "x-wr-np" "((x_wr_r + x_wr_s + x_wr_t),x-x)")
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45 (define_reservation "x-wr-fp" "x_wr_fp,x-f")
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46 (define_reservation "x-mem" "x_ms|x_mt")
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47
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48 (absence_set "x_wr_fp"
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49 "x_s1,x_s2,x_s3,x_s4,x_t1,x_t2,x_t3,x_t4,x_wr_s,x_wr_t")
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51 (absence_set "x_e1_r,x_wr_r,x_wr_s,x_wr_t"
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52 "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6,x_wr_fp")
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53
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54 ;; Don't have any load type insn in same group as store
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55
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56 (absence_set "x_ms,x_mt" "x_store_tok")
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59 ;;
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60 ;; Simple insns
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61 ;;
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62
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63 (define_insn_reservation "x_int" 1
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64 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
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65 (and (eq_attr "type" "integer")
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66 (eq_attr "atype" "reg")))
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67 "x-e1-st,x-wr-st")
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69 (define_insn_reservation "x_agen" 1
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70 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
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71 (and (eq_attr "type" "integer")
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72 (eq_attr "atype" "agen")))
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73 "x-e1-st,x-wr-st")
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74
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75 (define_insn_reservation "x_lr" 1
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76 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
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77 (eq_attr "type" "lr"))
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78 "x-e1-st,x-wr-st")
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79
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80 (define_insn_reservation "x_la" 1
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81 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
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82 (eq_attr "type" "la"))
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83 "x-e1-st,x-wr-st")
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84
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85 (define_insn_reservation "x_larl" 1
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86 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
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87 (eq_attr "type" "larl"))
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88 "x-e1-st,x-wr-st")
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89
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90 (define_insn_reservation "x_load" 1
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91 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
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92 (eq_attr "type" "load"))
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93 "x-e1-st+x-mem,x-wr-st")
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95 (define_insn_reservation "x_store" 1
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96 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
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97 (eq_attr "type" "store"))
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98 "x-e1-st+x_store_tok,x-wr-st")
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99
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100 (define_insn_reservation "x_branch" 1
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101 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
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102 (eq_attr "type" "branch"))
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103 "x_e1_r,x_wr_r")
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104
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105 (define_insn_reservation "x_call" 5
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106 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
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107 (eq_attr "type" "jsr"))
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108 "x-e1-np*5,x-wr-np")
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109
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110 (define_insn_reservation "x_mul_hi" 2
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111 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
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112 (eq_attr "type" "imulhi"))
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113 "x-e1-np*2,x-wr-np")
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114
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115 (define_insn_reservation "x_mul_sidi" 4
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116 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
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117 (eq_attr "type" "imulsi,imuldi"))
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118 "x-e1-np*4,x-wr-np")
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119
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120 (define_insn_reservation "x_div" 10
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121 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
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122 (eq_attr "type" "idiv"))
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123 "x-e1-np*10,x-wr-np")
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124
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125 (define_insn_reservation "x_sem" 17
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126 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
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127 (eq_attr "type" "sem"))
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128 "x-e1-np+x-mem,x-e1-np*16,x-wr-st")
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129
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130 ;;
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131 ;; Multicycle insns
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132 ;;
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134 (define_insn_reservation "x_cs" 1
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135 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
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136 (eq_attr "type" "cs"))
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137 "x-e1-np,x-wr-np")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
138
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
139 (define_insn_reservation "x_vs" 1
111
kono
parents: 67
diff changeset
140 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
141 (eq_attr "type" "vs"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
142 "x-e1-np*10,x-wr-np")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
143
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
144 (define_insn_reservation "x_stm" 1
111
kono
parents: 67
diff changeset
145 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
146 (eq_attr "type" "stm"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
147 "(x-e1-np+x_store_tok)*10,x-wr-np")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
148
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
149 (define_insn_reservation "x_lm" 1
111
kono
parents: 67
diff changeset
150 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
151 (eq_attr "type" "lm"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
152 "x-e1-np*10,x-wr-np")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
153
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
154 (define_insn_reservation "x_other" 1
111
kono
parents: 67
diff changeset
155 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
156 (eq_attr "type" "other"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
157 "x-e1-np,x-wr-np")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
158
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
159 ;;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
160 ;; Floating point insns
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
161 ;;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
162
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
163 (define_insn_reservation "x_fsimptf" 7
111
kono
parents: 67
diff changeset
164 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
36
855418dad1a3 gcc-4.4-20091020
e075725
parents: 0
diff changeset
165 (eq_attr "type" "fsimptf,fhex"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
166 "x_e1_t*2,x-wr-fp")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
167
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
168 (define_insn_reservation "x_fsimpdf" 6
111
kono
parents: 67
diff changeset
169 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
170 (eq_attr "type" "fsimpdf,fmuldf,fmadddf,fhex"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
171 "x_e1_t,x-wr-fp")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
172
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
173 (define_insn_reservation "x_fsimpsf" 6
111
kono
parents: 67
diff changeset
174 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
175 (eq_attr "type" "fsimpsf,fmulsf,fmaddsf,fhex"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
176 "x_e1_t,x-wr-fp")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
177
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
178
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
179 (define_insn_reservation "x_fmultf" 33
111
kono
parents: 67
diff changeset
180 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
181 (eq_attr "type" "fmultf"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
182 "x_e1_t*27,x-wr-fp")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
183
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
184
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
185 (define_insn_reservation "x_fdivtf" 82
111
kono
parents: 67
diff changeset
186 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
187 (eq_attr "type" "fdivtf,fsqrttf"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
188 "x_e1_t*76,x-wr-fp")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
189
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
190 (define_insn_reservation "x_fdivdf" 36
111
kono
parents: 67
diff changeset
191 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
192 (eq_attr "type" "fdivdf,fsqrtdf"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
193 "x_e1_t*30,x-wr-fp")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
194
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
195 (define_insn_reservation "x_fdivsf" 36
111
kono
parents: 67
diff changeset
196 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
197 (eq_attr "type" "fdivsf,fsqrtsf"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
198 "x_e1_t*30,x-wr-fp")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
199
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
200
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
201 (define_insn_reservation "x_floadtf" 6
111
kono
parents: 67
diff changeset
202 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
203 (eq_attr "type" "floadtf"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
204 "x_e1_t,x-wr-fp")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
205
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
206 (define_insn_reservation "x_floaddf" 6
111
kono
parents: 67
diff changeset
207 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
208 (eq_attr "type" "floaddf"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
209 "x_e1_t,x-wr-fp")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
210
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
211 (define_insn_reservation "x_floadsf" 6
111
kono
parents: 67
diff changeset
212 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
213 (eq_attr "type" "floadsf"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
214 "x_e1_t,x-wr-fp")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
215
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
216
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
217 (define_insn_reservation "x_fstoredf" 1
111
kono
parents: 67
diff changeset
218 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
219 (eq_attr "type" "fstoredf"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
220 "x_e1_t,x-wr-fp")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
221
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
222 (define_insn_reservation "x_fstoresf" 1
111
kono
parents: 67
diff changeset
223 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
224 (eq_attr "type" "fstoresf"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
225 "x_e1_t,x-wr-fp")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
226
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
227
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
228 (define_insn_reservation "x_ftrunctf" 16
111
kono
parents: 67
diff changeset
229 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
230 (eq_attr "type" "ftrunctf"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
231 "x_e1_t*10,x-wr-fp")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
232
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
233 (define_insn_reservation "x_ftruncdf" 11
111
kono
parents: 67
diff changeset
234 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
235 (eq_attr "type" "ftruncdf"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
236 "x_e1_t*5,x-wr-fp")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
237
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
238
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
239 (define_insn_reservation "x_ftoi" 1
111
kono
parents: 67
diff changeset
240 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
241 (eq_attr "type" "ftoi"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
242 "x_e1_t*3,x-wr-fp")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
243
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
244 (define_insn_reservation "x_itof" 7
111
kono
parents: 67
diff changeset
245 (and (eq_attr "cpu" "z990,z9_109,z9_ec")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
246 (eq_attr "type" "itoftf,itofdf,itofsf"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
247 "x_e1_t*3,x-wr-fp")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
248
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
249 (define_bypass 1 "x_fsimpdf" "x_fstoredf")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
250
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
251 (define_bypass 1 "x_fsimpsf" "x_fstoresf")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
252
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
253 (define_bypass 1 "x_floaddf" "x_fsimpdf,x_fstoredf,x_floaddf")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
254
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
255 (define_bypass 1 "x_floadsf" "x_fsimpsf,x_fstoresf,x_floadsf")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
256
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
257 ;;
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
258 ;; s390_agen_dep_p returns 1, if a register is set in the
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
259 ;; first insn and used in the dependent insn to form a address.
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
260 ;;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
261
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
262 ;;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
263 ;; If an instruction uses a register to address memory, it needs
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
264 ;; to be set 5 cycles in advance.
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77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
265 ;;
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
266
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
267 (define_bypass 5 "x_int,x_agen,x_lr"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
268 "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
269 "s390_agen_dep_p")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
270
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 36
diff changeset
271 (define_bypass 9 "x_int,x_agen,x_lr"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
272 "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
273 x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
274 "s390_agen_dep_p")
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275 ;;
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276 ;; A load type instruction uses a bypass to feed the result back
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277 ;; to the address generation pipeline stage.
0
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278 ;;
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279
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280 (define_bypass 4 "x_load"
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281 "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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282 "s390_agen_dep_p")
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283
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284 (define_bypass 5 "x_load"
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285 "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\
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286 x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf"
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287 "s390_agen_dep_p")
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288
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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289 ;;
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290 ;; A load address type instruction uses a bypass to feed the
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291 ;; result back to the address generation pipeline stage.
0
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292 ;;
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293
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294 (define_bypass 3 "x_larl,x_la"
0
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295 "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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296 "s390_agen_dep_p")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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297
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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298 (define_bypass 5 "x_larl, x_la"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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299 "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\
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300 x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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301 "s390_agen_dep_p")
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302
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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303 ;;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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304 ;; Operand forwarding
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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305 ;;
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306
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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307 (define_bypass 0 "x_lr,x_la,x_load" "x_int,x_lr")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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308
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309